coreboot-gerrit March 2019

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Change in ...coreboot[master]: vboot: standardize on working data size
by Joel Kitching (Code Review) 22 Mar '19

22 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31474 Change subject: vboot: standardize on working data size ...................................................................... vboot: standardize on working data size Previously, the size of memory made for vb2_working_data through the macro VBOOT2_WORK was always specified in each individual memlayout file. However, there is effectively no reason to provide this customizability -- the workbuf size required for verifying firmware has never been more than 12K. (This could potentially increase in the future if key sizes or algorithms are changed, but this could be applied globally rather than for each individual platform.) This CL creates a new Kconfig option called VBOOT_WORKING_DATA_SIZE, which is tied to the value provided by vboot2 as VB2_WORKBUF_RECOMMENDED_DATA_SIZE via a _Static_assert in vboot_loader.c BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/arch/x86/car.ld M src/include/memlayout.h M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/vboot_loader.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld 18 files changed, 40 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31474/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6fe8f14..b8d8c03 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -26,11 +26,11 @@ . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; #endif - /* Vboot work buffer is completely volatile outside of verstage and - * romstage. Appropriate code needs to handle the transition. */ -#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) - VBOOT2_WORK(., 16K) -#endif + /* Vboot work buffer only needs to be available when verified boot + * starts in bootblock. */ +#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) + VBOOT2_WORK(.) + #endif /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a8b3a60..4fa1802 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -160,9 +160,8 @@ /* Careful: required work buffer size depends on RW properties such as key size * and algorithm -- what works for you might stop working after an update. Do * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ -#define VBOOT2_WORK(addr, size) \ - REGION(vboot2_work, addr, size, 16) \ - _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); +#define VBOOT2_WORK(addr) \ + REGION(vboot2_work, addr, CONFIG_VBOOT_WORKING_DATA_SIZE, 16) #if ENV_VERSTAGE #define VERSTAGE(addr, sz) \ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a3e9b86..1b34c91 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -92,6 +92,13 @@ memory initialization). This implies that vboot working data is allocated in CBMEM. +config VBOOT_WORKING_DATA_SIZE + int + default 12288 # 12K, must match VB2_WORKBUF_RECOMMENDED_SIZE + help + Size in bytes that should be allocated for verified boot's working + data structure. + config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6c63f7b..d1e2fe4 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -22,7 +22,13 @@ verstage-y += bootmode.c postcar-y += bootmode.c -verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +# When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by the time +# verstage runs. +ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) +verstage-generic-ccopts += -D__PRE_RAM__ +endif + +verstage-generic-ccopts += -D__VERSTAGE__ ramstage-y += gbb.c diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 747644a..c3d065e 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -40,25 +40,16 @@ uint32_t buffer_size; }; -static const size_t vb_work_buf_size = 16 * KiB; - static struct vb2_working_data * const vboot_get_working_data(void) { if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) /* cbmem_add() does a cbmem_find() first. */ - return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb_work_buf_size); + return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, + CONFIG_VBOOT_WORKING_DATA_SIZE); else return (struct vb2_working_data *)_vboot2_work; } -static size_t vb2_working_data_size(void) -{ - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) - return vb_work_buf_size; - else - return _vboot2_work_size; -} - static struct selected_region *vb2_selected_region(void) { struct selected_region *sel_reg = NULL; @@ -86,19 +77,17 @@ void vb2_init_work_context(struct vb2_context *ctx) { struct vb2_working_data *wd; - size_t work_size; /* First initialize the working data region. */ - work_size = vb2_working_data_size(); wd = vboot_get_working_data(); - memset(wd, 0, work_size); + memset(wd, 0, CONFIG_VBOOT_WORKING_DATA_SIZE); /* * vboot prefers 16-byte alignment. This takes away 16 bytes * from the VBOOT2_WORK region, but the vboot devs said that's okay. */ wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - wd->buffer_size = work_size - wd->buffer_offset; + wd->buffer_size = CONFIG_VBOOT_WORKING_DATA_SIZE - wd->buffer_offset; /* Initialize the vb2_context. */ memset(ctx, 0, sizeof(*ctx)); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 75f75b5..7b0b8d8 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -22,6 +22,7 @@ #include <security/vboot/misc.h> #include <security/vboot/symbols.h> #include <security/vboot/vboot_common.h> +#include <vb2_api.h> /* Ensure vboot configuration is valid: */ _Static_assert(IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) + @@ -33,6 +34,8 @@ _Static_assert(!IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) || IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); +_Static_assert(CONFIG_VBOOT_WORKING_DATA_SIZE == VB2_WORKBUF_RECOMMENDED_SIZE, + "working data size must be set to VB2_WORKBUF_RECOMMENDED_SIZE"); /* The stage loading code is compiled and entered from multiple stages. The * helper functions below attempt to provide more clarity on when certain diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 2222617..ab47f1f 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,7 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) - VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) + VBOOT2_WORK(BOOTROM_OFFSET + 0x30000) VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 05042ef..e0a92cf8 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -45,7 +45,7 @@ SRAM_START(0x1a000000) REGION(gram_bootblock, 0x1a000000, 28K, 1) ROMSTAGE(0x1a007000, 60K) - VBOOT2_WORK(0x1a016000, 12K) + VBOOT2_WORK(0x1a016000) PRERAM_CBFS_CACHE(0x1a019000, 48K) SRAM_END(0x1a066000) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 5b92153..3705ca1 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -38,7 +38,7 @@ SRAM_L2C_END(0x00100000) SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) + VBOOT2_WORK(0x00100000) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index a547083..4d065c7 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -28,7 +28,7 @@ SECTIONS { SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) + VBOOT2_WORK(0x00100000) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 615f0563..9907afe 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -29,7 +29,7 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32) PRERAM_CBFS_CACHE(0x40006000, 16K) - VBOOT2_WORK(0x4000A000, 16K) + VBOOT2_WORK(0x4000A000) STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 30K) VERSTAGE(0x40017800, 72K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index d807c06..1521431 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -30,7 +30,7 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 4K) PRERAM_CBFS_CACHE(0x40001000, 36K) - VBOOT2_WORK(0x4000A000, 12K) + VBOOT2_WORK(0x4000A000) #if ENV_ARM64 STACK(0x4000D000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 5e97077..59281cc 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -46,7 +46,7 @@ REGION_START(wifi_imem_1, 0x0A8C0000) BOOTBLOCK(0x0A8C0000, 24K) OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K) - VBOOT2_WORK(0x0A8D6000, 16K) + VBOOT2_WORK(0x0A8D6000) PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K) TIMESTAMP(0x0A8E2000, 1K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 6ff2b77..8ecd924 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -27,7 +27,7 @@ /* DDR(0x2A000000, 48K) */ BOOTBLOCK(0x2A00C000, 24K) OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) - VBOOT2_WORK(0x2A022000, 16K) + VBOOT2_WORK(0x2A022000) PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) TIMESTAMP(0x2A02E000, 1K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 5d99a8e..7a6394e 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -35,7 +35,7 @@ REGION(fw_reserved2, 0x14800000, 0x16000, 4096) BOOTBLOCK(0x14816000, 40K) TTB(0x14820000, 56K) - VBOOT2_WORK(0x1482E000, 16K) + VBOOT2_WORK(0x1482E000) STACK(0x14832000, 16K) TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 6320fad..de957d5 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -32,7 +32,7 @@ TTB(0xFF700000, 16K) BOOTBLOCK(0xFF704004, 20K - 4) PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) - VBOOT2_WORK(0xFF709800, 12K) + VBOOT2_WORK(0xFF709800) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K) PRERAM_CBFS_CACHE(0xFF717000, 1K) TIMESTAMP(0xFF717400, 0x180) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 01e352f..a3581a8 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -35,7 +35,7 @@ /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) BOOTBLOCK(0xFF8D8000, 40K) - VBOOT2_WORK(0XFF8E2000, 12K) + VBOOT2_WORK(0XFF8E2000) TTB(0xFF8E5000, 24K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 4daf2b9..9bdf105 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -32,7 +32,7 @@ /* 32K hole */ TTB(0x2058000, 16K) PRERAM_CBFS_CACHE(0x205C000, 80K) - VBOOT2_WORK(0x2070000, 16K) + VBOOT2_WORK(0x2070000) STACK(0x2074000, 16K) SRAM_END(0x2078000) -- To view, visit https://review.coreboot.org/c/coreboot/+/31474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Gerrit-Change-Number: 31474 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports
by Patrick Georgi (Code Review) 22 Mar '19

22 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31520 ) Change subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports ...................................................................... soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 5 files changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 16a0ef1..0299ded 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -66,6 +66,11 @@ register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "44" register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 5e70481..6f167c2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -41,6 +41,13 @@ register "SlowSlewRateForGt" = "0" register "SlowSlewRateForSa" = "0" register "SlowSlewRateForFivr" = "0" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index df22aff..2714b60 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -45,6 +45,13 @@ register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b4d78f3..5d9c744 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -383,6 +383,21 @@ /* SATA Power Optimizer */ uint8_t satapwroptimize; + + /* Enable or disable eDP device */ + uint8_t DdiPortEdp; + + /* Enable or disable HPD of DDI port B/C/D/F */ + uint8_t DdiPortBHpd; + uint8_t DdiPortCHpd; + uint8_t DdiPortDHpd; + uint8_t DdiPortFHpd; + + /* Enable or disable DDC of DDI port B/C/D/F */ + uint8_t DdiPortBDdc; + uint8_t DdiPortCDdc; + uint8_t DdiPortDDdc; + uint8_t DdiPortFDdc; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 77d82d6..1a3b4fb 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,6 +177,21 @@ params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; + /* eDP device */ + params->DdiPortEdp = config->DdiPortEdp; + + /* HPD of DDI ports */ + params->DdiPortBHpd = config->DdiPortBHpd; + params->DdiPortCHpd = config->DdiPortCHpd; + params->DdiPortDHpd = config->DdiPortDHpd; + params->DdiPortFHpd = config->DdiPortFHpd; + + /* DDC of DDI ports */ + params->DdiPortBDdc = config->DdiPortBDdc; + params->DdiPortCDdc = config->DdiPortCDdc; + params->DdiPortDDdc = config->DdiPortDDdc; + params->DdiPortFDdc = config->DdiPortFDdc; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/31520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Gerrit-Change-Number: 31520 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/lynxpoint: Remove PCI bridge function
by Patrick Georgi (Code Review) 22 Mar '19

22 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31986 ) Change subject: sb/intel/lynxpoint: Remove PCI bridge function ...................................................................... sb/intel/lynxpoint: Remove PCI bridge function Legacy PCI-to-PCI (parallel) bridge 0:1e.0 is no longer supported in these SKUs. Change-Id: I954ee9cf8228c6352743cae968a0dd665865496c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/pci.c 2 files changed, 0 insertions(+), 138 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index c2a49fd..b18e6da 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -18,7 +18,6 @@ ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c -ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sata.c ramstage-y += usb_ehci.c diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c deleted file mode 100644 index 6c26bb8..0000000 --- a/src/southbridge/intel/lynxpoint/pci.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include "pch.h" - -static void pci_init(struct device *dev) -{ - u16 reg16; - u8 reg8; - - printk(BIOS_DEBUG, "PCI init.\n"); - /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); - - /* This device has no interrupt */ - pci_write_config8(dev, INTR, 0xff); - - /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - pci_write_config16(dev, BCTRL, reg16); - - /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, SMLT, reg8); - - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - - /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, PSTS); - //reg16 |= 0xf900; - pci_write_config16(dev, PSTS, reg16); - - reg16 = pci_read_config16(dev, SECSTS); - // reg16 |= 0xf900; - pci_write_config16(dev, SECSTS, reg16); -} - -static void ich_pci_dev_enable_resources(struct device *dev) -{ - const struct pci_operations *ops; - uint16_t command; - - /* Set the subsystem vendor and device id for mainboard devices */ - ops = ops_pci(dev); - if (dev->on_mainboard && ops && ops->set_subsystem) { - printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", - dev_path(dev), - CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); - ops->set_subsystem(dev, - CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); - } - - command = pci_read_config16(dev, PCI_COMMAND); - command |= dev->command; - /* If we write to PCI_COMMAND, on some systems - * this will cause the ROM and APICs not being visible - * anymore. - */ - printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); - pci_write_config16(dev, PCI_COMMAND, command); -} - -static void ich_pci_bus_enable_resources(struct device *dev) -{ - uint16_t ctrl; - /* enable IO in command register if there is VGA card - * connected with (even it does not claim IO resource) - */ - if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) - dev->command |= PCI_COMMAND_IO; - ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ - printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); - - /* This is the reason we need our own pci_bus_enable_resources */ - ich_pci_dev_enable_resources(dev); -} - -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x54, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, 0x54, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - -static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, -}; - -static struct device_operations device_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = ich_pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = &pci_ops, -}; - -static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I954ee9cf8228c6352743cae968a0dd665865496c Gerrit-Change-Number: 31986 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: device/pciexp_device: Add set_subsystem() for pciexp device
by Subrata Banik (Code Review) 22 Mar '19

22 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31950 Change subject: device/pciexp_device: Add set_subsystem() for pciexp device ...................................................................... device/pciexp_device: Add set_subsystem() for pciexp device This patch performs below operations 1. Add new function to perform subsystem programming for PCIE devices. 2. Remove duplicate implementaion of PCIE subsystem programming and refer the same from common pciexp_device.c. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h M src/northbridge/intel/sandybridge/pcie.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/lynxpoint/pcie.c 10 files changed, 23 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31950/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..318f8cd 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -463,9 +463,16 @@ pciexp_enable_ltr(dev); } +void pciexp_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + /** Default device operations for PCI Express bridges */ static struct pci_operations pciexp_bus_ops_pci = { - .set_subsystem = 0, + .set_subsystem = pciexp_set_subsystem, }; struct device_operations default_pciexp_ops_bus = { diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 0f1420a..121b998 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,6 +2,9 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ +/* PCI-E Sub-System ID */ +#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 + enum aspm_type { PCIE_ASPM_NONE = 0, PCIE_ASPM_L0S = 1, @@ -22,4 +25,8 @@ extern struct device_operations default_pciexp_ops_bus; unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); + +void pciexp_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); + #endif /* DEVICE_PCIEXP_H */ diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 16bc314..6ffe2d3 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -65,20 +65,8 @@ } #endif -static void -pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!ven || !device) - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (ven & 0xffff)); -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 32135ee..fdb8782 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,16 +649,6 @@ root_port_commit_config(); } -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) - pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, (device << 16) | vendor); -} - static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ @@ -666,7 +656,7 @@ } static struct pci_operations pcie_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, .set_L1_ss_latency = pcie_set_L1_ss_max_latency, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 0a5e1bf..1c3114b 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -25,8 +25,6 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 -/* PCI-E Sub-System ID */ -#define PCIE_SUBSYSTEM_VENDOR_ID 0x94 static void pch_pcie_init(struct device *dev) { @@ -72,16 +70,9 @@ PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); } -static void pcie_dev_set_subsystem(struct device *dev, - unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, - .set_subsystem = pcie_dev_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 39c53e8..3e2d5fb 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -306,21 +306,8 @@ return NULL; } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 4679ee5..c412927 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -252,22 +252,8 @@ root_port_commit_config(dev); } - -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a36fdc6..fee77ee 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -95,19 +95,6 @@ } } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801ix_config *config = dev->chip_info; @@ -121,7 +108,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index fb90cd9..1f0038f 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -95,19 +95,6 @@ } } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801jx_config *config = dev->chip_info; @@ -121,7 +108,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 695abf2..9479a37 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -727,21 +727,8 @@ root_port_commit_config(); } -static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pciexp_set_subsystem, }; static struct device_operations device_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Gerrit-Change-Number: 31950 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 25

Change in ...coreboot[master]: device/pci_device: Add generic subsystem programming logic
by Subrata Banik (Code Review) 22 Mar '19

22 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31983 Change subject: device/pci_device: Add generic subsystem programming logic ...................................................................... device/pci_device: Add generic subsystem programming logic This patch adds generic log to perform subsystem programming based on header type. Type 0: subsystem offset 0x2C Type 2: subsystem offset 0x40 Type 1: Read CAP ID 0xD to know cap offset start, offset 4 to locate subsystem vendor id. Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/pci_device.c M src/include/device/pci_def.h 2 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31983/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 86c72b8..a1a05a9 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -734,7 +734,26 @@ void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + uint8_t offset; + + /* Header type */ + switch (dev->hdr_type & 0x7f) { + case PCI_HEADER_TYPE_NORMAL: + offset = PCI_SUBSYSTEM_VENDOR_ID; + break; + case PCI_HEADER_TYPE_BRIDGE: + unsigned int cap_offset; + cap_offset = pci_find_capability(dev, PCI_CAP_ID_SSVID); + offset = cap_offset + 4; /* Vendor ID at offset 4 */ + break; + case PCI_HEADER_TYPE_CARDBUS: + offset = PCI_CB_SUBSYSTEM_VENDOR_ID; + break; + default: + return; + } + + pci_write_config32(dev, offset, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index f9ce1a6..bc5bc79 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -198,6 +198,7 @@ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3 Gerrit-Change-Number: 31983 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsys...
by Subrata Banik (Code Review) 22 Mar '19

22 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31982 Change subject: {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() ...................................................................... {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() This patch removes local definitions of sub_system function and make use of common function pci_dev_set_subsystem(). Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/gma.c M src/soc/intel/baytrail/chip.c M src/soc/intel/braswell/chip.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/fsp_baytrail/chip.c M src/soc/intel/fsp_broadwell_de/chip.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/nvidia/mcp55/azalia.c 68 files changed, 68 insertions(+), 837 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31982/1 diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 8c31f7e..6773a72 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -74,15 +74,8 @@ assign_resources(dev->link_list); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index cd900be..06d0fb2 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -172,18 +172,6 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_init(struct device *dev) { } @@ -193,7 +181,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 648aa48..6e54208 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -221,19 +221,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -287,7 +274,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0fd0228..1b2430f 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -499,18 +499,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -558,7 +546,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 9a1df0f..994296a 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,20 +103,8 @@ } } -static void minihd_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations minihd_pci_ops = { - .set_subsystem = minihd_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations minihd_ops = { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ad4563b..63e4f93 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -468,18 +468,6 @@ pci_write_config32(host_dev, DEVEN, deven); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_init(struct device *dev) { u8 bios_reset_cpl, pair; @@ -510,7 +498,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 633b09d..ee656de 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -756,18 +756,6 @@ pci_write_config8(dev, 0xf4, 0xff); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -834,7 +822,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index ce7d292..0b6542f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -192,19 +192,8 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 86fc583..0ed7192 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -624,19 +624,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static void gma_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -704,7 +691,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 8a4f64c..f3f14fd 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -190,19 +190,6 @@ pci_dev_set_resources(dev); } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static void northbridge_dmi_init(struct device *dev) { u32 reg32; @@ -304,7 +291,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 8bacc77..f41dc62 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -305,19 +305,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { struct device *dev = pcidev_on_root(0x2, 0); @@ -361,7 +348,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index d302c52..a8ff773 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -654,18 +654,6 @@ intel_gma_restore_opregion(); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -732,7 +720,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e58a0eb..1980d54 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -286,18 +286,6 @@ } } -static void intel_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void northbridge_dmi_init(struct device *dev) { u32 reg32; @@ -485,7 +473,7 @@ } static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations mc_ops = { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 8de568a..89046bb 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -96,19 +96,6 @@ pci_write_config16(dev_host, D0F0_GGC, ggc); } -static void gma_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { @@ -160,7 +147,7 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 2102637..acac679 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -72,18 +72,6 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = &pci_dev_set_subsystem, }; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e8fd9d1..7617d53 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -380,22 +380,8 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n", - __FILE__, __func__, dev_name(dev), vendor, device); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = &pci_dev_set_subsystem, }; /** diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 6383e15..caff026 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -64,17 +64,6 @@ .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - else - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - (device << 16) | vendor); -} - struct pci_operations broadwell_pci_ops = { - .set_subsystem = &pci_set_subsystem + .set_subsystem = &pci_dev_set_subsystem }; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index 53af617..f29c426 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -33,13 +33,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 68bd60c..b72bf28 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -129,21 +129,8 @@ .final = soc_final }; -static void soc_set_subsystem(struct device *dev, uint32_t vendor, - uint32_t device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | - (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = soc_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; /* diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index c74c847..9e86279 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -74,17 +74,6 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = &pci_dev_set_subsystem, }; diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index 348e1c0..623095c 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -89,18 +89,6 @@ .init = soc_init, }; -static void pci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - struct pci_operations soc_pci_ops = { - .set_subsystem = &pci_set_subsystem, + .set_subsystem = &pci_dev_set_subsystem, }; diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 0cc9efa..8d424b8 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -336,20 +336,8 @@ return "HDEF"; } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index f22be9e..eda16da 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -694,17 +694,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -924,7 +913,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 5731b9b..1670091 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -735,19 +735,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index a6ffe89..9543536 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -738,19 +738,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 3ee0a59..91c87bf 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -234,18 +234,6 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static const char *sata_acpi_name(const struct device *dev) { return "SATA"; @@ -258,7 +246,7 @@ } static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 9083806..4fb7539 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -71,20 +71,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 6cf4c10..8fe3e41 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -84,13 +84,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 07d74e0..85e450d 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -56,20 +56,8 @@ return "XHC"; } -static void xhci_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations xhci_pci_ops = { - .set_subsystem = xhci_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_xhci_ops = { diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 711778e..4118e5f 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -417,17 +417,6 @@ soc_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -448,7 +437,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 3f72a3d..58388a2 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -96,19 +96,8 @@ { } -static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 90b0420..83533f1 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -40,20 +40,8 @@ .read_byte = lsmbus_read_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void rangeley_smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 582c962..f18aedb 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -247,20 +247,8 @@ } } -static void ac97_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations ac97_pci_ops = { - .set_subsystem = ac97_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ac97_audio_ops = { diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 7bf48ef..938dc4e 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -303,20 +303,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index e25eaae..a362372 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -92,20 +92,8 @@ printk(BIOS_DEBUG, "\n"); } -static void ide_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations ide_pci_ops = { - .set_subsystem = ide_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ide_ops = { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 669648b..a1cc45a 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -676,18 +676,6 @@ outb(POST_OS_BOOT, 0x80); } -static void set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -728,7 +716,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index bf473f6..8514b6d 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -200,20 +200,8 @@ pci_write_config32(dev, SATA_IR, reg32); } -static void sata_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 7e95beb..693c2dc 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -81,20 +81,8 @@ .block_write = lsmbus_block_write, }; -static void smbus_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 307b5ac..cd43e03 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -43,20 +43,8 @@ printk(BIOS_DEBUG, "done.\n"); } -static void usb_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations usb_pci_ops = { - .set_subsystem = usb_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index cbefe20..0a94d3b 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -69,13 +69,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index e47f6e0..16350d5 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -287,20 +287,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 79a1a1d..ce47c59 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -527,17 +527,6 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -578,7 +567,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 0e7f35bc..6155c15 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -258,20 +258,8 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index c3d23ea..9bab9b2 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -64,20 +64,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 7316f95..2deb84d 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -51,20 +51,8 @@ pci_write_config32(dev, 0x10, 0); } -static void thermal_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations thermal_pci_ops = { - .set_subsystem = thermal_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 8768e3e..f7d8b87 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -44,13 +44,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 1e852c0..c2a505b 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -287,20 +287,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a365825..abfe665 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -684,17 +684,6 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -734,7 +723,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index bd035de..8de2d74 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -253,20 +253,8 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index f9e223f..d366703 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -91,20 +91,8 @@ .block_write = lsmbus_block_write, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index ac4c596..65d897f 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -51,20 +51,8 @@ pci_write_config32(dev, 0x10, 0); } -static void thermal_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations thermal_pci_ops = { - .set_subsystem = thermal_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 543ac57..a4f5a01 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -44,13 +44,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 3cec2a9..5b38ea7 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -313,20 +313,8 @@ pci_write_config8(dev, 0x43, reg8); } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d440f65..fe1d84a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -609,18 +609,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -807,7 +795,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index df224d3..8d3ae02 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -610,20 +610,8 @@ } } -static void set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2c24bbf..112445b 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -235,19 +235,6 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static void sata_fill_ssdt(struct device *dev) { config_t *config = dev->chip_info; @@ -255,7 +242,7 @@ } static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 53ba9e2..dd3abfe 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -71,20 +71,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index ca8492b..31b2cb6 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -45,21 +45,8 @@ printk(BIOS_DEBUG, "Thermal init done.\n"); } -static void set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations thermal_ops = { diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 4eacd1b..95cac81 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -78,14 +78,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & - 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 5dd46b2..2deb929 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -154,20 +154,8 @@ } } -static void azalia_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 94b3111..e8cad38 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -723,17 +723,6 @@ pch_enable(dev); } -static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs; @@ -981,7 +970,7 @@ } static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index f5f94fe..09eeff2 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -874,20 +874,8 @@ */ } -static void set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void intel_me_enable(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 97b55e1..fd611ea 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -323,20 +323,8 @@ pci_write_config16(dev, 0x90, map); } -static void sata_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index f5c52ef..23d8125 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -237,20 +237,8 @@ } } -static void serialio_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = serialio_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 307d7d4..c12b29e 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -70,20 +70,8 @@ .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static void smbus_read_resources(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index b54e36b..bc86053 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -175,13 +175,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } + pci_dev_set_subsystem(dev, vendor, device); /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index ee25e5c..ddba351 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -373,20 +373,8 @@ } } -static void usb_xhci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations lops_pci = { - .set_subsystem = &usb_xhci_set_subsystem, + .set_subsystem = &pci_dev_set_subsystem, }; static struct device_operations usb_xhci_ops = { diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 86ab5b9..f393297 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,20 +254,8 @@ #endif } -static void azalia_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - if (!vendor || !device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - pci_read_config32(dev, PCI_VENDOR_ID)); - } else { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations azalia_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d Gerrit-Change-Number: 31982 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: src/arch/mips: Fix checkpatch warnings and errors
by Asami Doi (Code Review) 22 Mar '19

22 Mar '19

Asami Doi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31938 Change subject: src/arch/mips: Fix checkpatch warnings and errors ...................................................................... src/arch/mips: Fix checkpatch warnings and errors Change-Id: Ic859913b93dc8ed6ff64b551c8a6baf72d28c75a Signed-off-by: Asami Doi <d0iasm.pub(a)gmail.com> --- M src/arch/mips/ashldi3.c M src/arch/mips/boot.c M src/arch/mips/bootblock_simple.c M src/arch/mips/include/arch/memlayout.h 4 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31938/1 diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c index 9ee40efa..f68d78e 100644 --- a/src/arch/mips/ashldi3.c +++ b/src/arch/mips/ashldi3.c @@ -19,7 +19,7 @@ #errror "What endian are you!?" #endif -typedef unsigned word_type; +typedef unsigned int word_type; long long __ashldi3(long long u, word_type b); struct DWstruct { diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c index 5ab36ec..3857036 100644 --- a/src/arch/mips/boot.c +++ b/src/arch/mips/boot.c @@ -19,7 +19,7 @@ void arch_prog_run(struct prog *prog) { void *cb_tables = prog_entry_arg(prog); - void (*doit)(void *) = prog_entry(prog); + void *doit = (void *)prog_entry(prog); doit(cb_tables); } diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c index 40987d8..367dd6c 100644 --- a/src/arch/mips/bootblock_simple.c +++ b/src/arch/mips/bootblock_simple.c @@ -34,8 +34,8 @@ if (init_extra_hardware()) { printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n"); - } else { + else run_romstage(); - } + halt(); } diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index fe05bd8..099531d 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -21,8 +21,10 @@ /* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */ /* TODO: Double-check that that's the correct alignment for our ABI. */ #define STACK(addr, size) \ +do { \ REGION(stack, addr, size, 8) \ - _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc") \ +} while (0) #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) -- To view, visit https://review.coreboot.org/c/coreboot/+/31938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic859913b93dc8ed6ff64b551c8a6baf72d28c75a Gerrit-Change-Number: 31938 Gerrit-PatchSet: 1 Gerrit-Owner: Asami Doi <d0iasm.pub(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: Revert "soc/nvidia/tegra{124,210}: Remove unneeded 'include <halt.h>'"
by Patrick Georgi (Code Review) 22 Mar '19

22 Mar '19

Hello Kyösti Mälkki, HAOUAS Elyes, Julius Werner, build bot (Jenkins), Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32015 to review the following change. Change subject: Revert "soc/nvidia/tegra{124,210}: Remove unneeded 'include <halt.h>'" ...................................................................... Revert "soc/nvidia/tegra{124,210}: Remove unneeded 'include <halt.h>'" This reverts commit a9273b5015f1cbcf3fc5db048663147c25c76f83. Reason for revert: halt.h may be the wrong solution to the problem, but we need a better fix: https://qa.coreboot.org/job/coreboot-gerrit/91169/testReport/junit/(root)/t… Change-Id: Ibfe77eca75b8f2c2d722d8ca69644ecb00122540 --- M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32015/1 diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 7cc3204..4f219e4 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <halt.h> #include <stdint.h> /* Function unit addresses. */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 51e75f5..ddd1f4f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <halt.h> #include <stdint.h> /* Function unit addresses. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfe77eca75b8f2c2d722d8ca69644ecb00122540 Gerrit-Change-Number: 32015 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: nvidia/tegra{124,210}/lp0: Directly include `stdint.h`
by Nico Huber (Code Review) 22 Mar '19

22 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32005 Change subject: nvidia/tegra{124,210}/lp0: Directly include `stdint.h` ...................................................................... nvidia/tegra{124,210}/lp0: Directly include `stdint.h` Use the compiler's `-include` switch to include `stdint.h` instead of adding coreboot's include paths. This avoids leaking other coreboot header files into lp0. Change-Id: I321c0a2fc4a2b3941990804db4e1a691e1bed8c6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/nvidia/tegra124/lp0/Makefile M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/lp0/Makefile M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c 4 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32005/1 diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile index 66af1f5..884f8b2 100644 --- a/src/soc/nvidia/tegra124/lp0/Makefile +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -34,7 +34,7 @@ tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ - -I ../../../../include -I ../../../../arch/arm/include \ + -include ../../../../arch/arm/include/stdint.h \ -include ../../../../commonlib/include/commonlib/compiler.h \ -o $@ $(filter %.c,$+) diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 7cc3204..e00dbd1 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> - /* Function unit addresses. */ enum { UP_TAG_BASE = 0X60000000, diff --git a/src/soc/nvidia/tegra210/lp0/Makefile b/src/soc/nvidia/tegra210/lp0/Makefile index 66af1f5..884f8b2 100644 --- a/src/soc/nvidia/tegra210/lp0/Makefile +++ b/src/soc/nvidia/tegra210/lp0/Makefile @@ -34,7 +34,7 @@ tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ - -I ../../../../include -I ../../../../arch/arm/include \ + -include ../../../../arch/arm/include/stdint.h \ -include ../../../../commonlib/include/commonlib/compiler.h \ -o $@ $(filter %.c,$+) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 51e75f5..c6a8393 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <stdint.h> - /* Function unit addresses. */ enum { UP_TAG_BASE = 0x60000000, -- To view, visit https://review.coreboot.org/c/coreboot/+/32005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I321c0a2fc4a2b3941990804db4e1a691e1bed8c6 Gerrit-Change-Number: 32005 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: arch/ppc64: Add <arch/mmio.h> stubs
by Timothy Pearson (Code Review) 22 Mar '19

22 Mar '19

Timothy Pearson has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31996 ) Change subject: arch/ppc64: Add <arch/mmio.h> stubs ...................................................................... arch/ppc64: Add <arch/mmio.h> stubs The work may be incomplete, we only have an emulation power8 at the moment in the tree. Change-Id: Icdaa0995c8610dcc636923cc79b8455dfaeaa057 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- A src/arch/ppc64/include/arch/mmio.h 1 file changed, 53 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Timothy Pearson: Looks good to me, approved diff --git a/src/arch/ppc64/include/arch/mmio.h b/src/arch/ppc64/include/arch/mmio.h new file mode 100644 index 0000000..8ffb816 --- /dev/null +++ b/src/arch/ppc64/include/arch/mmio.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_MMIO_H__ +#define __ARCH_MMIO_H__ + +#include <stdint.h> + +/* NOTE: These are just stubs; if the architecture requires special + * care to avoid posted writes or cachelines, it is not yet done here. + */ + +static inline uint8_t read8(const volatile void *addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const volatile void *addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const volatile void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void write8(volatile void *addr, uint8_t val) +{ + *(volatile uint8_t *)addr = val; +} + +static inline void write16(volatile void *addr, uint16_t val) +{ + *(volatile uint16_t *)addr = val; +} + +static inline void write32(volatile void *addr, uint32_t val) +{ + *(volatile uint32_t *)addr = val; +} + +#endif /* __ARCH_MMIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdaa0995c8610dcc636923cc79b8455dfaeaa057 Gerrit-Change-Number: 31996 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2019