Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG@14
PS6, Line 14: SLP_S0 residency can increase
> What does that mean? The system is woken up less?
That's the method to confirm system did able to wake up from s0ix, cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec. Means system did able to stay in s0ix for some times.
--
To view, visit https://review.coreboot.org/c/coreboot/+/31888
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Gerrit-Change-Number: 31888
Gerrit-PatchSet: 6
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Thu, 28 Mar 2019 19:56:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: comment
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG@9
PS6, Line 9: Ignore integrated GBE controller LTR setting to make it wake up from
: s0ix with 10/100M cable attached.
Is that documented or is it a workaround? Why does Latency Tolerance Reporting cause problems?
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG@14
PS6, Line 14: SLP_S0 residency can increase
What does that mean? The system is woken up less?
--
To view, visit https://review.coreboot.org/c/coreboot/+/31888
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Gerrit-Change-Number: 31888
Gerrit-PatchSet: 6
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Comment-Date: Thu, 28 Mar 2019 19:19:58 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32092
Change subject: mb/google/sarien: Call EC romstage init function
......................................................................
mb/google/sarien: Call EC romstage init function
When in romstage call into the EC init function so it can send a
progress code to the EC before memory training starts.
BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.
Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/mainboard/google/sarien/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32092/1
diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c
index 95af0bc..e83cd4a 100644
--- a/src/mainboard/google/sarien/romstage.c
+++ b/src/mainboard/google/sarien/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <ec/google/wilco/romstage.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
@@ -49,5 +50,7 @@
.spd_smbus_address[2] = 0xa4
};
+ wilco_ec_romstage_init();
+
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/32092
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b
Gerrit-Change-Number: 32092
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-MessageType: newchange
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32091
Change subject: ec/google/wilco: Add a romstage init function to send progress code
......................................................................
ec/google/wilco: Add a romstage init function to send progress code
When using FSP with debug enabled it takes too long to get to ramstage
and send the first progress code to the EC. The same thing has been
reported to happen when 2x16GB memory is installed.
BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.
Change-Id: I5676354f5e53540273a9029411507f91864735a1
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/ec/google/wilco/Makefile.inc
M src/ec/google/wilco/commands.h
A src/ec/google/wilco/romstage.c
A src/ec/google/wilco/romstage.h
4 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32091/1
diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc
index 2e1c0d4..fe8910c 100644
--- a/src/ec/google/wilco/Makefile.inc
+++ b/src/ec/google/wilco/Makefile.inc
@@ -1,6 +1,7 @@
ifeq ($(CONFIG_EC_GOOGLE_WILCO),y)
bootblock-y += bootblock.c
+romstage-y += commands.c mailbox.c romstage.c
ramstage-y += chip.c commands.c mailbox.c
smm-y += commands.c mailbox.c smihandler.c
diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h
index 42bb4f2..85f5feb 100644
--- a/src/ec/google/wilco/commands.h
+++ b/src/ec/google/wilco/commands.h
@@ -63,6 +63,7 @@
};
enum bios_progress_code {
+ BIOS_PROGRESS_BEFORE_MEMORY = 0x00,
BIOS_PROGRESS_MEMORY_INIT = 0x01,
BIOS_PROGRESS_VIDEO_INIT = 0x02,
BIOS_PROGRESS_LOGO_DISPLAYED = 0x03,
diff --git a/src/ec/google/wilco/romstage.c b/src/ec/google/wilco/romstage.c
new file mode 100644
index 0000000..4f5eef2
--- /dev/null
+++ b/src/ec/google/wilco/romstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "commands.h"
+#include "ec.h"
+#include "romstage.h"
+
+void wilco_ec_romstage_init(void)
+{
+ wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_BEFORE_MEMORY);
+}
diff --git a/src/ec/google/wilco/romstage.h b/src/ec/google/wilco/romstage.h
new file mode 100644
index 0000000..fbbbdc4
--- /dev/null
+++ b/src/ec/google/wilco/romstage.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef EC_GOOGLE_WILCO_ROMSTAGE_H
+#define EC_GOOGLE_WILCO_ROMSTAGE_H
+
+/**
+ * wilco_ec_early_init
+ *
+ * This function performs initialization of the EC in romstage.
+ */
+void wilco_ec_romstage_init(void);
+
+#endif /* EC_GOOGLE_WILCO_ROMSTAGE_H */
--
To view, visit https://review.coreboot.org/c/coreboot/+/32091
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5676354f5e53540273a9029411507f91864735a1
Gerrit-Change-Number: 32091
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-MessageType: newchange
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variant…
File src/mainboard/google/sarien/variants/sarien/ramstage.c:
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variant…
PS4, Line 29: ignore_gbe_ltr
> Could this be done at the SOC level based on whether LAN+s0ix is enabled?
I think that's generic consideration for GBE low power consideration even without s0ix.
--
To view, visit https://review.coreboot.org/c/coreboot/+/31888
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Gerrit-Change-Number: 31888
Gerrit-PatchSet: 4
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 28 Mar 2019 19:14:37 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-MessageType: comment
Hello Roy Park, Patrick Rudolph, EricR Lai, Roy Mingi Park, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31888
to look at the new patch set (#6).
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from
s0ix with 10/100M cable attached.
BUG=b:122435844
TEST= Test on sarien platorm, after the changes sytem can wake by WOL,
and also checked SLP_S0 residency can increase with 10/100M cable
and battery connected.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
---
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/pmc.c
2 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31888/6
--
To view, visit https://review.coreboot.org/c/coreboot/+/31888
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Gerrit-Change-Number: 31888
Gerrit-PatchSet: 6
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello Roy Park, Patrick Rudolph, EricR Lai, Roy Mingi Park, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31888
to look at the new patch set (#5).
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from
s0ix with 10/100M cable attached.
BUG=b:122435844
TEST= Test on sarien platorm, after the changes sytem can wake by WOL,
and also checked SLP_S0 residency can increase with 10/100M cable
and battery connected.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
---
M src/mainboard/google/sarien/variants/sarien/ramstage.c
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/pmc.c
3 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31888/5
--
To view, visit https://review.coreboot.org/c/coreboot/+/31888
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Gerrit-Change-Number: 31888
Gerrit-PatchSet: 5
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com>
Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Julius Werner, Angel Pons, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29917
to look at the new patch set (#31).
Change subject: src: Remove unused variables
......................................................................
src: Remove unused variables
If we enable Wunused in the compiler, we'll have some 'unused variables'.
This patch corrects some of them.
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/quadcore/quadcore.c
M src/device/dram/ddr3.c
M src/drivers/spi/sst.c
M src/lib/selfboot.c
M src/northbridge/amd/amdmct/mct/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/x4x/dq_dqs.c
M src/northbridge/via/vx900/raminit_ddr3.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/acpi.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/southbridge/amd/common/amd_pci_util.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/i82371eb/fadt.c
18 files changed, 44 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/31
--
To view, visit https://review.coreboot.org/c/coreboot/+/29917
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837
Gerrit-Change-Number: 29917
Gerrit-PatchSet: 31
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com>
Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com>
Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: York Yang <yyang024(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-MessageType: newpatchset