Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32089
Change subject: soc/intel/cannonlake: Update CPU Ratio base on MSR
......................................................................
soc/intel/cannonlake: Update CPU Ratio base on MSR
The following is logic with FSP, as long as the Cpu Ratio input in
coreboot is different with CpuStrapSet, system will force to follow
input from coreboot. But CpuStrapsetting is floating, it will 0 from
first cold boot before memory training and set to 0x1c after first
memory training.
BUG=b:129412691
TEST=Boot up sarien platform and force recovery, check there's no reset
in the path of recovery.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa
---
M src/soc/intel/cannonlake/romstage/fsp_params.c
1 file changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/32089/1
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 3e3aa5e..b7dbac7 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -15,10 +15,12 @@
#include <assert.h>
#include <chip.h>
+#include <cpu/x86/msr.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
+#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -69,19 +71,10 @@
m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif
- /* Disable CPU Flex Ratio and SaGv in recovery mode */
- if (vboot_recovery_mode_enabled()) {
- struct chipset_power_state *ps = pmc_get_power_state();
-
- /*
- * Only disable when coming from S5 (cold reset) otherwise
- * the flex ratio may be locked and FSP will return an error.
- */
- if (ps && ps->prev_sleep_state == ACPI_S5) {
- m_cfg->CpuRatio = 0;
- m_cfg->SaGv = 0;
- }
- }
+ /* Set CpuRatio to be match with MSR settings */
+ msr_t flex_ratio;
+ flex_ratio = rdmsr(MSR_FLEX_RATIO);
+ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
/* If ISH is enabled, enable ISH elements */
if (!dev)
--
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32079 )
Change subject: drivers/intel/fsp2_0: Enable FSP feature to make use of same stack with bootloader
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32079/2/src/drivers/intel/fsp2_0/memory_ini…
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/#/c/32079/2/src/drivers/intel/fsp2_0/memory_ini…
PS2, Line 175: arch_upd->StackBase = (void *)_car_stack_start;
> Commit description needs more elaboration. […]
yes, we have discovered a bug with existing implementation where car global variables were getting corrupted after FSP-M call return.
if you see TEST description, it hope its clear that nothing is corrupted now. This was more CB side bug rather FSP.
Also with previous implementation, we were not honoring same stack for CB and FSP, rather we were giving different stack base to both to grow but FSP can actually exist inside same CB stack with new implementation. From FSP team side, this feature been tested across other bootloader and we have also tested the same with coreboot. Should be good for us to enable this feature for ICL and CML going forward.
TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp.
No stack variable or car global variable corruption seen after enabling
this feature.
--
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Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: mb/google/sarien: Ignore GBE LTR
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variant…
File src/mainboard/google/sarien/variants/sarien/ramstage.c:
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variant…
PS4, Line 29: ignore_gbe_ltr
Could this be done at the SOC level based on whether LAN+s0ix is enabled?
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30964
Change subject: soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing
......................................................................
soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing
It's used in the code but never defined, which trips up the linter.
We need to sort it out before the patch train gets in, but until then,
the linter is mostly creating noise.
Change-Id: Ib04d5b6d2cb03cc8ee6ef0275e1b201c0fc9eb6d
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/soc/qualcomm/qcs405/Kconfig
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30964/1
diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig
index b24dc9e..ea1cee4 100644
--- a/src/soc/qualcomm/qcs405/Kconfig
+++ b/src/soc/qualcomm/qcs405/Kconfig
@@ -21,6 +21,13 @@
select VBOOT_OPROM_MATTERS
select VBOOT_STARTS_IN_BOOTBLOCK
+config QC_SDI_ENABLE
+ bool
+ default n
+ help
+ dummy entry because that variable isn't _really_ used yet.
+ todo(pgeorgi): check if used before merging
+
config QC_SOC_SIMULATE
bool
prompt "Build for Early Simulation Environment"
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 )
Change subject: soc/intel/common: Move eventlog support into common code
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo…
File src/soc/intel/common/block/elog/elog.c:
https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo…
PS4, Line 38: static void pch_log_wake_source(struct chipset_power_state *ps)
Are all these pm1_sts bits really common across different platforms -- APL,GLK,KBL,WHL,CNL?
https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo…
PS4, Line 72: pch_log_power_and_resets
Are these all bits same across different platforms such that they can be made common?
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 )
Change subject: soc/intel/common: Move eventlog support into common code
......................................................................
Patch Set 3:
> what about KBL, ICL, GLK using the same?
KBL and ICL will be same, I can update that. GLK will be a little bit difference, thanks for point that out and I am going to update them.
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 )
Change subject: soc/intel/common: Move eventlog support into common code
......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/31967/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31967/3//COMMIT_MSG@9
PS3, Line 9: intel
> Intel
Done
https://review.coreboot.org/#/c/31967/3/src/soc/intel/common/block/elog/Kco…
File src/soc/intel/common/block/elog/Kconfig:
https://review.coreboot.org/#/c/31967/3/src/soc/intel/common/block/elog/Kco…
PS3, Line 4: suupport
> support
Done
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Hello Patrick Rudolph, Subrata Banik, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31967
to look at the new patch set (#4).
Change subject: soc/intel/common: Move eventlog support into common code
......................................................................
soc/intel/common: Move eventlog support into common code
Event log support is similar across Intel SOC, move to common code for
easier integration of future SOCs.
TEST=Boot up into OS on Sarien platform, check with mosys eventlog list
to see eventlog updated.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: Idf1f69b15487c9a08f1ddaeab055880eef9c2f24
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/common/block/elog/Kconfig
A src/soc/intel/common/block/elog/Makefile.inc
R src/soc/intel/common/block/elog/elog.c
5 files changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/31967/4
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