coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

1 participants
1542 discussions

Change in ...coreboot[master]: qcs405: Add support for USB host mode
by Name of user not set (Code Review) 27 Mar '19

27 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29966 to look at the new patch set (#18). Change subject: qcs405: Add support for USB host mode ...................................................................... qcs405: Add support for USB host mode Add required changes for USB host mode for USB disk enumeration. TEST=build & run Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy(a)partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/clock.h A src/soc/qualcomm/qcs405/include/soc/usb.h A src/soc/qualcomm/qcs405/usb.c 4 files changed, 351 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29966/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 18 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mb/mainboard/google/hatch/variants: Set tcc_offset value
by Sumeet R Pawnikar (Code Review) 27 Mar '19

27 Mar '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31984 Change subject: mb/mainboard/google/hatch/variants: Set tcc_offset value ...................................................................... mb/mainboard/google/hatch/variants: Set tcc_offset value Set tcc_offset value to 5C. It configures the Thermal Control Circuit (TCC) activaction value to 95C. This prevents any abrupt thermal shutdown by taking early thermal throttling action when CPU temperature goes above 95C. Change-Id: Ifee0fcc326530622b04e60af0f3b9cb9e3aea7ea Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31984/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 16a0ef1..516ee79 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -66,6 +66,7 @@ register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "44" register "Device4Enable" = "1" + register "tcc_offset" = "5" # TCC of 95C register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifee0fcc326530622b04e60af0f3b9cb9e3aea7ea Gerrit-Change-Number: 31984 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: soc/intel/common: Move eventlog support into common code
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 ) Change subject: soc/intel/common: Move eventlog support into common code ...................................................................... Patch Set 3: (1 comment) I support Subrata's motion to enable this on other chipsets as well. Maybe in a follow-up patch if this is considered in any way controversial. https://review.coreboot.org/#/c/31967/3/src/soc/intel/common/block/elog/Kco… File src/soc/intel/common/block/elog/Kconfig: https://review.coreboot.org/#/c/31967/3/src/soc/intel/common/block/elog/Kco… PS3, Line 4: suupport support -- To view, visit https://review.coreboot.org/c/coreboot/+/31967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf1f69b15487c9a08f1ddaeab055880eef9c2f24 Gerrit-Change-Number: 31967 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2019 08:39:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: FSP UPD update
by Krzysztof M Sywula (Code Review) 27 Mar '19

27 Mar '19

Krzysztof M Sywula has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32026 Change subject: soc/intel/cannonlake: FSP UPD update ...................................................................... soc/intel/cannonlake: FSP UPD update Exposed FSP params: SlpS0WithGbeSupport, PchPmSlpS0VmRuntimeControl, PchPmSlpS0VmRuntimeControl, PchPmSlpS0VmRuntimeControl. Their values can be controled from devicetree.cb. Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32026/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b4d78f3..72fb45a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -138,6 +138,12 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + /* Power management related */ + uint8_t SlpS0WithGbeSupport; + uint8_t PchPmSlpS0VmRuntimeControl; + uint8_t PchPmSlpS0Vm070VSupport; + uint8_t PchPmSlpS0Vm075VSupport; + /* Audio related */ uint8_t PchHdaDspEnable; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 77d82d6..58dab3f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -164,6 +164,12 @@ else params->PchLanEnable = dev->enabled; + /* Power management related */ + params->SlpS0WithGbeSupport = config->SlpS0WithGbeSupport; + params->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl; + params->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport; + params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport; + /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; -- To view, visit https://review.coreboot.org/c/coreboot/+/32026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e Gerrit-Change-Number: 32026 Gerrit-PatchSet: 1 Gerrit-Owner: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-MessageType: newchange

6 17

Change in ...coreboot[master]: drivers/intel/gma: Move gfxinit into sub package
by Nico Huber (Code Review) 27 Mar '19

27 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31456 Change subject: drivers/intel/gma: Move gfxinit into sub package ...................................................................... drivers/intel/gma: Move gfxinit into sub package Move the actual graphics init provided by libgfxinit into a sub package `GMA.GFX_Init`. This way it can be compiled in individually. Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/Makefile.inc A src/drivers/intel/gma/gma-gfx_init.ads M src/drivers/intel/gma/gma.ads R src/drivers/intel/gma/hires_fb/gma-gfx_init.adb R src/drivers/intel/gma/text_fb/gma-gfx_init.adb 5 files changed, 48 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31456/1 diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index ebc688f..e128ad6 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -50,11 +50,13 @@ subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma.ads +ramstage-y += gma.ads + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-gfx_init.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma-gfx_init.adb else -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma-gfx_init.adb endif endif # CONFIG_GFX_GMA diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads new file mode 100644 index 0000000..7c96f9a --- /dev/null +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -0,0 +1,38 @@ +with Interfaces.C; + +with HW; +use HW; + +package GMA.GFX_Init +is + + procedure gfxinit (lightup_ok : out Interfaces.C.int); + pragma Export (C, gfxinit, "gma_gfxinit"); + + ---------------------------------------------------------------------------- + + type lb_framebuffer is record + tag : word32; + size : word32; + + physical_address : word64; + x_resolution : word32; + y_resolution : word32; + bytes_per_line : word32; + bits_per_pixel : word8; + red_mask_pos : word8; + red_mask_size : word8; + green_mask_pos : word8; + green_mask_size : word8; + blue_mask_pos : word8; + blue_mask_size : word8; + reserved_mask_pos : word8; + reserved_mask_size : word8; + end record; + + function fill_lb_framebuffer + (framebuffer : in out lb_framebuffer) + return Interfaces.C.int; + pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer"); + +end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/gma.ads b/src/drivers/intel/gma/gma.ads index 7286e7e..a6ce3a4 100644 --- a/src/drivers/intel/gma/gma.ads +++ b/src/drivers/intel/gma/gma.ads @@ -1,38 +1,2 @@ -with Interfaces.C; - -with HW; -use HW; - -package GMA -is - - procedure gfxinit (lightup_ok : out Interfaces.C.int); - pragma Export (C, gfxinit, "gma_gfxinit"); - - ---------------------------------------------------------------------------- - - type lb_framebuffer is record - tag : word32; - size : word32; - - physical_address : word64; - x_resolution : word32; - y_resolution : word32; - bytes_per_line : word32; - bits_per_pixel : word8; - red_mask_pos : word8; - red_mask_size : word8; - green_mask_pos : word8; - green_mask_size : word8; - blue_mask_pos : word8; - blue_mask_size : word8; - reserved_mask_pos : word8; - reserved_mask_size : word8; - end record; - - function fill_lb_framebuffer - (framebuffer : in out lb_framebuffer) - return Interfaces.C.int; - pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer"); - +package GMA is end GMA; diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb similarity index 98% rename from src/drivers/intel/gma/hires_fb/gma.adb rename to src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index e3553ca..1393784 100644 --- a/src/drivers/intel/gma/hires_fb/gma.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -13,7 +13,7 @@ with GMA.Mainboard; -package body GMA +package body GMA.GFX_Init is fb_valid : boolean := false; @@ -114,4 +114,4 @@ end if; end gfxinit; -end GMA; +end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/text_fb/gma.adb b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb similarity index 97% rename from src/drivers/intel/gma/text_fb/gma.adb rename to src/drivers/intel/gma/text_fb/gma-gfx_init.adb index 145b9a0..038b76b 100644 --- a/src/drivers/intel/gma/text_fb/gma.adb +++ b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb @@ -8,7 +8,7 @@ with GMA.Mainboard; -package body GMA +package body GMA.GFX_Init is function fill_lb_framebuffer @@ -65,4 +65,4 @@ end if; end gfxinit; -end GMA; +end GMA.GFX_Init; -- To view, visit https://review.coreboot.org/c/coreboot/+/31456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec Gerrit-Change-Number: 31456 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: drivers/intel/gma: Make libgfxinit available w/o gfxinit
by Nico Huber (Code Review) 27 Mar '19

27 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31455 Change subject: drivers/intel/gma: Make libgfxinit available w/o gfxinit ...................................................................... drivers/intel/gma: Make libgfxinit available w/o gfxinit We might want to make use of libgfxinit functions without using it for actual graphics init. Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc 3 files changed, 19 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31455/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index b90b15f..4e09c06 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -76,7 +76,6 @@ depends on MAINBOARD_HAS_LIBGFXINIT select HAVE_VGA_TEXT_FRAMEBUFFER select HAVE_LINEAR_FRAMEBUFFER - select RAMSTAGE_LIBHWBASE select VGA if VGA_TEXT_FRAMEBUFFER help Use the SPARK library `libgfxinit` for the native graphics diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index a5c8495..4f897fa 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -69,7 +69,20 @@ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE - depends on MAINBOARD_HAS_LIBGFXINIT + depends on MAINBOARD_USE_LIBGFXINIT + select RAMSTAGE_LIBHWBASE + +config GFX_GMA_INTERNAL_IS_EDP + bool + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + default n if GFX_GMA_INTERNAL_IS_LVDS + default y + +config GFX_GMA_INTERNAL_IS_LVDS + bool + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM + default n if GFX_GMA @@ -89,16 +102,6 @@ default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL default "Normal" -config GFX_GMA_INTERNAL_IS_EDP - bool - default n if GFX_GMA_INTERNAL_IS_LVDS - default y - -config GFX_GMA_INTERNAL_IS_LVDS - bool - default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM - default n - config GFX_GMA_INTERNAL_PORT string default "DP" if GFX_GMA_INTERNAL_IS_EDP diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..ebc688f 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -33,7 +33,7 @@ $(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE))) endif -ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) +ifeq ($(CONFIG_GFX_GMA),y) $(call add-special-class,gfxinit) gfxinit-handler = $(eval ramstage-srcs += $(1)$(2)) @@ -50,11 +50,11 @@ subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-y += gma.ads +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) -ramstage-y += hires_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma.adb else -ramstage-y += text_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma.adb endif -endif # CONFIG_MAINBOARD_USE_LIBGFXINIT +endif # CONFIG_GFX_GMA -- To view, visit https://review.coreboot.org/c/coreboot/+/31455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9 Gerrit-Change-Number: 31455 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: lib/edid.c: Dump EDID breakdown after null check
by Jacob Garber (Code Review) 27 Mar '19

27 Mar '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32055 Change subject: lib/edid.c: Dump EDID breakdown after null check ...................................................................... lib/edid.c: Dump EDID breakdown after null check The edid variable was being dereferenced before the null check. Split off the null check to before dumping and update the error message. Fixes CID 1370576 (REVERSE_INULL) Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I8fe3d911df3a11a873056d3a5c05c5a3cbcfe2c0 --- M src/lib/edid.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32055/1 diff --git a/src/lib/edid.c b/src/lib/edid.c index 553b0a2..5925759 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1138,11 +1138,16 @@ .conformant = EDID_CONFORMANT, }; - dump_breakdown(edid); - memset(out, 0, sizeof(*out)); - if (!edid || memcmp(edid, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)) { + if (!edid) { + printk(BIOS_SPEW, "No EDID found\n"); + return EDID_ABSENT; + } + + dump_breakdown(edid); + + if (memcmp(edid, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)) { printk(BIOS_SPEW, "No header found\n"); return EDID_ABSENT; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fe3d911df3a11a873056d3a5c05c5a3cbcfe2c0 Gerrit-Change-Number: 32055 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Micron memory
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32046 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Micron memory ...................................................................... mb/google/poppy/variants/rammus: Support new onboard Micron memory Add micron_dimm_MT52L256M32D1PF-107 for new onboard memory support. BUG=none BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32046 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/rammus/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 48def13..44dd07b 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -2,6 +2,7 @@ SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-093 # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/32046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d Gerrit-Change-Number: 32046 Gerrit-PatchSet: 3 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Micron memory
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has removed a vote on this change. Change subject: mb/google/poppy/variants/rammus: Support new onboard Micron memory ...................................................................... Removed Code-Review+1 by YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/32046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d Gerrit-Change-Number: 32046 Gerrit-PatchSet: 2 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: deleteVote

1 0

Change in ...coreboot[master]: Move calls to quick_ram_check() before CBMEM init
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31978 ) Change subject: Move calls to quick_ram_check() before CBMEM init ...................................................................... Move calls to quick_ram_check() before CBMEM init After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/intel/haswell/romstage.c M src/include/lib.h M src/lib/imd_cbmem.c M src/lib/ramtest.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/x4x/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/intel/fsp_rangeley/romstage.c 13 files changed, 11 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ee87eff..0426bb4 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <lib.h> #include <timestamp.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> @@ -121,9 +120,6 @@ intel_early_me_status(); - quick_ram_check(); - post_code(0x3e); - if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ diff --git a/src/include/lib.h b/src/include/lib.h index 3edc372..098d62d 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,10 +24,11 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn); /* Defined in src/lib/ramtest.c */ +/* Assumption is 32-bit addressable UC memory. */ void ram_check(unsigned long start, unsigned long stop); int ram_check_nodie(unsigned long start, unsigned long stop); int ram_check_noprint_nodie(unsigned long start, unsigned long stop); -void quick_ram_check(void); +void quick_ram_check_or_die(uintptr_t dst); /* Defined in primitive_memtest.c */ int primitive_memtest(uintptr_t base, uintptr_t size); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index c458e5e..1a67ad5 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <cbmem.h> #include <imd.h> +#include <lib.h> #include <stdlib.h> #include <arch/early_variables.h> @@ -119,6 +120,10 @@ return; cbmem_top_init(); + + /* The test is only effective on X86 and when address hits UC memory. */ + if (ENV_X86) + quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32)); } void cbmem_initialize_empty_id_size(u32 id, u64 size) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index eb58c30..489ca28 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -171,7 +171,10 @@ return failures; } -static void __quick_ram_check(uintptr_t dst) +/* Assumption is 32-bit addressable UC memory at dst. This also executes + * on S3 resume path so target memory must be restored. + */ +void quick_ram_check_or_die(uintptr_t dst) { int fail = 0; u32 backup; @@ -200,8 +203,3 @@ } phys_memory_barrier(); } - -void quick_ram_check(void) -{ - __quick_ram_check(0x100000); -} diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index c5a3120..7e895b4 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> #include <romstage_handoff.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -273,7 +272,4 @@ } romstage_handoff_init(s3resume); - - if (!s3resume) - quick_ram_check(); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index b20c445..35b90f6 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> #include <romstage_handoff.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -266,7 +265,4 @@ } romstage_handoff_init(s3resume); - - if (!s3resume) - quick_ram_check(); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index cf1da63..e6a344e 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <lib.h> #include <timestamp.h> #include <console/console.h> #include <device/pci_ops.h> @@ -105,8 +104,6 @@ post_code(0x31); - quick_ram_check(); - mb_pirq_setup(); rcba_config(); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3f62d10..4a048db 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -31,7 +31,6 @@ #include <southbridge/intel/common/smbus.h> #include <cpu/x86/msr.h> #include <delay.h> -#include <lib.h> #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" @@ -419,9 +418,6 @@ /* Zone config */ dram_zones(&ctrl, 0); - /* Non intrusive, fast ram check */ - quick_ram_check(); - intel_early_me_status(); intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); intel_early_me_status(); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 72ef1a9..02a8b74 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -23,7 +23,6 @@ #include <arch/cpu.h> #include <delay.h> #include <halt.h> -#include <lib.h> #include "iomap.h" #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ @@ -734,6 +733,5 @@ } timestamp_add_now(TS_AFTER_INITRAM); - quick_ram_check(); printk(BIOS_DEBUG, "Memory initialized\n"); } diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 04657ae..8d43907 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -20,7 +20,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <device/pci_def.h> -#include <lib.h> #include <memory_info.h> #include <mrc_cache.h> #include <string.h> @@ -98,9 +97,6 @@ report_memory_config(); - /* Basic memory sanity test */ - quick_ram_check(); - if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b4eb006..c46b09e 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -15,7 +15,6 @@ */ #include <stddef.h> -#include <lib.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -245,12 +244,6 @@ late_mainboard_romstage_entry(); post_code(0x4c); - /* if S3 resume skip RAM check */ - if (prev_sleep_state != ACPI_S3) { - quick_ram_check(); - post_code(0x4d); - } - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 36e9e6b..a75dabd 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -16,7 +16,6 @@ */ #include <stddef.h> -#include <lib.h> #include <device/pci_ops.h> #include <arch/cbfs.h> #include <cbmem.h> @@ -112,9 +111,6 @@ post_code(0x4b); late_mainboard_romstage_entry(); - post_code(0x4c); - quick_ram_check(); - post_code(0x4d); cbmem_was_initted = !cbmem_recovery(0); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 14611b3..19e470e 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <lib.h> #include <timestamp.h> #include <arch/io.h> #include <device/mmio.h> @@ -114,9 +113,6 @@ /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - quick_ram_check(); - post_code(0x4d); - cbmem_was_initted = !cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/31978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Gerrit-Change-Number: 31978 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2019