coreboot-gerrit March 2019

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Enable FSP feature to make use of same stack wi...
by Paul Menzel (Code Review) 28 Mar '19

28 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32079 ) Change subject: drivers/intel/fsp2_0: Enable FSP feature to make use of same stack with bootloader ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/32079/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32079/2//COMMIT_MSG@7 PS2, Line 7: drivers/intel/fsp2_0: Enable FSP feature to make use of same stack with bootloader 1. Please short the summary. > drivers/intel/fsp2_0: Use same stack with bootloader 2. What is the bootloader? GRUB is a bootloader for me. https://review.coreboot.org/#/c/32079/2//COMMIT_MSG@10 PS2, Line 10: Please describe the problem in more detail. -- To view, visit https://review.coreboot.org/c/coreboot/+/32079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I673b4216d991d8ccad725c3931006a694184106c Gerrit-Change-Number: 32079 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Mar 2019 08:58:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 28 Mar '19

28 Mar '19

Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#30). Change subject: src: Remove unused variables ...................................................................... src: Remove unused variables If we enable Wunused in the compiler, we'll have some 'unused variables'. This patch corrects some of them. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/quadcore/quadcore.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 18 files changed, 44 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 30 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: chromeos: remove remaining dev switch references
by Joel Kitching (Code Review) 28 Mar '19

28 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32064 Change subject: chromeos: remove remaining dev switch references ...................................................................... chromeos: remove remaining dev switch references As part of chromium:942901, physical dev switch functionality is being deprecated. Remove remaining references as well as helper macros. BUG=chromium:942901 TEST=Build locally TEST=make clean && make test-abuild BRANCH=none Change-Id: Ib4eec083eb76d41b47685701f9394c684ddc6b37 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/vendorcode/google/chromeos/chromeos.h 6 files changed, 2 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/32064/1 diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index a956e28..2301d3e 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -90,7 +90,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), }; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 99fc764..f17b6a6 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -83,7 +83,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), }; diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 875578f..0c8d0b2 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -65,7 +65,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), }; diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 9fae822..aa0d9aa 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -62,7 +62,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), }; diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 9487e9b..6464ef4 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -50,7 +50,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_DEV_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 6db7fc4..e5420ac 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -78,7 +78,8 @@ enum { CROS_GPIO_REC = 1, /* Recovery */ - CROS_GPIO_DEV = 2, /* Developer */ + CROS_GPIO_DEPRECATED_DEV = 2, /* Developer; + * deprecated (chromium:942901) */ CROS_GPIO_WP = 3, /* Write Protect */ CROS_GPIO_PE = 4, /* Phase enforcement for final product */ @@ -112,15 +113,6 @@ #define CROS_GPIO_REC_AH(num, dev) \ CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) -#define CROS_GPIO_DEV_INITIALIZER(pol, num, dev) \ - CROS_GPIO_INITIALIZER(CROS_GPIO_DEV, pol, num, dev) - -#define CROS_GPIO_DEV_AL(num, dev) \ - CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) - -#define CROS_GPIO_DEV_AH(num, dev) \ - CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) - #define CROS_GPIO_WP_INITIALIZER(pol, num, dev) \ CROS_GPIO_INITIALIZER(CROS_GPIO_WP, pol, num, dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/32064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4eec083eb76d41b47685701f9394c684ddc6b37 Gerrit-Change-Number: 32064 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Add support to log XHCI wake events
by Karthik Ramasubramanian (Code Review) 28 Mar '19

28 Mar '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32000 to review the following change. Change subject: soc/intel/apollolake: Add support to log XHCI wake events ...................................................................... soc/intel/apollolake: Add support to log XHCI wake events Add support to identify and log the XHCI wake events for apollolake into event logs. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 12 | 2019-03-20 13:36:12 | S0ix Enter 13 | 2019-03-20 13:36:23 | S0ix Exit 14 | 2019-03-20 13:36:23 | Wake Source | PME - XHCI (USB 2.0 port) | 9 15 | 2019-03-20 13:36:23 | Wake Source | GPE # | 13 16 | 2019-03-20 13:36:54 | S0ix Enter 17 | 2019-03-20 13:36:59 | S0ix Exit 18 | 2019-03-20 13:36:59 | Wake Source | PME - XHCI (USB 2.0 port) | 9 19 | 2019-03-20 13:36:59 | Wake Source | GPE # | 13 20 | 2019-03-20 13:38:15 | S0ix Enter 21 | 2019-03-20 13:38:23 | S0ix Exit 22 | 2019-03-20 13:38:23 | Wake Source | PME - XHCI (USB 2.0 port) | 9 23 | 2019-03-20 13:38:23 | Wake Source | GPE # | 13 Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/elog.c 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32000/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..9696245 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_ELOG_XHCI select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index b03d5e6..51e4e00 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -19,11 +19,24 @@ #include <console/console.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <soc/intel/common/elog_xhci.h> #include <soc/pm.h> #include <soc/pci_devs.h> #include <soc/smbus.h> #include <stdint.h> +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#define XHCI_USB3_PORT_NUM 7 + +static struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -54,6 +67,10 @@ if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); + /* XHCI */ + if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) + pch_xhci_update_wake_event(PCH_DEV_XHCI, &usb_info); + /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/32000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Gerrit-Change-Number: 32000 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Move support to log XHCI wake events
by Karthik Ramasubramanian (Code Review) 28 Mar '19

28 Mar '19

Hello Karthikeyan Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31999 to review the following change. Change subject: soc/intel/common: Move support to log XHCI wake events ...................................................................... soc/intel/common: Move support to log XHCI wake events The policy to identify and log the XHCI wake events is similar between skylake and apollolake. Hence move the similar parts to a common location. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 12 | 2019-03-20 13:36:12 | S0ix Enter 13 | 2019-03-20 13:36:23 | S0ix Exit 14 | 2019-03-20 13:36:23 | Wake Source | PME - XHCI (USB 2.0 port) | 9 15 | 2019-03-20 13:36:23 | Wake Source | GPE # | 13 16 | 2019-03-20 13:36:54 | S0ix Enter 17 | 2019-03-20 13:36:59 | S0ix Exit 18 | 2019-03-20 13:36:59 | Wake Source | PME - XHCI (USB 2.0 port) | 9 19 | 2019-03-20 13:36:59 | Wake Source | GPE # | 13 20 | 2019-03-20 13:38:15 | S0ix Enter 21 | 2019-03-20 13:38:23 | S0ix Exit 22 | 2019-03-20 13:38:23 | Wake Source | PME - XHCI (USB 2.0 port) | 9 23 | 2019-03-20 13:38:23 | Wake Source | GPE # | 13 Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/Kconfig M src/soc/intel/common/Makefile.inc A src/soc/intel/common/elog_xhci.c A src/soc/intel/common/elog_xhci.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/elog.c 6 files changed, 216 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/31999/1 diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index b5caf40..7344198 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -68,4 +68,11 @@ acpi_get_gpe() is used to provide interrupt status to TPM layer. This option specifies the GPE number. +config SOC_INTEL_COMMON_ELOG_XHCI + bool + default n + help + Set this option to identify if XHCI caused a wake up and log that + information into the event log. + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..54d98bb 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -20,6 +20,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ELOG_XHCI) += elog_xhci.c bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c verstage-$(CONFIG_TPM_CR50) += tpm_tis.c @@ -27,6 +28,8 @@ ramstage-$(CONFIG_TPM_CR50) += tpm_tis.c postcar-$(CONFIG_TPM_CR50) += tpm_tis.c +smm-$(CONFIG_SOC_INTEL_COMMON_ELOG_XHCI) += elog_xhci.c + ifeq ($(CONFIG_MMA),y) MMA_BLOBS_PATH = $(call strip_quotes,$(CONFIG_MMA_BLOBS_PATH)) MMA_TEST_NAMES = $(notdir $(wildcard $(MMA_BLOBS_PATH)/tests/*)) diff --git a/src/soc/intel/common/elog_xhci.c b/src/soc/intel/common/elog_xhci.c new file mode 100644 index 0000000..6984e46 --- /dev/null +++ b/src/soc/intel/common/elog_xhci.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <soc/intel/common/elog_xhci.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +/* Wake on disconnect enable */ +#define XHCI_STATUS_WDE (1 << 26) +/* Wake on connect enable */ +#define XHCI_STATUS_WCE (1 << 25) +/* Port link status change */ +#define XHCI_STATUS_PLC (1 << 22) +/* Connect status change */ +#define XHCI_STATUS_CSC (1 << 17) +/* Port link status */ +#define XHCI_STATUS_PLS_SHIFT (5) +#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT) +#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT) + +static bool pch_xhci_csc_set(uint32_t port_status) +{ + return !!(port_status & XHCI_STATUS_CSC); +} + +static bool pch_xhci_wake_capable(uint32_t port_status) +{ + return !!((port_status & XHCI_STATUS_WCE) | + (port_status & XHCI_STATUS_WDE)); +} + +static bool pch_xhci_plc_set(uint32_t port_status) +{ + return !!(port_status & XHCI_STATUS_PLC); +} + +static bool pch_xhci_resume(uint32_t port_status) +{ + return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME; +} + +/* + * Check if a particular USB port caused wake by: + * 1. Change in connect/disconnect status (if enabled) + * 2. USB device activity + * + * Params: + * base : MMIO address of first port. + * num : Number of ports. + * event : Event that needs to be added in case wake source is found. + * + * Return value: + * true : Wake source was found. + * false : Wake source was not found. + */ +static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, + uint32_t event) +{ + uint8_t i; + uint32_t port_status; + bool found = false; + + for (i = 0; i < num; i++, base += 0x10) { + /* Read port status and control register for the port. */ + port_status = read32((void *)base); + + /* Ensure that the status is not all 1s. */ + if (port_status == 0xffffffff) + continue; + + /* + * Check if CSC bit is set and port is capable of wake on + * connect/disconnect to identify if the port caused wake + * event for usb attach/detach. + */ + if (pch_xhci_csc_set(port_status) && + pch_xhci_wake_capable(port_status)) { + elog_add_event_wake(event, i + 1); + found = true; + continue; + } + + /* + * Check if PLC is set and PLS indicates resume to identify if + * the port caused wake event for usb activity. + */ + if (pch_xhci_plc_set(port_status) && + pch_xhci_resume(port_status)) { + elog_add_event_wake(event, i + 1); + found = true; + } + } + return found; +} + +/* + * Update elog event and instance depending upon the USB2 port that caused + * the wake event. + * + * Return value: + * true = Indicates that USB2 wake event was found. + * false = Indicates that USB2 wake event was not found. + */ +static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base, + struct xhci_usb_info *info) +{ + return pch_xhci_port_wake_check(mmio_base + info->usb2_port_status_reg, + info->num_usb2_ports, + ELOG_WAKE_SOURCE_PME_XHCI_USB_2); +} + +/* + * Update elog event and instance depending upon the USB3 port that caused + * the wake event. + * + * Return value: + * true = Indicates that USB3 wake event was found. + * false = Indicates that USB3 wake event was not found. + */ +static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base, + struct xhci_usb_info *info) +{ + return pch_xhci_port_wake_check(mmio_base + info->usb3_port_status_reg, + info->num_usb3_ports, + ELOG_WAKE_SOURCE_PME_XHCI_USB_3); +} + +#ifdef __SIMPLE_DEVICE__ +bool pch_xhci_update_wake_event(pci_devfn_t dev, struct xhci_usb_info *info) +#else +bool pch_xhci_update_wake_event(struct device *dev, struct xhci_usb_info *info) +#endif +{ + uintptr_t mmio_base; + bool event_found = false; + mmio_base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); + + if (pch_xhci_usb2_update_wake_event(mmio_base, info)) + event_found = true; + + if (pch_xhci_usb3_update_wake_event(mmio_base, info)) + event_found = true; + + return event_found; +} diff --git a/src/soc/intel/common/elog_xhci.h b/src/soc/intel/common/elog_xhci.h new file mode 100644 index 0000000..9e38911 --- /dev/null +++ b/src/soc/intel/common/elog_xhci.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_ELOG_XHCI_H +#define SOC_INTEL_COMMON_ELOG_XHCI_H + +#include <stdint.h> +#include <device/pci_type.h> + +struct xhci_usb_info { + uint32_t usb2_port_status_reg; + uint32_t num_usb2_ports; + uint32_t usb3_port_status_reg; + uint32_t num_usb3_ports; +}; + +#ifdef __SIMPLE_DEVICE__ +bool pch_xhci_update_wake_event(pci_devfn_t dev, struct xhci_usb_info *info); +#else +bool pch_xhci_update_wake_event(struct device *dev, struct xhci_usb_info *info); +#endif + +#endif /* SOC_INTEL_COMMON_ELOG_XHCI_H */ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 53094b1..c02900a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -66,6 +66,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_ELOG_XHCI select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 7a8932b..3094591 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <soc/intel/common/elog_xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> @@ -42,142 +43,13 @@ #define XHCI_USB3_PORT_STATUS_REG 0x540 #define XHCI_USB2_PORT_NUM 10 #define XHCI_USB3_PORT_NUM 6 -/* Wake on disconnect enable */ -#define XHCI_STATUS_WDE (1 << 26) -/* Wake on connect enable */ -#define XHCI_STATUS_WCE (1 << 25) -/* Port link status change */ -#define XHCI_STATUS_PLC (1 << 22) -/* Connect status change */ -#define XHCI_STATUS_CSC (1 << 17) -/* Port link status */ -#define XHCI_STATUS_PLS_SHIFT (5) -#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT) -#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT) -static bool pch_xhci_csc_set(uint32_t port_status) -{ - return !!(port_status & XHCI_STATUS_CSC); -} - -static bool pch_xhci_wake_capable(uint32_t port_status) -{ - return !!((port_status & XHCI_STATUS_WCE) | - (port_status & XHCI_STATUS_WDE)); -} - -static bool pch_xhci_plc_set(uint32_t port_status) -{ - return !!(port_status & XHCI_STATUS_PLC); -} - -static bool pch_xhci_resume(uint32_t port_status) -{ - return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME; -} - -/* - * Check if a particular USB port caused wake by: - * 1. Change in connect/disconnect status (if enabled) - * 2. USB device activity - * - * Params: - * base : MMIO address of first port. - * num : Number of ports. - * event : Event that needs to be added in case wake source is found. - * - * Return value: - * true : Wake source was found. - * false : Wake source was not found. - */ -static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, - uint32_t event) -{ - uint8_t i; - uint32_t port_status; - bool found = false; - - for (i = 0; i < num; i++, base += 0x10) { - /* Read port status and control register for the port. */ - port_status = read32((void *)base); - - /* Ensure that the status is not all 1s. */ - if (port_status == 0xffffffff) - continue; - - /* - * Check if CSC bit is set and port is capable of wake on - * connect/disconnect to identify if the port caused wake - * event for usb attach/detach. - */ - if (pch_xhci_csc_set(port_status) && - pch_xhci_wake_capable(port_status)) { - elog_add_event_wake(event, i + 1); - found = true; - continue; - } - - /* - * Check if PLC is set and PLS indicates resume to identify if - * the port caused wake event for usb activity. - */ - if (pch_xhci_plc_set(port_status) && - pch_xhci_resume(port_status)) { - elog_add_event_wake(event, i + 1); - found = true; - } - } - return found; -} - -/* - * Update elog event and instance depending upon the USB2 port that caused - * the wake event. - * - * Return value: - * true = Indicates that USB2 wake event was found. - * false = Indicates that USB2 wake event was not found. - */ -static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base) -{ - return pch_xhci_port_wake_check(mmio_base + XHCI_USB2_PORT_STATUS_REG, - XHCI_USB2_PORT_NUM, - ELOG_WAKE_SOURCE_PME_XHCI_USB_2); -} - -/* - * Update elog event and instance depending upon the USB3 port that caused - * the wake event. - * - * Return value: - * true = Indicates that USB3 wake event was found. - * false = Indicates that USB3 wake event was not found. - */ -static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base) -{ - return pch_xhci_port_wake_check(mmio_base + XHCI_USB3_PORT_STATUS_REG, - XHCI_USB3_PORT_NUM, - ELOG_WAKE_SOURCE_PME_XHCI_USB_3); -} - -#ifdef __SIMPLE_DEVICE__ -static bool pch_xhci_update_wake_event(pci_devfn_t dev) -#else -static bool pch_xhci_update_wake_event(struct device *dev) -#endif -{ - uintptr_t mmio_base; - bool event_found = false; - mmio_base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); - - if (pch_xhci_usb2_update_wake_event(mmio_base)) - event_found = true; - - if (pch_xhci_usb3_update_wake_event(mmio_base)) - event_found = true; - - return event_found; -} +static struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; struct pme_status_info { #ifdef __SIMPLE_DEVICE__ @@ -203,7 +75,8 @@ * If wake source is XHCI, check for detailed wake source events on * USB2/3 ports. */ - if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(dev)) + if ((info->dev == PCH_DEV_XHCI) && + pch_xhci_update_wake_event(dev, &usb_info)) return; elog_add_event_wake(info->elog_event, 0); @@ -251,7 +124,7 @@ * PME_STS_BIT in controller register. */ if (!dev_found) - dev_found = pch_xhci_update_wake_event(PCH_DEV_XHCI); + dev_found = pch_xhci_update_wake_event(PCH_DEV_XHCI, &usb_info); if (!dev_found) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/31999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e Gerrit-Change-Number: 31999 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: mb/google/hatch/variants: Add DPTF based Fan control
by Sumeet R Pawnikar (Code Review) 28 Mar '19

28 Mar '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31980 Change subject: mb/google/hatch/variants: Add DPTF based Fan control ...................................................................... mb/google/hatch/variants: Add DPTF based Fan control This adds DPTF based Fan speed control for CML based Hatch system. BUG=None BRANCH=None TEST=Built and tested fan speed with different temperatures Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl 1 file changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31980/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl index 6e818f6..f1b14ff 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -15,18 +15,34 @@ #define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 #define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { @@ -36,6 +52,49 @@ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ }) +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) +#endif + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d Gerrit-Change-Number: 31980 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: payload: Fix not to display `Fit support` on non-ARM platforms
by Xiang Wang (Code Review) 28 Mar '19

28 Mar '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32056 Change subject: payload: Fix not to display `Fit support` on non-ARM platforms ...................................................................... payload: Fix not to display `Fit support` on non-ARM platforms Change-Id: Ided1cc22173342fa751b84db5f08a5cf7408941d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32056/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index c7a7ba6..d3f5927 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -100,6 +100,7 @@ bool "FIT support" default n default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64) + depends on ARCH_ARM || ARCH_ARM64 select FLATTENED_DEVICE_TREE help Select this option if your payload is of type FIT. -- To view, visit https://review.coreboot.org/c/coreboot/+/32056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ided1cc22173342fa751b84db5f08a5cf7408941d Gerrit-Change-Number: 32056 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: google/oak: Delete rowan
by Evan Green (Code Review) 28 Mar '19

28 Mar '19

Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32061 Change subject: google/oak: Delete rowan ...................................................................... google/oak: Delete rowan Rowan board is dead, dissect it out of Oak. Signed-off-by: Evan Green <evgreen(a)chromium.org> BUG=chromium:840888 BRANCH=none TEST=emerge-oak coreboot chromeos-bootimage CQ-DEPEND=CL:1538915,CL:*1087044 Change-Id: Ifb19fa0cd814853270847bc14fc21c841d905146 --- M src/mainboard/google/oak/Kconfig M src/mainboard/google/oak/Kconfig.name M src/mainboard/google/oak/gpio.h M src/mainboard/google/oak/mainboard.c 4 files changed, 12 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32061/1 diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index b770944..c383fa4 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -20,13 +20,12 @@ config OTHERS_HAVE_TPM1 bool - default y if !BOARD_GOOGLE_ROWAN + default y select MAINBOARD_HAS_I2C_TPM_GENERIC select MAINBOARD_HAS_TPM1 config OAK_HAS_TPM2 bool - default y if BOARD_GOOGLE_ROWAN default n select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 @@ -90,7 +89,6 @@ default "Oak" if BOARD_GOOGLE_OAK default "Elm" if BOARD_GOOGLE_ELM default "Hana" if BOARD_GOOGLE_HANA - default "Rowan" if BOARD_GOOGLE_ROWAN config GBB_HWID string @@ -98,7 +96,6 @@ default "OAK TEST 6858" if BOARD_GOOGLE_OAK default "ELM TEST 3839" if BOARD_GOOGLE_ELM default "HANA TEST 5855" if BOARD_GOOGLE_HANA - default "ROWAN TEST 9387" if BOARD_GOOGLE_ROWAN # All Oak-derivatives count their board IDs as 0 being equivalent to Oak rev6. config BOARD_ID_ADJUSTMENT @@ -106,6 +103,5 @@ default 0 if BOARD_GOOGLE_OAK default 7 if BOARD_GOOGLE_ELM default 11 if BOARD_GOOGLE_HANA - default 15 if BOARD_GOOGLE_ROWAN endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/oak/Kconfig.name b/src/mainboard/google/oak/Kconfig.name index 3290397..44e21a1 100644 --- a/src/mainboard/google/oak/Kconfig.name +++ b/src/mainboard/google/oak/Kconfig.name @@ -12,6 +12,3 @@ bool "-> Hana (Lenovo N23 Yoga Chromebook)" select BOARD_GOOGLE_OAK_COMMON -config BOARD_GOOGLE_ROWAN - bool "-> Rowan" - select BOARD_GOOGLE_OAK_COMMON diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index 84d9419..13636c7 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -17,16 +17,10 @@ #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ #include <soc/gpio.h> -#if CONFIG(BOARD_GOOGLE_ROWAN) -#define LID GPIO(KPROW1) -#define RAM_ID_1 GPIO(DSI_TE) -#define RAM_ID_2 GPIO(RDP1_A) -#else #define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \ GPIO(EINT12) : GPIO(SPI_CK)) #define RAM_ID_1 GPIO(RCN_A) #define RAM_ID_2 GPIO(RCP_A) -#endif /* Board ID related GPIOS. */ #define BOARD_ID_0 GPIO(RDN3_A) diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 21525fa..d2aee90 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -127,12 +127,10 @@ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) { /* Type C port 0 Over current alert pin */ gpio_input_pullup(GPIO(MSDC3_DSL)); - if (!CONFIG(BOARD_GOOGLE_ROWAN)) { - /* Enable USB3 type A port 0 5V load switch */ - gpio_output(GPIO(CM2MCLK), 1); - /* USB3 Type A port 0 power over current alert pin */ - gpio_input_pullup(GPIO(CMPCLK)); - } + /* Enable USB3 type A port 0 5V load switch */ + gpio_output(GPIO(CM2MCLK), 1); + /* USB3 Type A port 0 power over current alert pin */ + gpio_input_pullup(GPIO(CMPCLK)); /* Type C port 1 over current alert pin */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) gpio_input_pullup(GPIO(PCM_SYNC)); @@ -150,9 +148,6 @@ static void configure_usb_hub(void) { - if (CONFIG(BOARD_GOOGLE_ROWAN)) - return; - /* set usb hub reset pin (low active) to high */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) gpio_output(GPIO(UTXD3), 1); @@ -203,51 +198,6 @@ udelay(100); } -static void configure_backlight_rowan(void) -{ - gpio_output(GPIO(DAIPCMOUT), 0); /* PANEL_LCD_POWER_EN */ - gpio_output(GPIO(DISP_PWM0), 0); /* DISP_PWM0 */ - gpio_output(GPIO(PCM_TX), 0); /* PANEL_POWER_EN */ -} - -static void configure_display_rowan(void) -{ - gpio_output(GPIO(UCTS2), 1); /* VDDIO_EN */ - /* delay 15 ms for panel vddio to stabilize */ - mdelay(15); - - gpio_output(GPIO(SRCLKENAI2), 1); /* LCD_RESET */ - udelay(20); - gpio_output(GPIO(SRCLKENAI2), 0); /* LCD_RESET */ - udelay(20); - gpio_output(GPIO(SRCLKENAI2), 1); /* LCD_RESET */ - mdelay(20); - - /* Rowan panel avdd */ - gpio_output(GPIO(URTS2), 1); - - /* Rowan panel avee */ - gpio_output(GPIO(URTS0), 1); - - /* panel.delay.prepare */ - mdelay(20); -} - -static const struct edid rowan_boe_edid = { - .panel_bits_per_color = 8, - .panel_bits_per_pixel = 24, - .mode = { - .name = "1536x2048@60Hz", - .pixel_clock = 241646, - .lvds_dual_channel = 1, - .refresh = 60, - .ha = 1536, .hbl = 404, .hso = 200, .hspw = 4, .hborder = 0, - .va = 2048, .vbl = 28, .vso = 12, .vspw = 2, .vborder = 0, - .phsync = '-', .pvsync = '-', - .x_mm = 147, .y_mm = 196, - }, -}; - static int read_edid_from_ps8640(struct edid *edid) { u8 i2c_bus, i2c_addr; @@ -278,21 +228,12 @@ u32 mipi_dsi_flags; bool dual_dsi_mode; - if (CONFIG(BOARD_GOOGLE_ROWAN)) { - edid = rowan_boe_edid; - dual_dsi_mode = true; - mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | - MIPI_DSI_CLOCK_NON_CONTINUOUS; - } else { - if (read_edid_from_ps8640(&edid) < 0) - return; + if (read_edid_from_ps8640(&edid) < 0) + return; - dual_dsi_mode = false; - mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE; - } + dual_dsi_mode = false; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE; edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); @@ -327,13 +268,8 @@ if (display_init_required()) { mtcmos_display_power_on(); - if (CONFIG(BOARD_GOOGLE_ROWAN)) { - configure_backlight_rowan(); - configure_display_rowan(); - } else { - configure_backlight(); - configure_display(); - } + configure_backlight(); + configure_display(); display_startup(); } else { printk(BIOS_INFO, "Skipping display init.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb19fa0cd814853270847bc14fc21c841d905146 Gerrit-Change-Number: 32061 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Initialize FPMCU_PCH_BOOT1
by Shelley Chen (Code Review) 28 Mar '19

28 Mar '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32060 Change subject: mb/google/hatch: Initialize FPMCU_PCH_BOOT1 ...................................................................... mb/google/hatch: Initialize FPMCU_PCH_BOOT1 In the latest hatch schematics, BOOT1 for the FP MCU is now connected to the AP. Configuring it to be the same as BOOT0. BUG=b:126455006 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -c max Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32060/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 73d6645..1328240 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -33,8 +33,8 @@ /* A8 : EMR_GARAGE_DET ==> NC */ PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ - /* A10 : PEN_RESET_ODL */ - PAD_NC(GPP_A10, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), /* A11 : PCH_SPI_FPMCU_CS_L */ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c Gerrit-Change-Number: 32060 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/intel/common: Move eventlog support into common code
by Lijian Zhao (Code Review) 28 Mar '19

28 Mar '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 ) Change subject: soc/intel/common: Move eventlog support into common code ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo… File src/soc/intel/common/block/elog/elog.c: https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo… PS4, Line 38: static void pch_log_wake_source(struct chipset_power_state *ps) > Are all these pm1_sts bits really common across different platforms -- APL,GLK,KBL,WHL,CNL? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/31967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf1f69b15487c9a08f1ddaeab055880eef9c2f24 Gerrit-Change-Number: 31967 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Mar 2019 06:34:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2019