Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31888/6//COMMIT_MSG@9
PS6, Line 9: Ignore integrated GBE controller LTR setting to make it wake up from
: s0ix with 10/100M cable attached.
> Is that documented or is it a workaround? Why does Latency Tolerance Reporting cause problems?
Yes it is a workaround. https://elixir.bootlin.com/linux/latest/source/drivers/net/ethernet/intel/e… in GBE is not actually a real LTR for PCIE. Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop latencies in the LTR Extended Capability Structure in the PCIe Extended Capability register set, on this device LTR is set by writing the equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) message to the PMC.
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variant…
File src/mainboard/google/sarien/variants/sarien/ramstage.c:
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variant…
PS4, Line 29: ignore_gbe_ltr
> I think that's generic consideration for GBE low power consideration even without s0ix.
After discuss with Roy, it is still proper to bundle with s0ix since S3 will not be blocked by CPU PC10 state.
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Hello Roy Park, Patrick Rudolph, EricR Lai, Roy Mingi Park, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from
s0ix with 10/100M cable attached.
BUG=b:122435844
TEST= Test on sarien platorm, after the changes sytem can wake by WOL,
and also checked SLP_S0 residency can increase with 10/100M cable
and battery connected.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/pmc.h
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31888/8
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Hello Roy Park, Patrick Rudolph, EricR Lai, Roy Mingi Park, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31888
to look at the new patch set (#7).
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from
s0ix with 10/100M cable attached.
BUG=b:122435844
TEST= Test on sarien platorm, after the changes sytem can wake by WOL,
and also checked SLP_S0 residency can increase with 10/100M cable
and battery connected.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/pmc.c
3 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31888/7
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 )
Change subject: soc/intel/common: Move eventlog support into common code
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo…
File src/soc/intel/common/block/elog/elog.c:
https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo…
PS4, Line 38: static void pch_log_wake_source(struct chipset_power_state *ps)
> Ack
I have checked the following EDS
APL,GLK,KBL,WHL,CNL and ICL, three bits we are using here is identical, we can move the definition to common.
However the GPE0 is totally different though, we will need dedicate pm.h in soc directory to take care of the difference.
https://review.coreboot.org/#/c/31967/4/src/soc/intel/common/block/elog/elo…
PS4, Line 72: pch_log_power_and_resets
> Are these all bits same across different platforms such that they can be made common?
There's no gblrst_cause at small core, but they have gen_pmcon_1,2,3
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arch/x86/smbios(type4): Write processor_upgrade field
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Change subject: arch/x86/smbios(type4): Write processor_upgrade field
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