coreboot-gerrit March 2019

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Change in ...coreboot[master]: sdm845: Add USB support on cheza platform
by Julius Werner (Code Review) 27 Mar '19

27 Mar '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 ) Change subject: sdm845: Add USB support on cheza platform ...................................................................... Patch Set 66: (2 comments) LGTM but comment style still needs to be fixed. (T.mike, maybe you could just do that?) https://review.coreboot.org/#/c/25213/66/src/soc/qualcomm/sdm845/usb.c File src/soc/qualcomm/sdm845/usb.c: https://review.coreboot.org/#/c/25213/66/src/soc/qualcomm/sdm845/usb.c@646 PS66, Line 646: printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB\n"); nit: should move this into reset_usb0()/reset_usb1() to be able to print the right controller name https://review.coreboot.org/#/c/25213/66/src/soc/qualcomm/sdm845/usb.c@788 PS66, Line 788: /* DEBUG_STAT5: wait for 160uS for PLL lock; Correct multi-line comment style is either /* * Like * this */ or /* Like this */ (note no star on continuation line for short version). -- To view, visit https://review.coreboot.org/c/coreboot/+/25213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Gerrit-Change-Number: 25213 Gerrit-PatchSet: 66 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Ciluveru chandana kishori <cchiluve(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Chandana Kishori Chiluveru <cchiluve(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Mar 2019 23:17:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Ignore GBE LTR
by Lijian Zhao (Code Review) 27 Mar '19

27 Mar '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 ) Change subject: mb/google/sarien: Ignore GBE LTR ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/31888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613 Gerrit-Change-Number: 31888 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Roy Park <roy.mingi.park(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Mar 2019 22:22:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Julius Werner (Code Review) 27 Mar '19

27 Mar '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29962 ) Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... Patch Set 18: (3 comments) Note that this code (and the previous patch about GPIOs) still needs to be deduplicated with the respective SDM845 code. I'd recommend waiting with merging these until that has happened. https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/clock.c File src/soc/qualcomm/qcs405/clock.c: https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/clock.c@251 PS18, Line 251: clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, This should probably go into uart_init(), not here. https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/clock.c@259 PS18, Line 259: clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, Clock configuration for individual peripheral drivers should be done by the peripheral driver (with frequency values passed in from mainboard code), not in the global clock init. So you probably want a function like clock_configure_spi(bus, freq) in here that is called by the spi_init(freq) of your SPI driver, and the freq value should be passed in from the mainboard/.../bootblock.c code that calls that. Also, please always use the KHz and MHz macros to make frequency values more readable (e.g. 1*MHz instead of 1000000). https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/clock.h: https://review.coreboot.org/#/c/29962/18/src/soc/qualcomm/qcs405/include/so… PS18, Line 24: #define REG(addr) ((void *)addr) Unused, please take it out (we usually don't like hiding casts in macros). -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 18 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 26 Mar 2019 21:36:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp uart driver
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 16: the iomap.h file here needs to come before the SPI driver support commit -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 16 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 26 Mar 2019 20:54:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Mistral: qcs405: Add support for USB host mode
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Mistral: qcs405: Add support for USB host mode ...................................................................... Patch Set 17: please split it up into a QCS commit and a mistral commit on top of that. -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 26 Mar 2019 20:54:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29962 ) Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... qcs405: clock: Adding the clock support for qcs405 Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Pranav Agrawal <pranava(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/addressmap.h A src/soc/qualcomm/qcs405/include/soc/clock.h 5 files changed, 449 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index c702264..89a7354 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -7,17 +7,20 @@ bootblock-y += spi.c bootblock-y += mmu.c bootblock-y += gpio.c +bootblock-y += clock.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c +verstage-y += clock.c ################################################################################ romstage-y += timer.c romstage-y += spi.c romstage-y += cbmem.c romstage-y += gpio.c +romstage-y += clock.c ################################################################################ ramstage-y += soc.c @@ -25,6 +28,7 @@ ramstage-y += spi.c ramstage-y += cbmem.c ramstage-y += gpio.c +ramstage-y += clock.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 5e63f13..15d1c18 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -15,6 +15,12 @@ #include <bootblock_common.h> #include <soc/mmu.h> +#include <soc/clock.h> + +void bootblock_soc_early_init(void) +{ + clock_init(); +} void bootblock_soc_init(void) { diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c new file mode 100644 index 0000000..31fdc3d --- /dev/null +++ b/src/soc/qualcomm/qcs405/clock.c @@ -0,0 +1,269 @@ + /* This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <types.h> +#include <console/console.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> +#include <commonlib/helpers.h> +#include <string.h> + +#include <soc/clock.h> + +#define DIV(div) (div ? (2*div - 1) : 0) +#define HALF_DIVIDER(div2x) (div2x ? (div2x - 1) : 0) + +struct clock_config uart_cfg[] = { + { + .hz = 1843200, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(0), + .m = 36, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 3686400, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(0), + .m = 72, + .n = 15625, + .d_2 = 15625, + } +}; + +struct clock_config i2c_cfg[] = { + { + .hz = 19200000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 50000000, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(32), + } +}; + +struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + }, + { + .hz = 7372800, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(1), + .m = 144, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 19200000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 30000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(0), + }, + { + .hz = 50000000, + .hw_ctl = 0x0, + .src = SRC_GPLL0_MAIN_800MHZ, + .div = DIV(32), + } +}; + +static int clock_configure_gpll0(void) +{ + /* Keep existing GPLL0 configuration, in RUN mode @800Mhz. */ + setbits_le32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_AUX2_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_AUX_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT); + return 0; +} + +static int clock_configure_mnd(struct qcs405_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + uint32_t reg_val; + + /* Configure Root Clock Generator(RCG) for Dual Edge Mode */ + reg_val = read32(&clk->rcg.cfg); + reg_val |= (2 << CLK_CTL_CFG_MODE_SHFT); + write32(&clk->rcg.cfg, reg_val); + + /* Set M/N/D config */ + write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure(struct qcs405_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg.cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(void *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)); + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_disable(void *cbcr_addr) +{ + + /* Set clock enable bit */ + clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + return 0; +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct qcs405_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_configure_uart(uint32_t hz) +{ + struct qcs405_clock *uart_clk = (struct qcs405_clock *) + &gcc->blsp1_uart2_apps_clk; + + clock_configure(uart_clk, uart_cfg, hz, ARRAY_SIZE(uart_cfg)); +} + +void clock_configure_spi(int blsp, uint32_t hz) +{ + struct qcs405_clock *spi_clk = (blsp == 1) ? + (struct qcs405_clock *)&gcc->blsp1_qup4_spi_clk + : (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk; + + clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); +} + +void clock_enable_uart(void) +{ + clock_enable(&gcc->blsp1_uart2_apps_cbcr); +} + +void clock_disable_uart(void) +{ + clock_disable(&gcc->blsp1_uart2_apps_cbcr); +} + +void clock_enable_spi(int blsp) +{ + (blsp == 1) ? clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr) + : clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); +} + +void clock_disable_spi(int blsp) +{ + (blsp == 1) ? clock_disable(&gcc->blsp1_qup4_spi_apps_cbcr) + : clock_disable(&gcc->blsp2_qup0_spi_apps_cbcr); +} + +void clock_init(void) +{ + + clock_configure_gpll0(); + + clock_configure(&gcc->blsp1_uart2_apps_clk, uart_cfg, 1843200, + ARRAY_SIZE(uart_cfg)); + + clock_enable(&gcc->blsp1_uart2_apps_cbcr); + clock_enable_vote(&gcc->blsp1_ahb_cbcr, + &gcc->gcc_apcs_clock_branch_en_vote, + BLSP1_AHB_CLK_ENA); + + clock_configure(&gcc->blsp1_qup4_spi_clk, spi_cfg, 1000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(&gcc->blsp1_qup4_spi_apps_cbcr); + + clock_configure(&gcc->blsp2_qup0_spi_clk, spi_cfg, 50000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(&gcc->blsp2_qup0_spi_apps_cbcr); + clock_enable_vote(&gcc->blsp2_ahb_cbcr, + &gcc->gcc_apcs_clock_branch_en_vote, + BLSP2_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index c85341b..30a30b6 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -22,5 +22,6 @@ #define TLMM_EAST_TILE_BASE 0x7B00000 #define TLMM_NORTH_TILE_BASE 0x1300000 #define TLMM_SOUTH_TILE_BASE 0x1000000 +#define GCC_BASE 0x01800000 #endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h new file mode 100644 index 0000000..2766f09 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -0,0 +1,169 @@ + /* This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/addressmap.h> +#include <types.h> + +#ifndef __SOC_QUALCOMM_QCS405_CLOCK_H__ +#define __SOC_QUALCOMM_QCS405_CLOCK_H__ + +#define BLSP1_AHB_CLK_ENA 10 +#define BLSP2_AHB_CLK_ENA 20 +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_800MHZ 1 +#define REG(addr) ((void *)addr) + +/** + * USB BCR registers + */ +#define GCC_USB_HS_PHY_CFG_AHB_BCR 0x1841038 +#define GCC_USB_HS_BCR 0x1841000 +#define GCC_USB_30_BCR 0x1839000 +#define GCC_USB2A_PHY_BCR 0x1841028 +#define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034 +#define GCC_QUSB2_PHY_BCR 0x184103C + +struct qcs405_rcg { + u32 cmd; + u32 cfg; +}; + +struct qcs405_clock { + struct qcs405_rcg rcg; + uint32_t m; + uint32_t n; + uint32_t d_2; +}; + +struct qcs405_bcr { + uint32_t bcr; +}; + +struct qcs405_gpll { + u32 mode; + u32 l_val; + u32 gpll_alpha_val; + u32 gpll_alpha_val_u; + u32 user_ctl; + u32 user_ctl_u; + u32 config_ctl; + u32 test_ctl; + u32 test_ctl_u; +}; + +struct qcs405_gcc { + u8 _res0[0x1000 - 0x0]; + u32 blsp1_bcr; + u32 blsp1_sleep_cbcr; + u32 blsp1_ahb_cbcr; + u8 _res1[0x3028 - 0x100c]; + u32 blsp1_uart2_bcr; + u32 blsp1_uart2_apps_cbcr; + u32 blsp1_uart2_sim_cbcr; + struct qcs405_clock blsp1_uart2_apps_clk; + u8 _res2[0x5018 - 0x3048]; + u32 blsp1_qup4_bcr; + u32 blsp1_qup4_spi_apps_cbcr; + u8 _res3[0x5024 - 0x5020]; + struct qcs405_clock blsp1_qup4_spi_clk; + u8 _res4[0xB000 - 0x5038]; + u32 blsp2_bcr; + u32 blsp2_sleep_cbcr; + u32 blsp2_ahb_cbcr; + u8 _res5[0xC000 - 0xB00C]; + u32 blsp2_qup0_bcr; + u32 blsp2_qup0_spi_apps_cbcr; + u8 _res6[0xC024 - 0xC008]; + struct qcs405_clock blsp2_qup0_spi_clk; + u8 _res7[0x21000 - 0xC038]; + struct qcs405_gpll gpll0; + u8 _res8[0x45004 - 0x21024]; + u32 gcc_apcs_clock_branch_en_vote; +}; + +struct mdss_clock_config { + const char *clk_name; + struct qcs405_clock *rcgr; + uint32_t *cbcr; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK = 0x8, + CLK_CTL_GPLL_PLLOUT_AUX2_BMSK = 0x4, + CLK_CTL_GPLL_PLLOUT_AUX_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_BMSK = 0x1, + CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT = 3, + CLK_CTL_GPLL_PLLOUT_AUX2_SHFT = 2, + CLK_CTL_GPLL_PLLOUT_AUX_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +struct clock_config { + uint32_t hz; + uint32_t hw_ctl; + uint32_t src; + uint32_t div; + uint32_t m; + uint32_t n; + uint32_t d_2; +}; + +static struct qcs405_gcc *const gcc = (void *)GCC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +int clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_uart(uint32_t hz); +void clock_configure_spi(int blsp, uint32_t hz); +void clock_enable_uart(void); +void clock_disable_uart(void); +void clock_enable_spi(int blsp); +void clock_disable_spi(int blsp); + +#endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 18 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29962 ) Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 26 Mar 2019 20:41:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add GPIO API
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29955 ) Change subject: qcs405: Add GPIO API ...................................................................... qcs405: Add GPIO API Introduce new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/gpio.c A src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/qcs405/include/soc/gpio.h 4 files changed, 400 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 2d1f842..c702264 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -6,21 +6,25 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-y += mmu.c +bootblock-y += gpio.c ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-y += gpio.c ################################################################################ romstage-y += timer.c romstage-y += spi.c romstage-y += cbmem.c +romstage-y += gpio.c ################################################################################ ramstage-y += soc.c ramstage-y += timer.c ramstage-y += spi.c ramstage-y += cbmem.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c new file mode 100644 index 0000000..db8b7a1 --- /dev/null +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <types.h> +#include <console/console.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> + +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); +} diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h new file mode 100644 index 0000000..c85341b --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ + +#include <stdint.h> + +#define QSPI_BASE 0x88DF000 +#define TLMM_EAST_TILE_BASE 0x7B00000 +#define TLMM_NORTH_TILE_BASE 0x1300000 +#define TLMM_SOUTH_TILE_BASE 0x1000000 + +#endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index e1ad453..fce4350 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -17,7 +17,299 @@ #define _SOC_QUALCOMM_QCS405_GPIO_H_ #include <types.h> +#include <soc/addressmap.h> -typedef u32 gpio_t; +typedef struct { + u32 addr; +} gpio_t; + +#define TLMM_TILE_SIZE 0x00400000 +#define TLMM_GPIO_OFF_DELTA 0x00001000 +#define TLMM_GPIO_TILE_NUM 3 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 149 + +#define GPIO_FUNC_GPIO 0 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(9, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(10, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(11, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(12, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(17, NORTH, BLSP_UART_TX_A, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(18, NORTH, BLSP_UART_RX_A, BLSP_SPI_MISO, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(19, NORTH, BLSP_UART_CTS_N, AUD_CDC_INT2, RES_3, BLSP_SPI_CS_N, + RES_5, RES_6, RES_7), + PIN(20, NORTH, BLSP_UART_RFR_N, RES_2, RES_3, BLSP_SPI_CLK, RES_5, + RES_6, RES_7), + PIN(21, SOUTH, M_VOC_EXT_VFR_REF_IRQ_2, RES_2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(22, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI_A, ASDIV1, RES_4, + RES_5, RES_6, RES_7), + PIN(23, NORTH, BLSP_UART_RX, BLSP_SPI_MISO_A, ASDIV2, RES_4, + RES_5, RES_6, RES_7), + PIN(24, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N_A, + RES_4, RES_5, RES_6, RES_7), + PIN(25, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK_A, + RES_4, RES_5, RES_6, RES_7), + PIN(26, EAST, RES_1, BLSP_UART_TX, BLSP_SPI_MOSI, RES_4, RES_5, + RES_6, RES_7), + PIN(27, EAST, RES_1, BLSP_UART_RX, BLSP_SPI_MISO, RES_4, RES_5, + RES_6, RES_7), + PIN(28, EAST, RES_1, BLSP_UART_CTS_N, RES_3, BLSP_SPI_CS_N, RES_5, + RES_6, RES_7), + PIN(29, EAST, RES_1, BLSP_UART_RFR_N, RES_3, BLSP_SPI_CLK, RES_5, + RES_6, RES_7), + PIN(30, NORTH, RES_1, BLSP_UART_TX, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(31, NORTH, RES_1, BLSP_UART_RX, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(32, NORTH, RES_1, BLSP_UART_CTS_N, BLSP_I2C_SDA, RES_4, RES_5, + RES_6, RES_7), + PIN(33, NORTH, RES_1, BLSP_UART_RFR_N, BLSP_I2C_SCL, RES_4, RES_5, + RES_6, RES_7), + PIN(34, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, PCIE_CLK_REQ, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(36, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(37, NORTH, NFC_IRQ, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(38, NORTH, RES_1, BLSP_SPI_MISO, AUDIO_TS_IN, RES_4, RES_5, + RES_6, RES_7), + PIN(39, EAST, RES_1, RES_2, BLSP_UART_TX_B, RES_4, RES_5, RES_6, + RES_7), + PIN(40, EAST, RES_1, RES_2, BLSP_UART_RX_B, RES_4, RES_5, RES_6, + RES_7), + PIN(41, EAST, RES_1, BLSP_I2C_SDA_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(42, EAST, RES_1, BLSP_I2C_SCL_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(43, EAST, RES_1, PWM_LED11, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, EAST, RES_1, PWM_LED12, BLSP_SPI_CS1_N, RES_4, RES_5, + RES_6, RES_7), + PIN(45, EAST, RES_1, PWM_LED13, BLSP_SPI_CS2_N, RES_4, RES_5, + RES_6, RES_7), + PIN(46, EAST, RES_1, PWM_LED14, BLSP_SPI_CS3_N, RES_4, RES_5, + RES_6, RES_7), + PIN(47, EAST, RES_1, PWM_LED15, BLSP_SPI_MOSI_B, RES_4, RES_5, + RES_6, RES_7), + PIN(48, EAST, RES_1, PWM_LED16, BLSP_SPI_MISO_B, RES_4, RES_5, + RES_6, RES_7), + PIN(49, EAST, RES_1, PWM_LED17, BLSP_SPI_CS_N_B, RES_4, RES_5, + RES_6, RES_7), + PIN(50, EAST, RES_1, PWM_LED18, BLSP_SPI_CLK_B, RES_4, RES_5, + RES_6, RES_7), + PIN(51, EAST, RES_1, PWM_LED19, EXT_MCLK1_B, RES_4, RES_5, RES_6, + RES_7), + PIN(52, EAST, RES_1, PWM_LED20, RES_3, I2S_3_SCK_B, RES_5, RES_6, + RES_7), + PIN(53, EAST, RES_1, PWM_LED21, I2S_3_WS_B, RES_4, RES_5, RES_6, + RES_7), + PIN(54, EAST, RES_1, I2S_3_DATA0_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(55, EAST, RES_1, I2S_3_DATA1_B, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(56, EAST, RES_1, RES_2, I2S_3_DATA2_B, RES_4, RES_5, RES_6, + RES_7), + PIN(57, EAST, RES_1, RES_2, I2S_3_DATA3_B, RES_4, RES_5, RES_6, + RES_7), + PIN(58, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(59, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(60, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(61, NORTH, RGMII_INT, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(62, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(63, NORTH, RGMII_CK_TX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(64, NORTH, RGMII_TX_3, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(65, NORTH, RGMII_TX_2, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(66, NORTH, RGMII_TX_1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(67, NORTH, RGMII_TX_0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(68, NORTH, RGMII_CTL_TX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(69, NORTH, RGMII_CK_RX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(70, NORTH, RGMII_RX_3, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(71, NORTH, RGMII_RX_2, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(72, NORTH, RGMII_RX_1, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(73, NORTH, RGMII_RX_0, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(74, NORTH, RGMII_CTL_RX, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(75, NORTH, RGMII_MDIO, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(76, NORTH, RGMII_MDC, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(77, NORTH, IR_IN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(78, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(79, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(80, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(81, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(82, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI, SD_WRITE_PROTECT, + RES_4, RES_5, RES_6, RES_7), + PIN(83, NORTH, BLSP_UART_RX, BLSP_SPI_MISO, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(84, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N, + RES_4, RES_5, RES_6, RES_7), + PIN(85, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK, RES_4, + RES_5, RES_6, RES_7), + PIN(86, EAST, RES_1, MCLK_IN1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, EAST, I2S_1_SCK, DSD_CLK_A, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(88, EAST, I2S_1_WS, I2S_1_DATA0_DSD0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(89, EAST, I2S_1_DATA0, I2S_1_DATA1_DSD1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(90, EAST, I2S_1_DATA1, I2S_1_DATA2_DSD2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(91, EAST, I2S_1_DATA2, I2S_1_DATA3_DSD3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(92, EAST, I2S_1_DATA3, I2S_1_DATA4_DSD4, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(93, EAST, I2S_1_DATA4, PWM_LED22, I2S_1_DATA5_DSD5, RES_4, + RES_5, RES_6, RES_7), + PIN(94, EAST, I2S_1_DATA5, PWM_LED23, I2S_1_DATA6_MIR, RES_4, + RES_5, RES_6, RES_7), + PIN(95, EAST, RES_1, PWM_LED1, I2S_1_DATA7_MIR, RES_4, RES_5, + RES_6, RES_7), + PIN(96, EAST, RES_1, PWM_LED2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(97, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(98, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(99, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(103, EAST, RES_1, MCLK_IN2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(104, EAST, I2S_3_SCK_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(105, EAST, I2S_3_WS_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(106, EAST, I2S_3_DATA0_A, RES_2, HDMI_HOT_PLUG_MIR, RES_4, + RES_5, RES_6, RES_7), + PIN(107, EAST, I2S_3_DATA1_A, RES_2, RES_3, RES_4, RES_5, RES_6, + RES_7), + PIN(108, EAST, I2S_3_DATA2_A, RES_2, RES_3, PWM_LED3, RES_5, + RES_6, RES_7), + PIN(109, EAST, I2S_3_DATA3_A, RES_2, PWM_LED4, RES_4, RES_5, + RES_6, RES_7), + PIN(110, EAST, RES_1, RES_2, DSD_CLK_B, PWM_LED5, RES_5, RES_6, + RES_7), + PIN(111, EAST, RES_1, I2S_4_DATA0_DSD0, PWM_LED6, RES_4, RES_5, + RES_6, RES_7), + PIN(112, EAST, RES_1, I2S_4_DATA1_DSD1, PWM_LED7, RES_4, RES_5, + RES_6, RES_7), + PIN(113, EAST, RES_1, I2S_4_DATA2_DSD2, PWM_LED8, RES_4, RES_5, + RES_6, RES_7), + PIN(114, EAST, RES_1, I2S_4_DATA3_DSD3, PWM_LED24, RES_4, RES_5, + RES_6, RES_7), + PIN(115, EAST, RES_1, I2S_4_DATA4_DSD4, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(116, EAST, I2S_4_DATA5_DSD5, SPKR_DAC0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(117, NORTH, BLSP_I2C_SDA, BLSP_SPI_CS_N, PWM_LED9, RES_4, + RES_5, RES_6, RES_7), + PIN(118, NORTH, BLSP_I2C_SCL, BLSP_SPI_CLK, PWM_LED10, RES_4, + RES_5, RES_6, RES_7), + PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); #endif // _SOC_QUALCOMM_QCS405_GPIO_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: merged

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Change in ...coreboot[master]: qcs405: Add GPIO API
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 ) Change subject: qcs405: Add GPIO API ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 16 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 26 Mar 2019 20:39:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: vboot: remove VBOOT_EC_SOFTWARE_SYNC Kconfig option
by Joel Kitching (Code Review) 27 Mar '19

27 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31926 Change subject: vboot: remove VBOOT_EC_SOFTWARE_SYNC Kconfig option ...................................................................... vboot: remove VBOOT_EC_SOFTWARE_SYNC Kconfig option This option is duplicated in depthcharge: https://crrev.com/c/1524811 BUG=b:124141368, b:124192753, b:128737909 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1524811 BRANCH=none Change-Id: Id8c207ec4ad5a476e24eee1ceb9e40f24d55e725 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/Kconfig M src/security/vboot/vboot_handoff.c 2 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31926/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 67853ab..ef5455f 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -176,15 +176,6 @@ bool default n -config VBOOT_EC_SOFTWARE_SYNC - bool "Enable EC software sync" - default y if EC_GOOGLE_CHROMEEC - default n - help - EC software sync is a mechanism where the AP helps the EC verify its - firmware similar to how vboot verifies the main system firmware. This - option selects whether vboot should support EC software sync. - config VBOOT_PHYSICAL_DEV_SWITCH bool default n diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 5ac627c..c916b6d 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -81,8 +81,6 @@ /* TODO: Set these in depthcharge */ if (!CONFIG(VBOOT_PHYSICAL_DEV_SWITCH)) vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; - if (CONFIG(VBOOT_EC_SOFTWARE_SYNC)) - vb_sd->flags |= VBSD_EC_SOFTWARE_SYNC; if (!CONFIG(VBOOT_PHYSICAL_REC_SWITCH)) vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; if (CONFIG(VBOOT_OPROM_MATTERS)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c207ec4ad5a476e24eee1ceb9e40f24d55e725 Gerrit-Change-Number: 31926 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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