coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: qcs405: Add GPIO API
by build bot (Jenkins) (Code Review) 26 Mar '19

26 Mar '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 ) Change subject: qcs405: Add GPIO API ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/#/c/29955/16/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/gpio.h: https://review.coreboot.org/#/c/29955/16/src/soc/qualcomm/qcs405/include/so… PS16, Line 87: #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 16 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Tue, 26 Mar 2019 14:14:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: QCS405: Added RPM support
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29970 to look at the new patch set (#17). Change subject: TEMP: NOT FOR REVIEW: Mistral: QCS405: Added RPM support ...................................................................... TEMP: NOT FOR REVIEW: Mistral: QCS405: Added RPM support This patch adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Note that, clock_reset_rpm function to touch the GCC registers actually should reside in clock.c, but for now keeping it here till clock patches are posted. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 7 files changed, 105 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qclib: Add qclib support
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29967 to look at the new patch set (#17). Change subject: TEMP: NOT FOR REVIEW: qclib: Add qclib support ...................................................................... TEMP: NOT FOR REVIEW: qclib: Add qclib support Add to load and execute qclib blob to configure pmic, clocks and ddr. This is the basic support without one-training and interface table to pass data between coreboot and qclib. That would be added later. Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/qclib_execute.c 9 files changed, 154 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: memlayout: Make bootblock 64k aligned
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29969 to look at the new patch set (#17). Change subject: TEMP: NOT FOR REVIEW: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... TEMP: NOT FOR REVIEW: qcs405: memlayout: Make bootblock 64k aligned The qc_sec in qcs405 excepts that bootblock to be 64k aligned. So adjust the memlayout accordingly. Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/armv8/bootblock.S M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 2 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29969/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Enable SPI-NOR
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29968 to look at the new patch set (#17). Change subject: qcs405: Enable SPI-NOR ...................................................................... qcs405: Enable SPI-NOR Enable support for WINBOND spi-nor flash. Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 17 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Mistral: qcs405: Add support for USB host mode
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29966 to look at the new patch set (#16). Change subject: Mistral: qcs405: Add support for USB host mode ...................................................................... Mistral: qcs405: Add support for USB host mode Add required changes for USB host mode working on mistral platform for USB disk enumeration. Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy(a)partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/mainboard.c A src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/clock.h A src/soc/qualcomm/qcs405/include/soc/usb.h A src/soc/qualcomm/qcs405/usb.c 7 files changed, 399 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29966/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 16 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: clock: Adding the clock support for qcs405
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29962 to look at the new patch set (#16). Change subject: qcs405: clock: Adding the clock support for qcs405 ...................................................................... qcs405: clock: Adding the clock support for qcs405 Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Pranav Agrawal <pranava(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/addressmap.h A src/soc/qualcomm/qcs405/include/soc/clock.h 5 files changed, 448 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29962/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Gerrit-Change-Number: 29962 Gerrit-PatchSet: 16 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add GPIO API
by Name of user not set (Code Review) 26 Mar '19

26 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29955 to look at the new patch set (#16). Change subject: qcs405: Add GPIO API ...................................................................... qcs405: Add GPIO API Introduce new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/gpio.c A src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/qcs405/include/soc/gpio.h 4 files changed, 400 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29955/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 16 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number
by HAOUAS Elyes (Code Review) 26 Mar '19

26 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29852 to look at the new patch set (#4). Change subject: vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number ...................................................................... vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number Change-Id: Ifdef135aa7517477a10657bb01f866ec41f5bdf7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29852/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdef135aa7517477a10657bb01f866ec41f5bdf7 Gerrit-Change-Number: 29852 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number.
by HAOUAS Elyes (Code Review) 26 Mar '19

26 Mar '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29852 to look at the new patch set (#2). Change subject: src/vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number. ...................................................................... src/vendorcodeamd/pi/00630F01: Fix invalid hexadecimal number. Change-Id: Ifdef135aa7517477a10657bb01f866ec41f5bdf7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29852/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdef135aa7517477a10657bb01f866ec41f5bdf7 Gerrit-Change-Number: 29852 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2019