coreboot-gerrit March 2019

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Change in ...coreboot[master]: mb/google/hatch: Add GPIO_A8 for Pen detect function
by Dtrain Hsu (Code Review) 27 Mar '19

27 Mar '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31815 Change subject: mb/google/hatch: Add GPIO_A8 for Pen detect function ...................................................................... mb/google/hatch: Add GPIO_A8 for Pen detect function Add GPIO_A8 for pen detect function. BUG=b:122765828 TEST=flash BIOS and using switch to verify GPIO_A8 value change. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 3 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31815/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 2290d8c..8e9ab9c 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -6,6 +6,7 @@ select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI + select DRIVERS_GENERIC_GPIO_KEYS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e2c3392..885105e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -220,7 +220,17 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A8)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #2 device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 35dd912..d66328b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -30,8 +30,8 @@ PAD_CFG_GPI_APIC(GPP_A6, NONE, DEEP, LEVEL, NONE), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : EMR_GARAGE_DET ==> NC */ - PAD_NC(GPP_A8, NONE), + /* A8 : PEN_EJECT(notifications) */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_A8, UP_20K, DEEP), /* A9 : ESPI_CLK */ /* A10 : PEN_RESET_ODL */ PAD_NC(GPP_A10, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/31815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be Gerrit-Change-Number: 31815 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants: Remove bip
by Evan Green (Code Review) 27 Mar '19

27 Mar '19

Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32053 Change subject: mb/google/octopus/variants: Remove bip ...................................................................... mb/google/octopus/variants: Remove bip Remove bip, as it is no longer actively developed, and its EC overflowed storage, so the EC build is no longer viable. BUG=b:129283539 BRANCH=none TEST=emerge-octopus coreboot chromeos-bootimage CQ-DEPEND=CL:1538819,CL:*1086038 Change-Id: Ie9ffa704af3523908858d382e2c188422323550e --- M Documentation/releases/coreboot-4.8.1-relnotes.md M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name D src/mainboard/google/octopus/variants/bip/Makefile.inc D src/mainboard/google/octopus/variants/bip/gpio.c D src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl D src/mainboard/google/octopus/variants/bip/include/variant/ec.h D src/mainboard/google/octopus/variants/bip/include/variant/gpio.h D src/mainboard/google/octopus/variants/bip/overridetree.cb 9 files changed, 0 insertions(+), 451 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32053/1 diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md index 8a6ab96..a1fc57a 100644 --- a/Documentation/releases/coreboot-4.8.1-relnotes.md +++ b/Documentation/releases/coreboot-4.8.1-relnotes.md @@ -92,7 +92,6 @@ ------------------- * Asus MAXIMUS_IV_GENE_Z Intel Sandybridge * Google ATLAS Intel Kabylake -* Google BIP Intel Geminilake * Google CHEZA Qualcomm SDM845 * Google NOCTURNE Intel Kabylake * Google OCTOPUS Intel Geminilake diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 6dd062a..9c0a2f7 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -51,7 +51,6 @@ config VARIANT_DIR string default "yorp" if BOARD_GOOGLE_YORP - default "bip" if BOARD_GOOGLE_BIP default "phaser" if BOARD_GOOGLE_PHASER default "fleex" if BOARD_GOOGLE_FLEEX default "bobba" if BOARD_GOOGLE_BOBBA @@ -72,7 +71,6 @@ config MAINBOARD_PART_NUMBER string default "Yorp" if BOARD_GOOGLE_YORP - default "Bip" if BOARD_GOOGLE_BIP default "Phaser" if BOARD_GOOGLE_PHASER default "Fleex" if BOARD_GOOGLE_FLEEX default "Bobba" if BOARD_GOOGLE_BOBBA @@ -90,7 +88,6 @@ string depends on CHROMEOS default "YORP TEST 7755" if BOARD_GOOGLE_YORP - default "BIP TEST 5732" if BOARD_GOOGLE_BIP default "PHASER TEST 7167" if BOARD_GOOGLE_PHASER default "FLEEX TEST 7423" if BOARD_GOOGLE_FLEEX default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA @@ -142,7 +139,6 @@ int depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI default 255 if BOARD_GOOGLE_YORP - default 255 if BOARD_GOOGLE_BIP default 2 if BOARD_GOOGLE_PHASER default 2 if BOARD_GOOGLE_FLEEX default 3 if BOARD_GOOGLE_BOBBA diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index adc7060..e5684e0 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -11,12 +11,6 @@ select BASEBOARD_OCTOPUS_LAPTOP select NHLT_DA7219 if INCLUDE_NHLT_BLOBS -config BOARD_GOOGLE_BIP - bool "-> Bip" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - config BOARD_GOOGLE_PHASER bool "-> Phaser" select BASEBOARD_OCTOPUS_LAPTOP diff --git a/src/mainboard/google/octopus/variants/bip/Makefile.inc b/src/mainboard/google/octopus/variants/bip/Makefile.inc deleted file mode 100644 index 7c092e4..0000000 --- a/src/mainboard/google/octopus/variants/bip/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -bootblock-y += gpio.c - -ramstage-y += gpio.c - -smm-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c deleted file mode 100644 index cf9de33..0000000 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> - -/* - * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' - * table found in EDS vol 1, but some pins aren't grouped functionally in - * the table so those were moved for more logical grouping. - */ -static const struct pad_config gpio_table[] = { - /* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */ - PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, NONE, DEEP, NF1), /* CX_PREQ_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, NONE, DEEP, NF1), /* CX_PRDY_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */ - PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ - PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ - PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ - PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ - PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ - PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ - PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ - PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ - - /* PMC stays active in suspend so disable standby for these pins */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ - PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ - PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ - PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */ - PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ - PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ - PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ - PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ - PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ - PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ - PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ - PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ - PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ - - /* NORTH COMMUNITY GPIOS */ - - /* svid - unused */ - PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ - PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ - PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ - - /* LPSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */ - PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ - PAD_NC(GPIO_84, NONE), /* LPSS_SPI_2_CLK - unused */ - PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */ - PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */ - PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */ - PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */ - PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */ - - /* Fast SPI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ - PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */ - PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ - - /* PMU Signals */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/* PMU_PLTRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ - PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ - PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ - - /* I2C5 - Audio */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ - - /* I2C6 - Trackpad */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ - - /* I2C7 - Touchscreen */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ - - /* PCIE_WAKE[0:3]_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ - PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ - PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ - PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ - - /* - * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination - * guideline for unused PCIE ports as described in PDG i.e. keep - * the pins in native mode and deploy the internal pull up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ - - /* DDI[0:1] SDA and SCL -- unused */ - PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ - PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ - PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ - PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ - - /* Panel 0 control */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */ - - /* Hot plug detect. */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ - - PAD_NC(GPIO_134, NONE),/* GPIO_134 -- unused */ - PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, - DISPUPD),/* GPIO_137 -- HP_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ - // Also we may be able to use eSPI WAKE# Virtual Wire instead - PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_145, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTEN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTCTL */ - - /* - * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for - * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO - * and kept unconnected to allow S0ix entry. - */ - - /* AUDIO COMMUNITY GPIOS*/ - PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ - PAD_NC(GPIO_157, DN_20K),/* AVS_I2S0_BCLK -- unused */ - PAD_NC(GPIO_158, DN_20K),/* AVS_I2S0_WS_SYNC -- unused */ - PAD_NC(GPIO_159, DN_20K),/* AVS_I2S0_SDI -- unused */ - PAD_NC(GPIO_160, DN_20K),/* AVS_I2S0_SDO -- unused */ - PAD_NC(GPIO_161, DN_20K),/* AVS_I2S1_MCLK -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ - - /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */ - PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ - PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */ - PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ - - /* SCC COMMUNITY GPIOS */ - PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ - PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ - PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ - PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ - PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ - PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */ - PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */ - PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */ - PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */ - PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */ - PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */ - PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */ - PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ - - /* - * Disable standby state for these CNVI pins to allow wake on - * WiFI & Bluetooth. - */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ - PAD_NC(GPIO_210, DN_20K), -}; - -const struct pad_config *variant_base_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ - /* GSPI0_INT */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), /* H1_PCH_INT_ODL */ - /* GSPI0_CLK */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ - /* GSPI0_CS# */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ - /* GSPI0_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ - /* GSPI0_MOSI */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ - - /* Enable power to wifi early in bootblock and de-assert PERST#. */ - PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ - - /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak - * pull-up for proper operation. Since there is no external pull present - * on this platform, configure an internal weak pull-up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), /* ESPI_IO1 */ -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl deleted file mode 100644 index cc17d56..0000000 --- a/src/mainboard/google/octopus/variants/bip/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/bip/include/variant/ec.h b/src/mainboard/google/octopus/variants/bip/include/variant/ec.h deleted file mode 100644 index 16f931b..0000000 --- a/src/mainboard/google/octopus/variants/bip/include/variant/ec.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/octopus/variants/bip/include/variant/gpio.h b/src/mainboard/google/octopus/variants/bip/include/variant/gpio.h deleted file mode 100644 index 1fd1e11..0000000 --- a/src/mainboard/google/octopus/variants/bip/include/variant/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <baseboard/gpio.h> - -#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/bip/overridetree.cb b/src/mainboard/google/octopus/variants/bip/overridetree.cb deleted file mode 100644 index 7271d56..0000000 --- a/src/mainboard/google/octopus/variants/bip/overridetree.cb +++ /dev/null @@ -1,56 +0,0 @@ -chip soc/intel/apollolake - - device domain 0 on - device pci 16.0 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM50C1"" - register "generic.desc" = ""WCOM Digitizer"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "generic.reset_delay_ms" = "20" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 0 - device pci 17.1 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end # - I2C 5 - device pci 17.2 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" - register "wake" = "GPE0_DW3_27" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 6 - device pci 17.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end # - I2C 7 - end -end -- To view, visit https://review.coreboot.org/c/coreboot/+/32053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9ffa704af3523908858d382e2c188422323550e Gerrit-Change-Number: 32053 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: chromeos: update old boards to use lb_add_gpios notation
by Joel Kitching (Code Review) 27 Mar '19

27 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32031 Change subject: chromeos: update old boards to use lb_add_gpios notation ...................................................................... chromeos: update old boards to use lb_add_gpios notation Instead of manually filling out the lb_gpios struct, use the newer lb_add_gpios notation, which is more compact and less error-prone. BUG=b:124141368 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: I90795f32be5de881c94519933f36127098c184df Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 11 files changed, 155 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32031/1 diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 11b28cd..a956e28 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -33,53 +33,28 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO active Low */ + {WP_GPIO, ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, - int lidswitch = 0; - if (!gpio_base) - return; + /* Recovery: virtual GPIO active high */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + /* lid switch value from EC */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - /* Write Protect: GPIO active Low */ - gpios->gpios[0].port = WP_GPIO; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Power Button - Hardcode Low as power button may still be + * pressed when read here.*/ + {-1, ACTIVE_HIGH, 0, "power"}, - /* Recovery: virtual GPIO active high */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* lid switch value from EC */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); - printk(BIOS_DEBUG,"LID SWITCH FROM EC: %x\n", lidswitch); - - /* Power Button - Hardcode Low as power button may still be pressed - when read here.*/ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - + /* Was VGA Option ROM loaded? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index ae456b4..65139bb 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -25,44 +25,21 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low (WP_GPIO) */ + {EXYNOS5_GPD1, ACTIVE_LOW, gpio_get_value(GPIO_D16), + "write protect"}, - /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active low */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* Lid: active high (LID_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"}, - /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* Power: virtual GPIO active low (POWER_GPIO) */ + {EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X13), "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 4cf2a85..024fd4c 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -24,46 +24,21 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; - /* TBD(twarren(a)nvidia.com): Any analogs for these on Foster-FFD? */ + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low */ + {-1, ACTIVE_LOW, get_write_protect_state(), "write protect"}, - /* Write Protect: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active high */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Recovery: active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* TODO: Power: active low / high depending on board id */ + {GPIO(X5), ACTIVE_LOW, -1, "power"}, - /* TODO: Power: active low / high depending on board id */ - gpios->gpios[count].port = GPIO(X5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - /* TODO: Reset: active low (output) */ - gpios->gpios[count].port = GPIO(I5); - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = -1; - strncpy((char *)gpios->gpios[count].name, "reset", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* TODO: Reset: active low (output) */ + {GPIO(I5), ACTIVE_LOW, -1, "reset"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 335f1f7..5156404 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -22,43 +22,28 @@ #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO57 = PCH_SPI_WP_D */ + {57, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - /* Write Protect: GPIO57 = PCH_SPI_WP_D */ - gpios->gpios[0].port = 57; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - /* Recovery: the "switch" comes from the EC */ - gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Recovery: the "switch" comes from the EC */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Lid: the "switch" comes from the EC */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_lid_switch(); - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Lid: the "switch" comes from the EC */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - /* Power Button: hard-coded as not pressed; we'll detect later presses - * via SMI. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 0; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); + /* Power Button: hard-coded as not pressed; we'll detect later + * presses via SMI. */ + {-1, ACTIVE_HIGH, 0, "power"}, - /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 1420bf5..ede600c 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -30,8 +30,6 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -41,39 +39,24 @@ if (!gpio_base) return; - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO70 active high */ + {70, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Write Protect: GPIO70 active high */ - gpios->gpios[0].port = 70; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); + /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Lid switch GPIO active high (open). */ + {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, - /* Lid switch GPIO active high (open). */ - gpios->gpios[3].port = 15; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, - /* Power Button */ - gpios->gpios[4].port = 101; - gpios->gpios[4].polarity = ACTIVE_LOW; - gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index e782986..6f3b8b7 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -25,44 +25,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - int count = 0; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: active low (WP_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_LOW, gpio_get_value(GPIO_X30), "write protect"}, - /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO - strncpy((char *)gpios->gpios[count].name, "write protect", - GPIO_MAX_NAME_LENGTH); - count++; + /* Recovery: active low */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Recovery: active low */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[count].name, "recovery", - GPIO_MAX_NAME_LENGTH); - count++; + /* Lid: active high (LID_GPIO) */ + {EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X34), "lid"}, - /* Lid: active high */ - gpios->gpios[count].port = EXYNOS5_GPX3; - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO - strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); - count++; - - /* Power: virtual GPIO active low */ - gpios->gpios[count].port = EXYNOS5_GPX1; - gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = - gpio_get_value(GPIO_X12); // POWER_GPIO - strncpy((char *)gpios->gpios[count].name, "power", - GPIO_MAX_NAME_LENGTH); - count++; - - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); - gpios->count = count; - - printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); + /* Power: virtual GPIO active low (POWER_GPIO) */ + {EXYNOS5_GPX1, ACTIVE_LOW, gpio_get_value(GPIO_X12), "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index d366e40..015e0aa 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -29,49 +29,30 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 7 - void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO7 */ + {7, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, - /* Write Protect: GPIO7 */ - gpios->gpios[0].port = 7; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = !get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: Virtual switch */ + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - /* Recovery: Virtual switch */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Lid Switch: Virtual switch */ + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - /* Lid Switch: Virtual switch */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = get_lid_switch(); - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button: Virtual switch */ + /* Hard-code value to de-asserted */ + {-1, ACTIVE_HIGH, 0, "power"}, - /* Power Button: Virtual switch */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; /* Hard-code to de-asserted */ - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); + /* Was VGA Option ROM loaded? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); - - /* EC is in RW mode when it isn't in recovery mode. */ - gpios->gpios[6].port = -1; - gpios->gpios[6].polarity = ACTIVE_HIGH; - gpios->gpios[6].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[6].name,"ec_in_rw", GPIO_MAX_NAME_LENGTH); + /* EC is in RW mode when it isn't in recovery mode. */ + {-1, ACTIVE_HIGH, !get_recovery_mode_switch(), "ec_in_rw"} + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 1c62e5e..f38f6d4 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -26,8 +26,6 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -39,39 +37,23 @@ u32 gp_lvl = inl(gpio_base + GP_LVL); u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO22 */ + {0, ACTIVE_LOW, (gp_lvl >> 22) & 1, "write protect"}, - /* Write Protect: GPIO22 */ - gpios->gpios[0].port = 0; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl >> 22) & 1; - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ + {69, ACTIVE_HIGH, (gp_lvl3 >> (69-64)) & 1, "recovery"}, - /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - gpios->gpios[1].port = 69; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1; - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {-1, ACTIVE_HIGH, 1, "lid"}, - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {-1, ACTIVE_HIGH, 0, "power"}, - /* Power Button */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA option ROM? */ - gpios->gpios[5].port = -1; - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA option ROM? */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 8c0aeea..31efe29 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -26,8 +26,6 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); @@ -40,39 +38,23 @@ u32 gp_lvl2 = inl(gpio_base + 0x38); /* u32 gp_lvl3 = inl(gpio_base + 0x48); */ - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO48 */ + {48, ACTIVE_LOW, (gp_lvl2 >> (48-32)) & 1, "write protect"}, - /* Write Protect: GPIO48 */ - gpios->gpios[0].port = 48; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1; - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO22 */ + {22, ACTIVE_LOW, (gp_lvl >> 22) & 1, "recovery"}, - /* Recovery: GPIO22 */ - gpios->gpios[1].port = 22; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = (gp_lvl >> 22) & 1; - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {-1, ACTIVE_HIGH, 1, "lid"}, - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {-1, ACTIVE_HIGH, 0, "power"}, - /* Power Button */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA option ROM? */ - gpios->gpios[5].port = -1; - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA option ROM? */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 5d688fe..2d4fb61 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -34,46 +34,31 @@ #include "ec.h" #include <ec/smsc/mec1308/ec.h> -#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); - u8 lid = ec_read(0x83); + u8 lid = ec_read(0x83); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO24 = KBC3_SPI_WP# */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, - /* Write Protect: GPIO24 = KBC3_SPI_WP# */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"}, - /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + {100, ACTIVE_HIGH, lid & 1, "lid"}, - gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = lid & 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, - /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 295c31f..b1ad137 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -31,46 +31,31 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 5 - void fill_lb_gpios(struct lb_gpios *gpios) { struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio chromeos_gpios[] = { + /* Write Protect: GPIO68 = CHP3_SPI_WP */ + {GPIO_SPI_WP, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, - /* Write Protect: GPIO68 = CHP3_SPI_WP */ - gpios->gpios[0].port = GPIO_SPI_WP; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + /* Recovery: GPIO42 = CHP3_REC_MODE# */ + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), + "recovery"}, - /* Recovery: GPIO42 = CHP3_REC_MODE# */ - gpios->gpios[1].port = GPIO_REC_MODE; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = !get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + /* Hard code the lid switch GPIO to open. */ + {100, ACTIVE_HIGH, 1, "lid"}, - /* Hard code the lid switch GPIO to open. */ - gpios->gpios[2].port = 100; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = 1; - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + /* Power Button */ + {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, - /* Power Button */ - gpios->gpios[3].port = 101; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH); + /* Did we load the VGA Option ROM? */ + /* -1 indicates that this is a pseudo GPIO */ + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90795f32be5de881c94519933f36127098c184df Gerrit-Change-Number: 32031 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

6 12

Change in ...coreboot[master]: vboot_handoff: no need to set VBSD_HONOR_VIRT_DEV_SWITCH
by Joel Kitching (Code Review) 27 Mar '19

27 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31952 Change subject: vboot_handoff: no need to set VBSD_HONOR_VIRT_DEV_SWITCH ...................................................................... vboot_handoff: no need to set VBSD_HONOR_VIRT_DEV_SWITCH As part of chromium:942901, physical dev switch functionality is being deprecated. This flag is no longer read after CL:1526070. coreboot's vboot subrepository needs to be updated to include CL:1526070 before this CL can be merged. BUG=b:124141368, b:124192753, chromium:942901 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1526070 BRANCH=none Change-Id: Ie5849f9e0fcb8e4e6d35d542a141bf635e751af4 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_handoff.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31952/1 diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 6f5b0a3..9e76073 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -79,7 +79,6 @@ vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } /* TODO: Set these in depthcharge */ - vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; if (!CONFIG(VBOOT_PHYSICAL_REC_SWITCH)) vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; if (CONFIG(VBOOT_OPROM_MATTERS)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5849f9e0fcb8e4e6d35d542a141bf635e751af4 Gerrit-Change-Number: 31952 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: vboot: deprecate physical dev switch
by Joel Kitching (Code Review) 27 Mar '19

27 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31943 Change subject: vboot: deprecate physical dev switch ...................................................................... vboot: deprecate physical dev switch Currently only two devices make use of physical dev switch: stumpy, lumpy Deprecate this switch. If these devices are flashed to ToT, they may still make use of virtual dev switch, activated via recovery screen. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/include/bootmode.h M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/samsung/stumpy/chromeos.c M src/security/vboot/Kconfig M src/security/vboot/vboot_handoff.c M src/security/vboot/vboot_logic.c 9 files changed, 1 insertion(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31943/1 diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 5650b3d..33148dc 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -19,7 +19,6 @@ /* functions implemented per mainboard: */ void init_bootmode_straps(void); int get_write_protect_state(void); -int get_developer_mode_switch(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 1da0d29..07d92e9 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -26,7 +26,6 @@ struct lb_gpio chromeos_gpios[] = { {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, @@ -35,12 +34,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_developer_mode_switch(void) -{ - /* No physical developer mode switch. It's virtual. */ - return 0; -} - int get_write_protect_state(void) { return 0; diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 68aeabd..37c967f 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -25,7 +25,6 @@ select INTEL_INT15 config VBOOT - select VBOOT_PHYSICAL_DEV_SWITCH select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index baa4094..ba00245 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -60,12 +60,6 @@ gpios->gpios[1].value = !get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: GPIO17 = KBC3_DVP_MODE */ - gpios->gpios[2].port = GPIO_DEV_MODE; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); - gpios->gpios[3].port = 100; gpios->gpios[3].polarity = ACTIVE_HIGH; gpios->gpios[3].value = lid & 1; @@ -95,16 +89,6 @@ return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } -int get_developer_mode_switch(void) -{ -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; -} - int get_recovery_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 36e28ff..d17dc68 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -21,7 +21,6 @@ select INTEL_INT15 config VBOOT - select VBOOT_PHYSICAL_DEV_SWITCH select VBOOT_PHYSICAL_REC_SWITCH select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 85f9038..b3c66c5 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -56,12 +56,6 @@ gpios->gpios[1].value = !get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: GPIO17 = KBC3_DVP_MODE */ - gpios->gpios[2].port = GPIO_DEV_MODE; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); - /* Hard code the lid switch GPIO to open. */ gpios->gpios[3].port = 100; gpios->gpios[3].polarity = ACTIVE_HIGH; @@ -92,16 +86,6 @@ return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } -int get_developer_mode_switch(void) -{ -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; -} - int get_recovery_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ef5455f..8a8f8dc 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -176,15 +176,6 @@ bool default n -config VBOOT_PHYSICAL_DEV_SWITCH - bool - default n - help - Whether this platform has a physical developer switch. Note that this - disables virtual dev switch functionality (through secdata). Operation - where both a physical pin and the virtual switch get sampled is not - supported by coreboot. - config VBOOT_PHYSICAL_REC_SWITCH bool default n diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index c916b6d..6f5b0a3 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -79,8 +79,7 @@ vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } /* TODO: Set these in depthcharge */ - if (!CONFIG(VBOOT_PHYSICAL_DEV_SWITCH)) - vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; + vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH; if (!CONFIG(VBOOT_PHYSICAL_REC_SWITCH)) vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL; if (CONFIG(VBOOT_OPROM_MATTERS)) { diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 4aab795..a074539 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -324,10 +324,6 @@ die("Initializing measured boot mode failed!"); } - if (CONFIG(VBOOT_PHYSICAL_DEV_SWITCH) && - get_developer_mode_switch()) - ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; - if (get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) -- To view, visit https://review.coreboot.org/c/coreboot/+/31943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193 Gerrit-Change-Number: 31943 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: enable VMX support
by Furquan Shaikh (Code Review) 27 Mar '19

27 Mar '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31928 ) Change subject: soc/intel/cannonlake: enable VMX support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31928/4/src/soc/intel/cannonlake/cpu.c File src/soc/intel/cannonlake/cpu.c: https://review.coreboot.org/#/c/31928/4/src/soc/intel/cannonlake/cpu.c@428 PS4, Line 428: set_vmx_and_lock Can this be done based on CONFIG(ENABLE_VMX) and get rid of VmxEnable from device tree? -- To view, visit https://review.coreboot.org/c/coreboot/+/31928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156 Gerrit-Change-Number: 31928 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Wed, 27 Mar 2019 05:56:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: device/pciexp_device: Add set_L1_ss_latency() for pciexp device
by Subrata Banik (Code Review) 27 Mar '19

27 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31951 Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device ...................................................................... device/pciexp_device: Add set_L1_ss_latency() for pciexp device This patch performs below operations 1. Add new function to perform L1 latency programming for PCIE devices. 2. Remove duplicate implementaion of PCIE L1 latency programming and refer the same from common pciexp_device.c. Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c 4 files changed, 17 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31951/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 318f8cd..e4af9b2 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -463,6 +463,14 @@ pciexp_enable_ltr(dev); } +void pciexp_set_L1_ss_max_latency(struct device *dev, unsigned int offset) +{ + /* Set max snoop and non-snoop latency for the SOC */ + pci_write_config32(dev, offset, + PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | + PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); +} + void pciexp_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 121b998..459eef5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -5,6 +5,11 @@ /* PCI-E Sub-System ID */ #define PCIE_SUBSYSTEM_VENDOR_ID 0x94 +/* Latency tolerance reporting, max non-snoop latency value 3.14ms */ +#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 +/* Latency tolerance reporting, max snoop latency value 3.14ms */ +#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 + enum aspm_type { PCIE_ASPM_NONE = 0, PCIE_ASPM_L0S = 1, @@ -29,4 +34,6 @@ void pciexp_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); +void pciexp_set_L1_ss_max_latency(struct device *dev, unsigned int offset); + #endif /* DEVICE_PCIEXP_H */ diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index fdb8782..72e9884 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,15 +649,9 @@ root_port_commit_config(); } -static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) -{ - /* Set max snoop and non-snoop latency for Broadwell */ - pci_write_config32(dev, off, 0x10031003); -} - static struct pci_operations pcie_ops = { .set_subsystem = pciexp_set_subsystem, - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_L1_ss_latency = pciexp_set_L1_ss_max_latency, }; static struct device_operations device_ops = { diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 1c3114b..f02c38b 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -21,10 +21,6 @@ #include <device/pci_ops.h> #define CACHE_LINE_SIZE 0x10 -/* Latency tolerance reporting, max non-snoop latency value 3.14ms */ -#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 -/* Latency tolerance reporting, max snoop latency value 3.14ms */ -#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 static void pch_pcie_init(struct device *dev) { @@ -62,16 +58,8 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) -{ - /* Set max snoop and non-snoop latency for the SOC */ - pci_write_config32(dev, offset, - PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | - PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); -} - static struct pci_operations pcie_ops = { - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, + .set_L1_ss_latency = pciexp_set_L1_ss_max_latency, .set_subsystem = pciexp_set_subsystem, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Gerrit-Change-Number: 31951 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Move eventlog support into common code
by Subrata Banik (Code Review) 27 Mar '19

27 Mar '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31967 ) Change subject: soc/intel/common: Move eventlog support into common code ...................................................................... Patch Set 3: what about KBL, ICL, GLK using the same? -- To view, visit https://review.coreboot.org/c/coreboot/+/31967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf1f69b15487c9a08f1ddaeab055880eef9c2f24 Gerrit-Change-Number: 31967 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2019 04:39:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/usb: Fix USB acpi gpio programming
by Lijian Zhao (Code Review) 27 Mar '19

27 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31905 Change subject: drivers/usb: Fix USB acpi gpio programming ...................................................................... drivers/usb: Fix USB acpi gpio programming GPIO programming for transition between D0 and D3 state will require power resources to be present. Otherwise the previously defined "reset-gpio" can't take effect. BUG=b:123342945 TEST=Boot up on Arcada platform and extract SSDT table, find the GPIOIO entry and set/clear and "_ON/_OFF" present under USB devices after reset-gpio entry added in devicetree.cb file. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: If312150b5065e2e3fb362e9433cdeff47064a35a --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31905/1 diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 512893d..51dec63 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -56,7 +56,29 @@ bool use_custom_pld; struct acpi_pld custom_pld; + /* Does the device have a power resource? */ + bool has_power_resource; + + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + + /* GPIO used to stop operation of device. */ + struct acpi_gpio stop_gpio; + /* Delay to be inserted after disabling stop. */ + unsigned int stop_delay_ms; + /* Delay to be inserted after enabling stop. */ + unsigned int stop_off_delay_ms; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 8c63d2a..e77472c 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -76,6 +76,22 @@ acpi_dp_write(dsd); } + /* Power Resource */ + if (config->has_power_resource) { + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + &config->stop_gpio, + config->stop_delay_ms, + config->stop_off_delay_ms + }; + acpi_device_add_power_res(&power_res_params); + } + acpigen_pop_len(); printk(BIOS_INFO, "%s: %s at %s\n", path, -- To view, visit https://review.coreboot.org/c/coreboot/+/31905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If312150b5065e2e3fb362e9433cdeff47064a35a Gerrit-Change-Number: 31905 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by Julius Werner (Code Review) 27 Mar '19

27 Mar '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 ) Change subject: sdm845: Add SPI QUP driver ...................................................................... Patch Set 46: (7 comments) Great, this looks almost ready to go. I suggest rebasing it before the blob-dependent patches so we can land it. https://review.coreboot.org/#/c/27483/46/src/mainboard/google/cheza/bootblo… File src/mainboard/google/cheza/bootblock.c: https://review.coreboot.org/#/c/27483/46/src/mainboard/google/cheza/bootblo… PS46, Line 24: qup_spi_init(10, 1010 * KHz); Please add comments describing which devices (EC and H1) these are connected to. https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/bootblock.c File src/soc/qualcomm/sdm845/bootblock.c: https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/bootblock.… PS46, Line 4: * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. nit: file not actually changing anymore? https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h: https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/include/so… PS46, Line 203: union proto_rx_trans_len { nit: is there a point in having this as a union? Why not just name the field tx_trans_len? (Goes for the others as well...) https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/spi_qup.c File src/soc/qualcomm/sdm845/spi_qup.c: https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/spi_qup.c@… PS46, Line 58: extern struct qup qup[16]; This declaration should go in qcom_qup_se.h, not here. https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/spi_qup.c@… PS46, Line 195: setup_fifo_params(slave); Sorry if I asked this before and forgot again... do we really need to do this again on every transfer? Wouldn't it be enough to do it once in qup_spi_init()? https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/spi_qup.c@… PS46, Line 237: if (!(m_irq & M_CMD_DONE_EN) || ((m_irq & M_CMD_DONE_EN) !A || (A && B) can be simplified to !A || B. So this can just be if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/spi_qup.c@… PS46, Line 273: assert(((DEFAULT_SE_CLK - speed_hz * div) <= div * KHz) && (div > 0)); nit: better put this at the top, right after div is calculated (before writing it to m_clk_cfg). Also maybe add an explaining comment (e.g. /* make sure div can hit target frequency within +/- 1KHz range */). -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 46 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Mar 2019 00:55:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2019