coreboot-gerrit March 2019

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Change in ...coreboot[master]: prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist
by Subrata Banik (Code Review) 08 Mar '19

08 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31608 Change subject: prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist ...................................................................... prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist This patch adds timestamp for "end of romstage" with postcar if platform has selected postcar as dedicated stage. If postcar stage doesn't exist then "end of romstage" timestamp will get call while starting of ramstage as exist today. TEST=Its been observed that "end of romstage" timestamp doesn't appear in "cbmem -t" log when ramstage is not getting executed. As part of this fix "end of romstage" timestamp is showing in "cbmem -t" log on IA platform where POSTCAR is a dedicated stage. Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/postcar_loader.c M src/lib/prog_loaders.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31608/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 141e8d2..8d1cab4 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -23,6 +23,7 @@ #include <rmodule.h> #include <romstage_handoff.h> #include <stage_cache.h> +#include <timestamp.h> static inline void stack_push(struct postcar_frame *pcf, uint32_t val) { @@ -159,6 +160,9 @@ struct prog prog = PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar"); + /* As postcar exist, its end of romstage here */ + timestamp_add_now(TS_END_ROMSTAGE); + postcar_commit_mtrrs(pcf); if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) && diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 70ea7ef..5baeb8b 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -128,7 +128,9 @@ struct prog ramstage = PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage"); - timestamp_add_now(TS_END_ROMSTAGE); + /* Call "end of romstage" here if postcar stage doesn't exist */ + if (!IS_ENABLED(CONFIG_ARCH_POSTCAR_X86_32)) + timestamp_add_now(TS_END_ROMSTAGE); /* * Only x86 systems using ramstage stage cache currently take the same -- To view, visit https://review.coreboot.org/c/coreboot/+/31608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Gerrit-Change-Number: 31608 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/postcar: Add separate timestamp for postcar stage
by Subrata Banik (Code Review) 08 Mar '19

08 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31762 Change subject: arch/x86/postcar: Add separate timestamp for postcar stage ...................................................................... arch/x86/postcar: Add separate timestamp for postcar stage This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,404,341 (20,022,190) 4:end of romstage 20,445,466 (41,124) 1103:start of postcar 20,478,259 (32,793) 1104:end of postcar 20,489,064 (10,805) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/commonlib/include/commonlib/timestamp_serialized.h 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/31762/1 diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..c2d91be 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <timestamp.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -37,6 +38,8 @@ display_mtrrs(); + timestamp_add_now(TS_END_POSTCAR); + /* Load and run ramstage. */ run_ramstage(); } diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b08b5ea..2d99eef 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -175,5 +175,7 @@ } else load_postcar_cbfs(&prog, pcf); + timestamp_add_now(TS_START_POSTCAR); + prog_run(&prog); } diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index cbf07b5..cc088f5 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -143,6 +143,8 @@ TS_START_KERNEL = 1101, TS_KERNEL_DECOMPRESSION = 1102, + TS_START_POSTCAR = 1103, + TS_END_POSTCAR = 1104, }; static const struct timestamp_id_to_name { @@ -257,6 +259,8 @@ { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" }, { TS_FSP_AFTER_END_OF_FIRMWARE, "returning from FspNotify(EndOfFirmware)" }, + { TS_START_POSTCAR, "start of postcar" }, + { TS_END_POSTCAR, "end of postcar" }, }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Gerrit-Change-Number: 31762 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Enable PM timer emulation support
by Subrata Banik (Code Review) 08 Mar '19

08 Mar '19

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31609 to review the following change. Change subject: soc/intel/icelake: Enable PM timer emulation support ...................................................................... soc/intel/icelake: Enable PM timer emulation support TEST=Able to build and boot with alt/tianocore payload. Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/cpu.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31609/1 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 0585450..f4ebacf 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -24,6 +24,7 @@ #include <fsp/api.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> #include <intelblocks/smm.h> #include <romstage_handoff.h> #include <soc/cpu.h> @@ -118,6 +119,23 @@ } } +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable*/ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -190,6 +208,9 @@ /* Configure Intel Speed Shift */ configure_isst(); + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index 1e8d9e8..fae8500 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -35,6 +35,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/31609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Gerrit-Change-Number: 31609 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.h
by Patrick Georgi (Code Review) 08 Mar '19

08 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30322 ) Change subject: mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.h ...................................................................... mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.h Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30322 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/asus/p5qc/dsdt.asl M src/mainboard/intel/dg43gt/dsdt.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl 3 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl index d7ce26e..5ec7c19 100644 --- a/src/mainboard/asus/p5qc/dsdt.asl +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801jx/i82801jx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/intel/dg43gt/dsdt.asl b/src/mainboard/intel/dg43gt/dsdt.asl index 3052557..911dcee 100644 --- a/src/mainboard/intel/dg43gt/dsdt.asl +++ b/src/mainboard/intel/dg43gt/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801jx/i82801jx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index 200dfb5..58220f6 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -16,6 +16,8 @@ /* Intel 82801Ix support */ +#include "../i82801jx.h" + Scope(\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. -- To view, visit https://review.coreboot.org/c/coreboot/+/30322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Gerrit-Change-Number: 30322 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.h
by Patrick Georgi (Code Review) 08 Mar '19

08 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30322 ) Change subject: mb/{asus/p5qc,intel/dg43gt}: Remove unneeded include i82801jx.h ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e64c750dfa6901ac7c9e786952eed49cccfa17 Gerrit-Change-Number: 30322 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Mar 2019 17:19:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: vboot: rename VB2_DISABLE_DEVELOPER_MODE
by Joel Kitching (Code Review) 08 Mar '19

08 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31298 Change subject: vboot: rename VB2_DISABLE_DEVELOPER_MODE ...................................................................... vboot: rename VB2_DISABLE_DEVELOPER_MODE Rename VB2_DISABLE_DEVELOPER_MODE to VB2_CONTEXT_DISABLE_DEVELOPER_MODE. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460645 BRANCH=none Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31298/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 1b24160..afed5cc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -326,7 +326,7 @@ if (get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY)) - ctx.flags |= VB2_DISABLE_DEVELOPER_MODE; + ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; } if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && -- To view, visit https://review.coreboot.org/c/coreboot/+/31298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Gerrit-Change-Number: 31298 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: rename VB2_SD_DEV_MODE_ENABLED
by Joel Kitching (Code Review) 08 Mar '19

08 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31297 Change subject: vboot: rename VB2_SD_DEV_MODE_ENABLED ...................................................................... vboot: rename VB2_SD_DEV_MODE_ENABLED Rename VB2_SD_DEV_MODE_ENABLED to VB2_SD_FLAG_DEV_MODE_ENABLED. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460644 BRANCH=none Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_handoff.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/31297/1 diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 684b495..884879e 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -71,7 +71,7 @@ *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; } - if (vb2_sd->flags & VB2_SD_DEV_MODE_ENABLED) { + if (vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { *oflags |= VB_INIT_OUT_ENABLE_DEVELOPER; *oflags |= VB_INIT_OUT_CLEAR_RAM; *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; -- To view, visit https://review.coreboot.org/c/coreboot/+/31297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Gerrit-Change-Number: 31297 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src: Drop unused include <timestamp.h>
by HAOUAS Elyes (Code Review) 08 Mar '19

08 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31784 Change subject: src: Drop unused include <timestamp.h> ...................................................................... src: Drop unused include <timestamp.h> Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/lib/fit.c M src/lib/lzma.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/cheza/bootblock.c M src/mainboard/google/cheza/mainboard.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/security/vboot/vboot_handoff.c M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/nvidia/tegra210/bootblock.c M src/soc/nvidia/tegra210/romstage.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/sdm845/clock.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/qualcomm/sdm845/soc.c M src/soc/rockchip/rk3288/bootblock.c 28 files changed, 0 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31784/1 diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index ceb30fd..5532c43 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -15,7 +15,6 @@ #include <fsp/util.h> #include <memrange.h> #include <string.h> -#include <timestamp.h> #include <cbfs.h> void fsp_temp_ram_exit(void) diff --git a/src/lib/fit.c b/src/lib/fit.c index 090d34a..9184d63 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -23,7 +23,6 @@ #include <string.h> #include <cbfs.h> #include <program_loading.h> -#include <timestamp.h> #include <memrange.h> #include <fit.h> #include <boardid.h> diff --git a/src/lib/lzma.c b/src/lib/lzma.c index dbc464c..eecbb26 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -13,7 +13,6 @@ #include <console/console.h> #include <string.h> #include <lib.h> -#include <timestamp.h> #include "lzmadecode.h" diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index f5383a7..9f98c8b 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c index c72856d..ad85842 100644 --- a/src/mainboard/google/cheza/bootblock.c +++ b/src/mainboard/google/cheza/bootblock.c @@ -14,7 +14,6 @@ */ #include <bootblock_common.h> -#include <timestamp.h> #include "board.h" void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index fdec3fb..cb4f5d0 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <bootblock_common.h> #include <gpio.h> -#include <timestamp.h> static void setup_usb(void) { diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 31051ef..46e2d60 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_def.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index c9b4e91..ce902be 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f6f36118..f60f822 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index e3deddd..664da66 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -18,7 +18,6 @@ #include <arch/cbfs.h> #include <cpu/x86/mtrr.h> #include <romstage_handoff.h> -#include <timestamp.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 4074a30..6e7a8b7 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 30800e8..3440a7f 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -29,8 +29,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <superio/winbond/common/winbond.h> -#include <timestamp.h> - void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 13d9a19..da23f05 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -18,7 +18,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index d50c7cd..38ede4b 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index b88d8f5..eb40245 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 244ce7c..bbe2c73 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index c45ca7e..64ac31f 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> -#include <timestamp.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index d0e5e82..3c36833 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <romstage_handoff.h> -#include <timestamp.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 684b495..5ed5011 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -31,7 +31,6 @@ #include <console/vtxprintf.h> #include <fmap.h> #include <stdlib.h> -#include <timestamp.h> #include <vboot_struct.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index f351ea1..6e40a39 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -18,7 +18,6 @@ #include <soc/cpu.h> #include <stdint.h> #include <timer.h> -#include <timestamp.h> #define PISTACHIO_CLOCK_SWITCH 0xB8144200 #define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index cf4bffc..e147f0c 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -37,7 +37,6 @@ #include <stage_cache.h> #include <stddef.h> #include <stdint.h> -#include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> /* SOC initialization before RAM is enabled */ diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index c10920d..97ea1c9 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -26,7 +26,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <soc/pmc.h> #include <soc/power.h> -#include <timestamp.h> #define BCT_OFFSET_IN_BIT 0x4c #define ODMDATA_OFFSET_IN_BCT 0x508 diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index bce8404..213d69d 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -29,7 +29,6 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <symbols.h> #include <timer.h> -#include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> void __weak romstage_mainboard_init(void) diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index d9cb131..761b571 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <string.h> #include <timer.h> -#include <timestamp.h> #include <program_loading.h> #include <soc/iomap.h> diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index c4e5efa..bdbcfb8 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <delay.h> #include <timer.h> -#include <timestamp.h> #include <commonlib/helpers.h> #include <assert.h> diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c index 9c3782a..a2a6fb9 100644 --- a/src/soc/qualcomm/sdm845/gpio.c +++ b/src/soc/qualcomm/sdm845/gpio.c @@ -17,7 +17,6 @@ #include <types.h> #include <delay.h> #include <timer.h> -#include <timestamp.h> #include <gpio.h> diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index e4eac96..bc7235f 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -15,7 +15,6 @@ #include <symbols.h> #include <device/device.h> -#include <timestamp.h> #include <soc/mmu.h> #include <soc/symbols.h> diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 941d8a7..8988804 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -20,7 +20,6 @@ #include <soc/grf.h> #include <soc/timer.h> #include <symbols.h> -#include <timestamp.h> void bootblock_soc_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Gerrit-Change-Number: 31784 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: 3rdparty/blobs: Update submodule pointer
by Nico Huber (Code Review) 08 Mar '19

08 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31786 Change subject: 3rdparty/blobs: Update submodule pointer ...................................................................... 3rdparty/blobs: Update submodule pointer * Update SMU firmware for amd/stoneyridge * Remove stale Sandy Bridge MRC binaries Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31786/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 16058e5..ca6cfcd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc +Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 -- To view, visit https://review.coreboot.org/c/coreboot/+/31786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61 Gerrit-Change-Number: 31786 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Docs/project_ideas: Add coverity scan cleanup project
by Patrick Georgi (Code Review) 08 Mar '19

08 Mar '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31805 Change subject: Docs/project_ideas: Add coverity scan cleanup project ...................................................................... Docs/project_ideas: Add coverity scan cleanup project Change-Id: I16d9a7f7088254c5c207adc9299a8525bf38199f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31805/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index e7dd3a7..117dcce 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -152,3 +152,23 @@ ### Mentors * Patrick Georgi <patrick(a)georgi.software> + +## Make coreboot coverity clean +coreboot and several other of our projects are automatically tested +using Synopsys' free "Coverity Scan" service. While some fare pretty +good, like [em100](https://scan.coverity.com/projects/em100) at 0 known +defects, there are still many open issues in other projects, most notably +[coreboot](https://scan.coverity.com/projects/coreboot) itself (which +is also the largest codebase). + +Not all of the reports are actual issues, but the project benefits a +lot if the list of unhandled reports is down to 0 because that provides +a baseline when future changes reintroduce new issues: it's easier to +triage and handle a list of 5 issues rather than more than 350. + +This project would be going through all reports and handling them +appropriately: Figure out if reports are valid or not and mark them +as such. For valid reports, provide patches to fix the underlying issue. + +### Mentors +* Patrick Georgi <patrick(a)georgi.software> -- To view, visit https://review.coreboot.org/c/coreboot/+/31805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16d9a7f7088254c5c207adc9299a8525bf38199f Gerrit-Change-Number: 31805 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019