Hello Patrick Rudolph, Aamir Bohra, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30310
to look at the new patch set (#6).
Change subject: drivers/intel/fsp2_0: Add support for FSP minor version update
......................................................................
drivers/intel/fsp2_0: Add support for FSP minor version update
This patch adds support for FSP2.1 Kconfig which is backward compatible
with FSP2.0 specification and added below coreboot impacted features as below:
1. Remove FSP stack switch and use the same stack with bootloader
2. FSP should support external EFI_PEI_MP_SERVICES_PPI stack
Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30310/6
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524
Gerrit-Change-Number: 30310
Gerrit-PatchSet: 6
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, dhaval v sharma, Balaji Manigandan, Vincent Zimmer, Paul Menzel, build bot (Jenkins), Patrick Georgi, ron minnich, Idwer Vollering, Philipp Deppenwiese, Nico Huber, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/25634
to look at the new patch set (#52).
Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
......................................................................
drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
This patch ensures to have below listed features:
1. All required APIs to create MP service structure.
2. Function to get MP service PPI status
MP specification here:
http://github.com/tianocore/edk2/blob/master/MdePkg/Include/Ppi/MpServices.h
coreboot design document here:
../Documentation/soc/intel/icelake/MultiProcessorInit.md
Supported platform will call fill mp_services structure so that FSP can
install the required PPI based on coreboot published structure.
BRANCH=none
BUG=b:74436746
TEST=Able to publish MP service PPI in coreboot.
Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
A src/drivers/intel/fsp2_0/include/fsp/fsp_mp_service_ppi.h
A src/drivers/intel/fsp2_0/ppi/fsp_mp_service_ppi.c
4 files changed, 211 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25634/52
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956
Gerrit-Change-Number: 25634
Gerrit-PatchSet: 52
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-CC: Furquan Shaikh <furquan(a)google.com>
Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com>
Gerrit-MessageType: newpatchset
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31804
Change subject: Docs/project_ideas: Expand "toolchain" project description
......................................................................
Docs/project_ideas: Expand "toolchain" project description
One of packages do us little good, we need to be able to automate
building them.
Change-Id: Idd9b6b231435ea9d6e946c7ccaa71174b497742c
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Documentation/contributing/project_ideas.md
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31804/1
diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md
index 9a2d414..e7dd3a7 100644
--- a/Documentation/contributing/project_ideas.md
+++ b/Documentation/contributing/project_ideas.md
@@ -29,6 +29,12 @@
Windows, Mac OS. For Windows, this should also include the environment
(shell, make, ...).
+The scripts for to generate these packages should be usable on a Linux
+host, as that's what we're using for our automated build testing system
+that we could extend to provide current packages going forward. This
+might include automating some virtualization system (eg. QEMU or CrosVM) for
+non-Linux builds or docker for different Linux distributions.
+
### Requirements
* coreboot knowledge: Should know how to build coreboot images and where
the compiler comes into play in our build system.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idd9b6b231435ea9d6e946c7ccaa71174b497742c
Gerrit-Change-Number: 31804
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Hello Aaron Durbin, Patrick Georgi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31776
to review the following change.
Change subject: lint/kconfig: Update to support new CONFIG() macro
......................................................................
lint/kconfig: Update to support new CONFIG() macro
This patch updates the Kconfig linter to support the new CONFIG() macro
in the same manner that IS_ENABLED() was previously supported. It will
be flagged when it is used on non-bool Kconfigs or used with #ifdef, and
it is supported for checking used Kconfigs. Remaining uses of
IS_ENABLED() are flagged with a deprecation warning.
Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M util/lint/kconfig_lint
1 file changed, 37 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31776/1
diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint
index dc01e71..6cf05a4 100755
--- a/util/lint/kconfig_lint
+++ b/util/lint/kconfig_lint
@@ -193,7 +193,7 @@
#look for #ifdef SYMBOL
while ( my $line = shift @ifdef_symbols ) {
- if ( $line =~ /^([^:]+):(\d+):\s*#\s*ifn?def\s*\(?\s*CONFIG_(\w+)/ ) {
+ if ( $line =~ /^([^:]+):(\d+):\s*#\s*ifn?def\s*\(?\s*CONFIG(?:_|\()(\w+)/ ) {
my $file = $1;
my $lineno = $2;
my $symbol = $3;
@@ -202,7 +202,7 @@
show_warning( "#ifdef 'CONFIG_$symbol' used at $file:$lineno."
. " Symbols of type '$symbols{$symbol}{type}' are always defined." );
}
- } elsif ( $line =~ /^([^:]+):(\d+):\s*#\s*if\s+!?\s*defined\s*\(?\s*CONFIG_(\w+)/ ) {
+ } elsif ( $line =~ /^([^:]+):(\d+):\s*#\s*if\s+!?\s*defined\s*\(?\s*CONFIG(?:_|\()(\w+)/ ) {
my $file = $1;
my $lineno = $2;
my $symbol = $3;
@@ -217,7 +217,7 @@
# look for (#if) defined SYMBOL
@ifdef_symbols = @collected_symbols;
while ( my $line = shift @ifdef_symbols ) {
- if ( $line =~ /^([^:]+):(\d+):.+defined\s*\(\s*CONFIG_(\w+)/ ) {
+ if ( $line =~ /^([^:]+):(\d+):.+defined\s*\(\s*CONFIG(?:_|\()(\w+)/ ) {
my $file = $1;
my $lineno = $2;
my $symbol = $3;
@@ -308,16 +308,35 @@
}
#-------------------------------------------------------------------------------
-# check_is_enabled - The IS_ENABLED() macro is only valid for symbols of type
-# bool. It would probably work on type hex or int if the value was 0 or 1, but
-# this seems like a bad plan. Using it on strings is dead out.
+# check_is_enabled - The IS_ENABLED() and CONFIG() macros are only valid for
+# symbols of type bool. It would probably work on type hex or int if the value
+# was 0 or 1, but this seems like a bad plan. Using it on strings is dead out.
#-------------------------------------------------------------------------------
sub check_is_enabled {
my @is_enabled_symbols = @collected_symbols;
#sort through symbols found by grep and store them in a hash for easy access
while ( my $line = shift @is_enabled_symbols ) {
- if ( $line =~ /^([^:]+):(\d+):(.+IS_ENABLED.*)/ ) {
+ if ( $line =~ /^([^:]+):(\d+):(.+\bCONFIG\(.*)/ ) {
+ my $file = $1;
+ my $lineno = $2;
+ $line = $3;
+ while ( $line =~ /(.*)\bCONFIG\(([^)]*)\)(.*)/ ) {
+ my $symbol = $2;
+ $line = $1 . $3;
+
+ #make sure that the type is bool
+ if ( exists $symbols{$symbol} ) {
+ if ( $symbols{$symbol}{type} ne "bool" ) {
+ show_error( "CONFIG($symbol) used at $file:$lineno."
+ . " CONFIG() is only valid for type 'bool', not '$symbols{$symbol}{type}'." );
+ }
+ }
+ else {
+ show_warning("CONFIG() used on unknown value ($symbol) at $file:$lineno.");
+ }
+ }
+ } elsif ( $line =~ /^([^:]+):(\d+):(.+IS_ENABLED.*)/ ) {
my $file = $1;
my $lineno = $2;
$line = $3;
@@ -334,6 +353,8 @@
if ( $symbols{$symbol}{type} ne "bool" ) {
show_error( "IS_ENABLED(CONFIG_$symbol) used at $file:$lineno."
. " IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'." );
+ } else {
+ show_warning("IS_ENABLED(CONFIG_$symbol) at $file:$lineno is deprecated. Use CONFIG($symbol) instead." );
}
}
else {
@@ -348,10 +369,10 @@
if ( exists $symbols{$symbol} ) {
if ( $symbols{$symbol}{type} eq "bool" ) {
show_error( "#if CONFIG_$symbol used at $file:$lineno."
- . " IS_ENABLED should be used for type 'bool'" );
+ . " CONFIG($symbol) should be used for type 'bool'" );
}
}
- } elsif ( $line =~ /^([^:]+):(\d+):\s*#\s*(?:el)?if.*(?:&&|\|\|)\s+!?\s*\(?\s*CONFIG_(\w+)\)?(\s*==\s*1)?$/ ) {
+ } elsif ( $line =~ /^([^:]+):(\d+):\s*#\s*(?:el)?if.*(?:&&|\|\|)\s+!?\s*\(?\s*CONFIG_(\w+)\)?(\s*==\s*1)?$/ ) {
my $file = $1;
my $lineno = $2;
my $symbol = $3;
@@ -359,7 +380,7 @@
if ( exists $symbols{$symbol} ) {
if ( $symbols{$symbol}{type} eq "bool" ) {
show_error( "#if CONFIG_$symbol used at $file:$lineno."
- . " IS_ENABLED should be used for type 'bool'" );
+ . " CONFIG($symbol) should be used for type 'bool'" );
}
}
}
@@ -471,17 +492,17 @@
# find all references to CONFIG_ statements in the tree
if ($dont_use_git_grep) {
- @collected_symbols = `grep -Irn -- "CONFIG_" | grep -v '$exclude_dirs_and_files'; grep -In -- "CONFIG_" $payload_files_to_check`;
+ @collected_symbols = `grep -Irn -- "CONFIG\\(_\\|(\\)" | grep -v '$exclude_dirs_and_files'; grep -In -- "CONFIG\\(_\\|(\\)" $payload_files_to_check`;
}
else {
- @collected_symbols = `git grep -In -- "CONFIG_" | grep -v '$exclude_dirs_and_files'; git grep -In -- "CONFIG_" $payload_files_to_check`;
+ @collected_symbols = `git grep -In -- "CONFIG\\(_\\|(\\)" | grep -v '$exclude_dirs_and_files'; git grep -In -- "CONFIG\\(_\\|(\\)" $payload_files_to_check`;
}
my @used_symbols = @collected_symbols;
#sort through symbols found by grep and store them in a hash for easy access
while ( my $line = shift @used_symbols ) {
- while ( $line =~ /[^A-Za-z0-9_]CONFIG_([A-Za-z0-9_]+)/g ) {
+ while ( $line =~ /[^A-Za-z0-9_]CONFIG(?:_|\()([A-Za-z0-9_]+)/g ) {
my $symbol = $1;
my $filename = "";
if ( $line =~ /^([^:]+):/ ) {
@@ -684,9 +705,9 @@
# visible if <expr>
elsif ( $line =~ /^\s*visible if.*$/ ) {
- # Must come directly after menu line (and on a separate line)
- # but kconfig already checks for that.
- # Ignore it.
+ # Must come directly after menu line (and on a separate line)
+ # but kconfig already checks for that.
+ # Ignore it.
}
# endmenu
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f
Gerrit-Change-Number: 31776
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Hello Aaron Durbin, Patrick Georgi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31774
to review the following change.
Change subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
......................................................................
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/include/arch/memlayout.h
M src/arch/arm/include/armv7/arch/cache.h
M src/arch/arm/tables.c
M src/arch/arm64/arm_tf.c
M src/arch/arm64/armv8/exception.c
M src/arch/arm64/boot.c
M src/arch/arm64/include/armv8/arch/barrier.h
M src/arch/arm64/tables.c
M src/arch/mips/bootblock_simple.c
M src/arch/ppc64/include/arch/cpu.h
M src/arch/riscv/include/arch/cpu.h
M src/arch/riscv/sbi.c
M src/arch/x86/acpi.c
M src/arch/x86/acpi_device.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/assembly_entry.S
M src/arch/x86/bootblock.ld
M src/arch/x86/bootblock_crt0.S
M src/arch/x86/bootblock_romcc.S
M src/arch/x86/bootblock_simple.c
M src/arch/x86/c_start.S
M src/arch/x86/car.ld
M src/arch/x86/cbmem.c
M src/arch/x86/cpu.c
M src/arch/x86/exception.c
M src/arch/x86/exit_car.S
M src/arch/x86/gdt.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/include/arch/exception.h
M src/arch/x86/include/arch/interrupt.h
M src/arch/x86/include/arch/pci_io_cfg.h
M src/arch/x86/include/arch/registers.h
M src/arch/x86/include/arch/smp/spinlock.h
M src/arch/x86/include/cf9_reset.h
M src/arch/x86/ioapic.c
M src/arch/x86/memlayout.ld
M src/arch/x86/pci_ops_conf1.c
M src/arch/x86/pirq_routing.c
M src/arch/x86/postcar_loader.c
M src/arch/x86/smbios.c
M src/arch/x86/tables.c
M src/arch/x86/timestamp.c
M src/commonlib/cbfs.c
M src/commonlib/include/commonlib/stdlib.h
M src/commonlib/storage/mmc.c
M src/commonlib/storage/sd_mmc.c
M src/commonlib/storage/sd_mmc.h
M src/commonlib/storage/sdhci.c
M src/commonlib/storage/sdhci_display.c
M src/commonlib/storage/storage.c
M src/console/console.c
M src/console/init.c
M src/console/post.c
M src/console/printk.c
M src/console/vtxprintf.c
M src/cpu/amd/agesa/family12/model_12_init.c
M src/cpu/amd/agesa/family14/model_14_init.c
M src/cpu/amd/agesa/family15tn/model_15_init.c
M src/cpu/amd/agesa/family16kb/model_16_init.c
M src/cpu/amd/car/cache_as_ram.inc
M src/cpu/amd/car/disable_cache_as_ram.c
M src/cpu/amd/car/post_cache_as_ram.c
M src/cpu/amd/family_10h-family_15h/fidvid.c
M src/cpu/amd/family_10h-family_15h/init_cpus.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/family_10h-family_15h/powernow_acpi.c
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/microcode/microcode.c
M src/cpu/amd/pi/00630F01/fixme.c
M src/cpu/amd/pi/00630F01/model_15_init.c
M src/cpu/amd/pi/00660F01/fixme.c
M src/cpu/amd/pi/00660F01/model_15_init.c
M src/cpu/amd/pi/00730F01/fixme.c
M src/cpu/amd/pi/00730F01/model_16_init.c
M src/cpu/amd/quadcore/quadcore.c
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/common/common_init.c
M src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/intel/haswell/bootblock.c
M src/cpu/intel/haswell/romstage.c
M src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_2065x/bootblock.c
M src/cpu/intel/model_206ax/bootblock.c
M src/cpu/intel/model_f3x/model_f3x_init.c
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/cpu/intel/turbo/turbo.c
M src/cpu/x86/16bit/entry16.inc
M src/cpu/x86/32bit/entry32.inc
M src/cpu/x86/backup_default_smm.c
M src/cpu/x86/car.c
M src/cpu/x86/lapic/apic_timer.c
M src/cpu/x86/lapic/boot_cpu.c
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/cpu/x86/mp_init.c
M src/cpu/x86/mtrr/debug.c
M src/cpu/x86/mtrr/mtrr.c
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smihandler.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/cpu/x86/smm/smmhandler.S
M src/cpu/x86/smm/smmrelocate.S
M src/cpu/x86/tsc/delay_tsc.c
M src/device/device.c
M src/device/device_const.c
M src/device/oprom/include/io.h
M src/device/oprom/include/x86emu/fpu_regs.h
M src/device/oprom/include/x86emu/regs.h
M src/device/oprom/include/x86emu/x86emu.h
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/biosemu.c
M src/device/oprom/yabel/compat/functions.c
M src/device/oprom/yabel/debug.h
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/device.h
M src/device/oprom/yabel/interrupt.c
M src/device/oprom/yabel/io.c
M src/device/oprom/yabel/mem.c
M src/device/oprom/yabel/vbe.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/root_device.c
M src/drivers/amd/agesa/acpi_tables.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/amd/agesa/def_callouts.c
M src/drivers/amd/agesa/eventlog.c
M src/drivers/amd/agesa/heapmanager.c
M src/drivers/amd/agesa/oem_s3.c
M src/drivers/amd/agesa/romstage.c
M src/drivers/amd/agesa/state_machine.c
M src/drivers/elog/boot_count.c
M src/drivers/elog/elog.c
M src/drivers/emulation/qemu/bochs.c
M src/drivers/emulation/qemu/cirrus.c
M src/drivers/generic/adau7002/adau7002.c
M src/drivers/generic/generic/chip.h
M src/drivers/generic/max98357a/max98357a.c
M src/drivers/i2c/da7219/da7219.c
M src/drivers/i2c/designware/dw_i2c.c
M src/drivers/i2c/designware/dw_i2c.h
M src/drivers/i2c/generic/generic.c
M src/drivers/i2c/hid/hid.c
M src/drivers/i2c/nau8825/nau8825.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/i2c/w83795/w83795.c
M src/drivers/intel/fsp1_0/cache_as_ram.inc
M src/drivers/intel/fsp1_0/fastboot_cache.c
M src/drivers/intel/fsp1_0/fsp_util.c
M src/drivers/intel/fsp1_0/fsp_util.h
M src/drivers/intel/fsp1_1/after_raminit.S
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp1_1/stack.c
M src/drivers/intel/fsp1_1/vbt.c
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/intel/gma/int15.h
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/vbt.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/lenovo/wacom.c
M src/drivers/mrc_cache/mrc_cache.c
M src/drivers/net/r8168.c
M src/drivers/pc80/pc/i8254.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/pc80/rtc/mc146818rtc_boot.c
M src/drivers/pc80/rtc/mc146818rtc_romcc.c
M src/drivers/pc80/tpm/tis.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/smmstore/store.c
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi_flash.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/drivers/tpm/tpm.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/drivers/uart/util.c
M src/drivers/usb/ehci_debug.c
M src/drivers/usb/gadget.c
M src/drivers/xgi/common/vb_init.c
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/ec/google/chromeec/acpi/ec.asl
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec_i2c.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/switches.c
M src/ec/google/wilco/acpi/superio.asl
M src/ec/google/wilco/bootblock.c
M src/ec/kontron/kempld/early_kempld.c
M src/ec/lenovo/h8/h8.c
M src/ec/lenovo/h8/panic.c
M src/ec/quanta/ene_kb3940q/ec.c
M src/include/adainit.h
M src/include/assert.h
M src/include/bootstate.h
M src/include/cbmem.h
M src/include/console/cbmem_console.h
M src/include/console/console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/include/cper.h
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/msr.h
M src/include/cpu/x86/post_code.h
M src/include/cpu/x86/smm.h
M src/include/cpu/x86/tsc.h
M src/include/device/device.h
M src/include/device/dram/common.h
M src/include/device/dram/ddr3.h
M src/include/device/early_smbus.h
M src/include/device/pci.h
M src/include/device/pci_ehci.h
M src/include/device/pci_mmio_cfg.h
M src/include/device/smbus.h
M src/include/elog.h
M src/include/gic.h
M src/include/memlayout.h
M src/include/option.h
M src/include/pc80/mc146818rtc.h
M src/include/reg_script.h
M src/include/rmodule.h
M src/include/rules.h
M src/include/smp/atomic.h
M src/include/smp/node.h
M src/include/smp/spinlock.h
M src/include/stddef.h
M src/include/thread.h
M src/include/timer.h
M src/include/timestamp.h
M src/include/trace.h
M src/include/watchdog.h
M src/lib/bootblock.c
M src/lib/bootmode.c
M src/lib/cbfs.c
M src/lib/cbmem_console.c
M src/lib/coreboot_table.c
M src/lib/decompressor.c
M src/lib/edid.c
M src/lib/fallback_boot.c
M src/lib/gcov-glue.c
M src/lib/hardwaremain.c
M src/lib/imd_cbmem.c
M src/lib/libgcc.c
M src/lib/malloc.c
M src/lib/prog_loaders.c
M src/lib/program.ld
M src/lib/ramtest.c
M src/lib/reg_script.c
M src/lib/reset.c
M src/lib/spd_bin.c
M src/lib/timestamp.c
M src/mainboard/advansus/a785e-i/get_bus_conf.c
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bettong/BiosCallOuts.c
M src/mainboard/amd/bettong/romstage.c
M src/mainboard/amd/bimini_fam10/get_bus_conf.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
M src/mainboard/amd/lamar/BiosCallOuts.c
M src/mainboard/amd/lamar/OemCustomize.c
M src/mainboard/amd/mahogany_fam10/get_bus_conf.c
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/amd/olivehill/BiosCallOuts.c
M src/mainboard/amd/olivehill/OemCustomize.c
M src/mainboard/amd/olivehillplus/BiosCallOuts.c
M src/mainboard/amd/parmer/BiosCallOuts.c
M src/mainboard/amd/parmer/OemCustomize.c
M src/mainboard/amd/parmer/buildOpts.c
M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
M src/mainboard/amd/thatcher/BiosCallOuts.c
M src/mainboard/amd/thatcher/buildOpts.c
M src/mainboard/amd/tilapia_fam10/get_bus_conf.c
M src/mainboard/amd/tilapia_fam10/romstage.c
M src/mainboard/amd/torpedo/Oem.h
M src/mainboard/amd/torpedo/platform_cfg.h
M src/mainboard/apple/macbook21/gpio.c
M src/mainboard/apple/macbook21/hda_verb.c
M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asrock/imb-a180/OemCustomize.c
M src/mainboard/asus/am1i-a/BiosCallOuts.c
M src/mainboard/asus/am1i-a/OemCustomize.c
M src/mainboard/asus/f2a85-m/BiosCallOuts.c
M src/mainboard/asus/f2a85-m/OemCustomize.c
M src/mainboard/asus/f2a85-m/acpi/routing.asl
M src/mainboard/asus/f2a85-m/buildOpts.c
M src/mainboard/asus/f2a85-m/romstage.c
M src/mainboard/asus/kcma-d8/acpi_tables.c
M src/mainboard/asus/kcma-d8/bootblock.c
M src/mainboard/asus/kcma-d8/mptable.c
M src/mainboard/asus/kcma-d8/romstage.c
M src/mainboard/asus/kfsn4-dre/acpi_tables.c
M src/mainboard/asus/kfsn4-dre/bootblock.c
M src/mainboard/asus/kfsn4-dre/get_bus_conf.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kgpe-d16/acpi_tables.c
M src/mainboard/asus/kgpe-d16/bootblock.c
M src/mainboard/asus/kgpe-d16/mptable.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/asus/m4a78-em/get_bus_conf.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/get_bus_conf.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/get_bus_conf.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/asus/p5qpl-am/romstage.c
M src/mainboard/avalue/eax-785e/get_bus_conf.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/bap/ode_e20XX/BiosCallOuts.c
M src/mainboard/bap/ode_e20XX/OemCustomize.c
M src/mainboard/bap/ode_e21XX/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/BiosCallOuts.c
M src/mainboard/biostar/a68n_5200/OemCustomize.c
M src/mainboard/biostar/a68n_5200/romstage.c
M src/mainboard/biostar/am1ml/BiosCallOuts.c
M src/mainboard/biostar/am1ml/OemCustomize.c
M src/mainboard/cavium/cn8100_sff_evb/bootblock.c
M src/mainboard/compulab/intense_pc/gpio.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/emulation/qemu-power8/bootblock.c
M src/mainboard/foxconn/g41s-k/acpi/superio.asl
M src/mainboard/foxconn/g41s-k/hda_verb.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/gigabyte/ma785gm/get_bus_conf.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/gigabyte/ma78gm/get_bus_conf.c
M src/mainboard/gigabyte/ma78gm/romstage.c
M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo2/OemCustomize.c
M src/mainboard/google/auron/acpi/mainboard.asl
M src/mainboard/google/auron/smihandler.c
M src/mainboard/google/auron/variants/buddy/variant.c
M src/mainboard/google/beltino/acpi_tables.c
M src/mainboard/google/beltino/lan.c
M src/mainboard/google/butterfly/mainboard.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/cyan/acpi/dptf.asl
M src/mainboard/google/cyan/acpi_tables.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/cyan/dsdt.asl
M src/mainboard/google/cyan/ec.c
M src/mainboard/google/cyan/romstage.c
M src/mainboard/google/cyan/smihandler.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/google/dragonegg/dsdt.asl
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/mainboard.c
M src/mainboard/google/gale/verstage.c
M src/mainboard/google/glados/mainboard.c
M src/mainboard/google/glados/romstage.c
M src/mainboard/google/glados/smihandler.c
M src/mainboard/google/gru/board.h
M src/mainboard/google/gru/boardid.c
M src/mainboard/google/gru/bootblock.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/gru/mainboard.c
M src/mainboard/google/gru/pwm_regulator.c
M src/mainboard/google/gru/romstage.c
M src/mainboard/google/gru/sdram_configs.c
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/jecht/lan.c
M src/mainboard/google/jecht/led.c
M src/mainboard/google/jecht/romstage.c
M src/mainboard/google/jecht/smihandler.c
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/smihandler.c
M src/mainboard/google/kahlee/variants/baseboard/mainboard.c
M src/mainboard/google/kukui/boardid.c
M src/mainboard/google/kukui/romstage.c
M src/mainboard/google/link/acpi_tables.c
M src/mainboard/google/link/mainboard.c
M src/mainboard/google/link/mainboard_smi.c
M src/mainboard/google/nyan/romstage.c
M src/mainboard/google/nyan_big/romstage.c
M src/mainboard/google/nyan_blaze/romstage.c
M src/mainboard/google/oak/bootblock.c
M src/mainboard/google/oak/gpio.h
M src/mainboard/google/oak/mainboard.c
M src/mainboard/google/octopus/romstage.c
M src/mainboard/google/octopus/variants/baseboard/memory.c
M src/mainboard/google/octopus/variants/baseboard/nhlt.c
M src/mainboard/google/parrot/acpi_tables.c
M src/mainboard/google/parrot/smihandler.c
M src/mainboard/google/poppy/dsdt.asl
M src/mainboard/google/rambi/mainboard.c
M src/mainboard/google/rambi/mainboard_smi.c
M src/mainboard/google/rambi/variants/ninja/lan.c
M src/mainboard/google/rambi/variants/sumo/lan.c
M src/mainboard/google/reef/smihandler.c
M src/mainboard/google/reef/variants/baseboard/nhlt.c
M src/mainboard/google/reef/variants/snappy/mainboard.c
M src/mainboard/google/sarien/dsdt.asl
M src/mainboard/google/sarien/variants/sarien/ramstage.c
M src/mainboard/google/slippy/acpi_tables.c
M src/mainboard/google/slippy/smihandler.c
M src/mainboard/google/smaug/mainboard.c
M src/mainboard/google/storm/mainboard.c
M src/mainboard/google/stout/acpi_tables.c
M src/mainboard/google/stout/ec.c
M src/mainboard/google/urara/mainboard.c
M src/mainboard/google/veyron/boardid.c
M src/mainboard/google/veyron/bootblock.c
M src/mainboard/google/veyron_mickey/bootblock.c
M src/mainboard/google/veyron_rialto/bootblock.c
M src/mainboard/hp/abm/OemCustomize.c
M src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/dl165_g6_fam10/mptable.c
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
M src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/intel/apollolake_rvp/romstage.c
M src/mainboard/intel/baskingridge/acpi_tables.c
M src/mainboard/intel/bayleybay_fsp/mainboard.c
M src/mainboard/intel/bayleybay_fsp/romstage.c
M src/mainboard/intel/camelbackmountain_fsp/mainboard.c
M src/mainboard/intel/cannonlake_rvp/dsdt.asl
M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/coffeelake_rvp/dsdt.asl
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
M src/mainboard/intel/dcp847ske/acpi/superio.asl
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/galileo/gpio.c
M src/mainboard/intel/galileo/mainboard.c
M src/mainboard/intel/galileo/vboot.c
M src/mainboard/intel/glkrvp/boardid.c
M src/mainboard/intel/glkrvp/ec.c
M src/mainboard/intel/glkrvp/romstage.c
M src/mainboard/intel/glkrvp/smihandler.c
M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
M src/mainboard/intel/harcuvar/romstage.c
M src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
M src/mainboard/intel/icelake_rvp/board_id.c
M src/mainboard/intel/icelake_rvp/dsdt.asl
M src/mainboard/intel/kblrvp/acpi/ec.asl
M src/mainboard/intel/kblrvp/acpi/mainboard.asl
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kblrvp/dsdt.asl
M src/mainboard/intel/kblrvp/hda_verb.c
M src/mainboard/intel/kblrvp/mainboard.c
M src/mainboard/intel/kblrvp/ramstage.c
M src/mainboard/intel/kblrvp/romstage.c
M src/mainboard/intel/kblrvp/smihandler.c
M src/mainboard/intel/kunimitsu/smihandler.c
M src/mainboard/intel/strago/ec.c
M src/mainboard/intel/strago/smihandler.c
M src/mainboard/jetway/pa78vm5/get_bus_conf.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/mainboard/kontron/ktqm77/mainboard.c
M src/mainboard/lenovo/g505s/BiosCallOuts.c
M src/mainboard/lenovo/g505s/OemCustomize.c
M src/mainboard/lenovo/g505s/buildOpts.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/msi/ms7721/BiosCallOuts.c
M src/mainboard/msi/ms7721/OemCustomize.c
M src/mainboard/msi/ms7721/buildOpts.c
M src/mainboard/msi/ms7721/romstage.c
M src/mainboard/msi/ms9652_fam10/get_bus_conf.c
M src/mainboard/msi/ms9652_fam10/romstage.c
M src/mainboard/ocp/monolake/mainboard.c
M src/mainboard/ocp/wedge100s/mainboard.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/mainboard/opencellular/elgon/bootblock.c
M src/mainboard/pcengines/apu2/BiosCallOuts.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/acpi_tables.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/scaleway/tagada/bootblock.c
M src/mainboard/siemens/mc_bdx1/mainboard.c
M src/mainboard/siemens/mc_tcu3/mainboard.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/supermicro/h8scm_fam10/romstage.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
M src/mainboard/tyan/s2912_fam10/romstage.c
M src/mainboard/via/epia-m850/mainboard.c
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/agesa/family16kb/state_machine.c
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/amd/amdfam10/debug.c
M src/northbridge/amd/amdfam10/debug.h
M src/northbridge/amd/amdfam10/early_ht.c
M src/northbridge/amd/amdfam10/link_control.c
M src/northbridge/amd/amdfam10/misc_control.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/amd/amdfam10/raminit_amdmct.c
M src/northbridge/amd/amdht/h3finit.c
M src/northbridge/amd/amdht/ht_wrapper.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/amd/amdmct/wrappers/mcti.h
M src/northbridge/amd/amdmct/wrappers/mcti_d.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/agesawrapper.c
M src/northbridge/amd/pi/agesawrapper.h
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
M src/northbridge/intel/nehalem/acpi/nehalem.asl
M src/northbridge/intel/nehalem/early_init.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/gma.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/via/vx900/lpc.c
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/vboot/bootmode.c
M src/security/vboot/common.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vbnv.c
M src/security/vboot/vbnv_cmos.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_common.h
M src/security/vboot/vboot_crtm.c
M src/security/vboot/vboot_crtm.h
M src/security/vboot/vboot_handoff.c
M src/security/vboot/vboot_loader.c
M src/security/vboot/vboot_logic.c
M src/security/vboot/verstage.c
M src/soc/amd/common/block/pi/refcode_loader.c
M src/soc/amd/common/block/psp/psp.c
M src/soc/amd/stoneyridge/BiosCallOuts.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/acpi/sleepstates.asl
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/amd/stoneyridge/finalize.c
M src/soc/amd/stoneyridge/include/soc/acpi.h
M src/soc/amd/stoneyridge/include/soc/iomap.h
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/amd/stoneyridge/smihandler.c
M src/soc/amd/stoneyridge/southbridge.c
M src/soc/amd/stoneyridge/spi.c
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/bootblock.c
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/apollolake/acpi/pci_irqs.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/acpi/xhci.asl
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/cse.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/apollolake/include/soc/gpio.h
M src/soc/intel/apollolake/include/soc/pcr_ids.h
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/meminit.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/apollolake/uart.c
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/include/soc/pmc.h
M src/soc/intel/baytrail/include/soc/ramstage.h
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/include/soc/pm.h
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/include/soc/ramstage.h
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/power_state.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/cannonlake/acpi/scs.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/cpu.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/cnl_memcfg_init.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/include/soc/gpio.h
M src/soc/intel/cannonlake/include/soc/pmc.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/acpi/acpi_debug.asl
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/exit_car.S
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pcr/pcr.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/rtc/rtc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/smm/smm.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/common/vbt.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/hob_mem.c
M src/soc/intel/denverton_ns/include/soc/pmc.h
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_baytrail/acpi/sleepstates.asl
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_baytrail/gpio.c
M src/soc/intel/fsp_baytrail/include/soc/pmc.h
M src/soc/intel/fsp_baytrail/include/soc/romstage.h
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/smihandler.c
M src/soc/intel/fsp_baytrail/southcluster.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/chip.c
M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/southcluster.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/icelake/bootblock/bootblock.c
M src/soc/intel/icelake/bootblock/cpu.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/icelake/graphics.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/lpc.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/quark/bootblock/bootblock.c
M src/soc/intel/quark/bootblock/esram_init.S
M src/soc/intel/quark/i2c.c
M src/soc/intel/quark/romstage/car.c
M src/soc/intel/quark/romstage/car_stage_entry.S
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/storage_test.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/acpi/gpio.asl
M src/soc/intel/skylake/acpi/pch.asl
M src/soc/intel/skylake/acpi/scs.asl
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/include/soc/gpio_defs.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/vr_config.h
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/car_stage.S
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smihandler.c
M src/soc/intel/skylake/vr_config.c
M src/soc/mediatek/mt8173/i2c.c
M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8173/memory.c
M src/soc/mediatek/mt8173/mt6391.c
M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8183/memory.c
M src/soc/nvidia/tegra210/ccplex.c
M src/soc/nvidia/tegra210/include/soc/console_uart.h
M src/soc/nvidia/tegra210/include/soc/mtc.h
M src/soc/nvidia/tegra210/romstage.c
M src/soc/nvidia/tegra210/soc.c
M src/soc/qualcomm/ipq40xx/uart.c
M src/soc/rockchip/common/gpio.c
M src/soc/rockchip/common/pwm.c
M src/soc/rockchip/rk3399/clock.c
M src/soc/rockchip/rk3399/soc.c
M src/southbridge/amd/agesa/hudson/acpi/fch.asl
M src/southbridge/amd/agesa/hudson/acpi/usb.asl
M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
M src/southbridge/amd/agesa/hudson/fadt.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/imc.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci_devs.h
M src/southbridge/amd/agesa/hudson/resume.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/amd8111/acpi.c
M src/southbridge/amd/amd8111/acpi/sleepstates.asl
M src/southbridge/amd/amd8111/lpc.c
M src/southbridge/amd/cimx/sb800/SBPLATFORM.h
M src/southbridge/amd/cimx/sb800/bootblock.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/cimx/sb900/late.c
M src/southbridge/amd/common/acpi/sleepstates.asl
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/acpi/usb.asl
M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
M src/southbridge/amd/pi/hudson/amd_pci_int_types.h
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/amd/pi/hudson/gpio.h
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/hudson.h
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci_devs.h
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/rs780/cmn.c
M src/southbridge/amd/rs780/early_setup.c
M src/southbridge/amd/rs780/gfx.c
M src/southbridge/amd/rs780/rs780.c
M src/southbridge/amd/sb700/bootblock.c
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/amd/sb700/fadt.c
M src/southbridge/amd/sb700/lpc.c
M src/southbridge/amd/sb700/sata.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sm.c
M src/southbridge/amd/sb700/usb.c
M src/southbridge/amd/sb800/fadt.c
M src/southbridge/amd/sb800/lpc.c
M src/southbridge/amd/sr5650/early_setup.c
M src/southbridge/amd/sr5650/ht.c
M src/southbridge/amd/sr5650/sr5650.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/common/pmutil.h
M src/southbridge/intel/common/rtc.c
M src/southbridge/intel/common/smbus.c
M src/southbridge/intel/common/smi.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/usb_debug.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/acpi/sleepstates.asl
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/i82801ix.h
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/acpi/sleepstates.asl
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/lynxpoint/acpi/pch.asl
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/smi.c
M src/southbridge/intel/lynxpoint/smihandler.c
M src/southbridge/nvidia/ck804/early_setup_car.c
M src/southbridge/nvidia/ck804/ht.c
M src/southbridge/nvidia/ck804/lpc.c
M src/southbridge/nvidia/mcp55/azalia.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/ht.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/nvidia/mcp55/smbus.c
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
M src/superio/ite/it8716f/superio.c
M src/superio/nuvoton/common/early_serial.c
M src/superio/nuvoton/npcd378/superio.c
M src/superio/via/vt1211/superio.c
M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
M src/vendorcode/cavium/bdk/libdram/libdram.c
M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-warn.h
M src/vendorcode/google/chromeos/acpi.c
M src/vendorcode/google/chromeos/acpi/chromeos.asl
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/elog.c
M src/vendorcode/google/chromeos/ramoops.c
M src/vendorcode/google/chromeos/sar.c
M src/vendorcode/google/chromeos/tpm2.c
918 files changed, 2,278 insertions(+), 2,278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31774/1
--
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Gerrit-Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Gerrit-Change-Number: 31774
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
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Gerrit-MessageType: newchange
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31771
Change subject: Documentation: Our coding style now allows 80 + 2*8 columns in a line
......................................................................
Documentation: Our coding style now allows 80 + 2*8 columns in a line
Update the document to match clang-format and checkpatch formally, and
provide a rationale.
Change-Id: I597a27d4e22d07e033b36f0dceb554ac1d8d5789
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M Documentation/coding_style.md
1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31771/1
diff --git a/Documentation/coding_style.md b/Documentation/coding_style.md
index 048b8e6..14e32ce 100644
--- a/Documentation/coding_style.md
+++ b/Documentation/coding_style.md
@@ -29,6 +29,10 @@
80-character terminal screen. The answer to that is that if you need
more than 3 levels of indentation, you're screwed anyway, and should
fix your program.
+Since most code in a file is indented at least 1 level, we account for
+2 levels in addition to the 80 characters on the terminal under the
+assumption that editors can scroll to the right, making an 80 characters
+screen visible with little loss on the left end.
In short, 8-char indents make things easier to read, and have the added
benefit of warning you when you're nesting your functions too deep.
@@ -80,11 +84,11 @@
Coding style is all about readability and maintainability using commonly
available tools.
-The limit on the length of lines is 80 columns and this is a strongly
-preferred limit.
+The limit on the length of lines is 96 columns (80 columns + 2 tab levels)
+and this is a strongly preferred limit.
-Statements longer than 80 columns will be broken into sensible chunks,
-unless exceeding 80 columns significantly increases readability and does
+Statements longer than 96 columns will be broken into sensible chunks,
+unless exceeding 96 columns significantly increases readability and does
not hide information. Descendants are always substantially shorter than
the parent and are placed substantially to the right. The same applies
to function headers with a long argument list. However, never break
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Gerrit-Change-Id: I597a27d4e22d07e033b36f0dceb554ac1d8d5789
Gerrit-Change-Number: 31771
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Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 )
Change subject: soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs
......................................................................
Patch Set 51:
(1 comment)
https://review.coreboot.org/#/c/25634/51/src/soc/intel/common/block/cpu/mp_…
File src/soc/intel/common/block/cpu/mp_service_ppi.c:
https://review.coreboot.org/#/c/25634/51/src/soc/intel/common/block/cpu/mp_…
PS51, Line 65: /* TODO: Fill EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer */
> ? Can we implement it here or remove the TODO?
Philipp, We can implement this but i don't see much use case of that implementation in FSP either while driving MP initialization, hence in my opinion we can keep this as TODO for now as well.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 )
Change subject: security/tpm: Fix TCPA log feature
......................................................................
Patch Set 67:
Guys, there were still tons of overlong lines in this patch. I've asked some 10+ times to clean them up without response. Can we please adhere to the coreboot code style and not ignore our own linter?!
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Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Gerrit-Change-Number: 29563
Gerrit-PatchSet: 67
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Gerrit-Comment-Date: Fri, 08 Mar 2019 01:22:29 +0000
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Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31795
Change subject: mb/google/hatch: Create hatch_whl variant
......................................................................
mb/google/hatch: Create hatch_whl variant
In preparation for the transition of hatch from WHL to CML, we are
creating a checkpoint called hatch_whl that we can use for creating
firmware compatible with the WHL hatch variant.
BUG=b:127310803
BRANCH=NONE
TEST=NONE
Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
A src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl
A src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h
A src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h
3 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/31795/1
diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..31f72b3
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h
new file mode 100644
index 0000000..c36f957
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h
new file mode 100644
index 0000000..5d69eed
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch_whl/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
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Gerrit-Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d
Gerrit-Change-Number: 31795
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen(a)google.com>
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