Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 )
Change subject: soc/intel/common: Implement EFI_MP_SERVICES_PPI structure APIs
......................................................................
Patch Set 51:
(2 comments)
https://review.coreboot.org/#/c/25634/51/src/soc/intel/common/block/cpu/Mak…
File src/soc/intel/common/block/cpu/Makefile.inc:
https://review.coreboot.org/#/c/25634/51/src/soc/intel/common/block/cpu/Mak…
PS51, Line 13: ramstage-$(CONFIG_SOC_INTEL_USES_MP_SERVICES_PPI) += mp_service_ppi.c
This is FSP specific right?. So it should be implemented somewhere generalized in the fsp driver. Maybe drivers/intel/fsp2_0/ppi?
https://review.coreboot.org/#/c/25634/51/src/soc/intel/common/block/cpu/mp_…
File src/soc/intel/common/block/cpu/mp_service_ppi.c:
https://review.coreboot.org/#/c/25634/51/src/soc/intel/common/block/cpu/mp_…
PS51, Line 65: /* TODO: Fill EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer */
? Can we implement it here or remove the TODO?
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31767 )
Change subject: soc/qualcomm/qcs405: Support for new SoC
......................................................................
Patch Set 1: Code-Review+2
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V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31787
Change subject: soc/intel/cannonlake: Move power_state functions to pmutil.c
......................................................................
soc/intel/cannonlake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938
BRANCH=none
TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36
Signed-off-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/cannonlake/romstage/Makefile.inc
D src/soc/intel/cannonlake/romstage/power_state.c
3 files changed, 64 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31787/1
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 7d6ee65..4e1500f 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -198,3 +198,67 @@
{
return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
}
+
+static inline int deep_s3_enabled(void)
+{
+ uint32_t deep_s3_pol;
+
+ deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
+ return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
+}
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+int soc_prev_sleep_state(const struct chipset_power_state *ps,
+ int prev_sleep_state)
+{
+
+ /*
+ * Check for any power failure to determine if this a wake from
+ * S5 because the PCH does not set the WAK_STS bit when waking
+ * from a true G3 state.
+ */
+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = ACPI_S5;
+
+ /*
+ * If waking from S3 determine if deep S3 is enabled. If not,
+ * need to check both deep sleep well and normal suspend well.
+ * Otherwise just check deep sleep well.
+ */
+ if (prev_sleep_state == ACPI_S3) {
+ /* PWR_FLR represents deep sleep power well loss. */
+ uint32_t mask = PWR_FLR;
+
+ /* If deep s3 isn't enabled check the suspend well too. */
+ if (!deep_s3_enabled())
+ mask |= SUS_PWR_FLR;
+
+ if (ps->gen_pmcon_b & mask)
+ prev_sleep_state = ACPI_S5;
+ }
+
+ return prev_sleep_state;
+}
+
+void soc_fill_power_state(struct chipset_power_state *ps)
+{
+ uint8_t *pmc;
+
+ ps->tco1_sts = tco_read_reg(TCO1_STS);
+ ps->tco2_sts = tco_read_reg(TCO2_STS);
+
+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
+ ps->tco1_sts, ps->tco2_sts);
+
+ pmc = pmc_mmio_regs();
+ ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
+ ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
+ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
+ ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+
+ printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
+ ps->gen_pmcon_a, ps->gen_pmcon_b);
+
+ printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
+ ps->gblrst_cause[0], ps->gblrst_cause[1]);
+}
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index c3bfdbb..75d7985 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -13,7 +13,6 @@
# GNU General Public License for more details.
#
-romstage-y += power_state.c
romstage-y += romstage.c
romstage-y += fsp_params.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c
deleted file mode 100644
index 9137507..0000000
--- a/src/soc/intel/cannonlake/romstage/power_state.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/mmio.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <intelblocks/pmclib.h>
-#include <intelblocks/tco.h>
-#include <string.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-static inline int deep_s3_enabled(void)
-{
- uint32_t deep_s3_pol;
-
- deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
- return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
-}
-
-/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int soc_prev_sleep_state(const struct chipset_power_state *ps,
- int prev_sleep_state)
-{
-
- /*
- * Check for any power failure to determine if this a wake from
- * S5 because the PCH does not set the WAK_STS bit when waking
- * from a true G3 state.
- */
- if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
- prev_sleep_state = ACPI_S5;
-
- /*
- * If waking from S3 determine if deep S3 is enabled. If not,
- * need to check both deep sleep well and normal suspend well.
- * Otherwise just check deep sleep well.
- */
- if (prev_sleep_state == ACPI_S3) {
- /* PWR_FLR represents deep sleep power well loss. */
- uint32_t mask = PWR_FLR;
-
- /* If deep s3 isn't enabled check the suspend well too. */
- if (!deep_s3_enabled())
- mask |= SUS_PWR_FLR;
-
- if (ps->gen_pmcon_b & mask)
- prev_sleep_state = ACPI_S5;
- }
-
- return prev_sleep_state;
-}
-
-void soc_fill_power_state(struct chipset_power_state *ps)
-{
- uint8_t *pmc;
-
- ps->tco1_sts = tco_read_reg(TCO1_STS);
- ps->tco2_sts = tco_read_reg(TCO2_STS);
-
- printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
- ps->tco1_sts, ps->tco2_sts);
-
- pmc = pmc_mmio_regs();
- ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
- ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
- ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
- ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
-
- printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
- ps->gen_pmcon_a, ps->gen_pmcon_b);
-
- printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
- ps->gblrst_cause[0], ps->gblrst_cause[1]);
-}
--
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Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31449
to review the following change.
Change subject: src/device/Kconfig: Add support for discrete VGA OpROM inclusion at config UI
......................................................................
src/device/Kconfig: Add support for discrete VGA OpROM inclusion at config UI
Create the way of adding the discrete VGA OpROM at config UI ( alternative to
./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom )
DGPU options are accessible only if CONFIG_MULTIPLE_VGA_ADAPTERS is enabled.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a
---
M src/arch/x86/Makefile.inc
M src/device/Kconfig
2 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31449/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8dafac8..47ef66b 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -47,6 +47,13 @@
pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))
pci$(stripped_vgabios_id).rom-type := optionrom
+ifeq ($(CONFIG_MULTIPLE_VGA_ADAPTERS),y)
+stripped_vgabios_dgpu_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_ID))
+cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom
+pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE))
+pci$(stripped_vgabios_dgpu_id).rom-type := optionrom
+endif
+
verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
diff --git a/src/device/Kconfig b/src/device/Kconfig
index b90b15f..33c1e5b3 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -613,6 +613,41 @@
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
+config VGA_BIOS_DGPU
+ bool "Add a Discrete VGA BIOS image"
+ depends on ARCH_X86 && MULTIPLE_VGA_ADAPTERS
+ help
+ Select this option if you have a VGA BIOS image for Discrete GPU
+ that you would like to add to your ROM.
+
+ You will be able to specify the location and file name of the
+ image later.
+
+config VGA_BIOS_DGPU_FILE
+ string "Discrete VGA BIOS path and filename"
+ depends on VGA_BIOS_DGPU
+ default "vgabios_dgpu.bin"
+ help
+ The path and filename of the file to use as VGA BIOS for Discrete GPU.
+
+config VGA_BIOS_DGPU_ID
+ string "Discrete VGA device PCI IDs"
+ depends on VGA_BIOS_DGPU
+ default "1002,6663"
+ help
+ The comma-separated PCI vendor and device ID that would associate
+ your VGA BIOS to your discrete video card.
+
+ Examples:
+ 1002,6663 for HD 8570M
+ 1002,6665 for R5 M230
+
+ In the above examples 1002 is the PCI vendor ID (in hex, but without
+ the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the
+ discrete video card (also in hex, without "0x" prefix).
+
+ Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
+
config INTEL_GMA_HAVE_VBT
bool
help
--
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