coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/intel/wifi/Kconfig: disable DRIVERS_INTEL_WIFI if !SYSTEM_TYP...
by mikeb mikeb (Code Review) 09 Mar '19

09 Mar '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31222 to review the following change. Change subject: drivers/intel/wifi/Kconfig: disable DRIVERS_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP ...................................................................... drivers/intel/wifi/Kconfig: disable DRIVERS_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP Intel PCI-e WiFi adapters are rare outside of laptops. DRIVERS_INTEL_WIFI should not be selected by default if the mainboard is not a laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9a7e5cd515da4ee4c4176227eea2e863ed55c420 --- M src/drivers/intel/wifi/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31222/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..80a7ef8 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 - default y if PCIEXP_PLUGIN_SUPPORT + default y if PCIEXP_PLUGIN_SUPPORT && !SYSTEM_TYPE_LAPTOP help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. -- To view, visit https://review.coreboot.org/c/coreboot/+/31222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a7e5cd515da4ee4c4176227eea2e863ed55c420 Gerrit-Change-Number: 31222 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/emulation/Kconfig: disable DRIVERS_INTEL_WIFI by default
by mikeb mikeb (Code Review) 09 Mar '19

09 Mar '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31308 to review the following change. Change subject: src/mainboard/emulation/Kconfig: disable DRIVERS_INTEL_WIFI by default ...................................................................... src/mainboard/emulation/Kconfig: disable DRIVERS_INTEL_WIFI by default It is impossible to insert the Intel PCI-e WiFi adapter to any of the Emulation boards because they are not physical, so this driver option should be disabled by default. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ia5802b3234f984d906c6a1048ed8176f85f9bb99 --- M src/mainboard/emulation/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31308/1 diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 759b1de..f9e1198 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -19,4 +19,8 @@ string default "Emulation" +config DRIVERS_INTEL_WIFI + bool + default n + endif # VENDOR_EMULATION -- To view, visit https://review.coreboot.org/c/coreboot/+/31308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5802b3234f984d906c6a1048ed8176f85f9bb99 Gerrit-Change-Number: 31308 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure
by Nico Huber (Code Review) 09 Mar '19

09 Mar '19

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Change in ...coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure
by Nico Huber (Code Review) 09 Mar '19

09 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29329 ) Change subject: drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure ...................................................................... Patch Set 5: (2 comments) What you describe sounds exactly like what the original code tries to accomplish (based on `RTC_VRT`). So this seems to be a workaround for either the chipset or the board? The name of the Kconfig (if it is really necessary) should reflect that this is not about normal behavior. "Reset time on rtc powerfail" is what we always do, just somehow your chipset fails to report the failure in the generic way, it seems. https://review.coreboot.org/#/c/29329/5/src/drivers/pc80/rtc/mc146818rtc.c File src/drivers/pc80/rtc/mc146818rtc.c: https://review.coreboot.org/#/c/29329/5/src/drivers/pc80/rtc/mc146818rtc.c@… PS5, Line 101: invalid Looking at its usage and the "Clear requested" in the printk() below. I guess this is just the wrong parameter to trigger a date reset. I'm not sure if changing the meaning of a parameter via Kconfig is a good idea. https://review.coreboot.org/#/c/29329/5/src/drivers/pc80/rtc/mc146818rtc.c@… PS5, Line 154: if (cmos_invalid) I would simply adapt this condition, e.g. if (cmos_invalid || (CONFIG(RESET_TIME_ON_CMOS_CLEAR_REQUEST) && invalid)) -- To view, visit https://review.coreboot.org/c/coreboot/+/29329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206 Gerrit-Change-Number: 29329 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 08 Mar 2019 15:46:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
by Frans Hendriks (Code Review) 09 Mar '19

09 Mar '19

Frans Hendriks has removed Hannah Williams from this change. ( https://review.coreboot.org/c/coreboot/+/29417 ) Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code ...................................................................... Removed reviewer Hannah Williams. -- To view, visit https://review.coreboot.org/c/coreboot/+/29417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606 Gerrit-Change-Number: 29417 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
by Subrata Banik (Code Review) 09 Mar '19

09 Mar '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 ) Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 52: > Move it to the new destination. Document the main idea of the PEIM > to PEIM Interface. Adapt the MultiProcessorInit.md with the correct > naming and drop the camel case filename got it. -- To view, visit https://review.coreboot.org/c/coreboot/+/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 52 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Fri, 08 Mar 2019 14:40:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
by Philipp Deppenwiese (Code Review) 09 Mar '19

09 Mar '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 ) Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 52: Move it to the new destination. Document the main idea of the PEIM to PEIM Interface. Adapt the MultiProcessorInit.md with the correct naming and drop the camel case filename -- To view, visit https://review.coreboot.org/c/coreboot/+/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 52 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Fri, 08 Mar 2019 14:39:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Reserve IOAPIC and ROM resources
by Frans Hendriks (Code Review) 09 Mar '19

09 Mar '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29423 ) Change subject: soc/intel/braswell: Reserve IOAPIC and ROM resources ...................................................................... Patch Set 10: (1 comment) Will implement your suggestion https://review.coreboot.org/#/c/29423/10/src/soc/intel/braswell/southcluste… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29423/10/src/soc/intel/braswell/southcluste… PS10, Line 82: (CONFIG_COREBOOT_ROMSIZE_KB*KiB)); /* BIOS ROM */ > This has simply a static size in `acpi/lpc.asl`, the maximum […] Thanks for pointing. Will create patch for this -- To view, visit https://review.coreboot.org/c/coreboot/+/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 10 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 08 Mar 2019 14:07:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mb: Remove include <commonlib/loglevel.h>
by HAOUAS Elyes (Code Review) 09 Mar '19

09 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31239 Change subject: src/mb: Remove include <commonlib/loglevel.h> ...................................................................... src/mb: Remove include <commonlib/loglevel.h> This file is alreasy included in <console/console.h> Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c 26 files changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31239/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index bb14c59..80ad1aa 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -27,7 +27,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <arch/cpu.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7d245e7..1252346 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 87ef750..2b37f9b 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 40ff0bb..bf5c9de 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 538e7a7..7a38f95 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 4316d4f..48ece89 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index c59816e..4bb35fb 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 58fea20..3419df5 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -29,7 +29,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <spd.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 11d6837..9ae3834 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -18,7 +18,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 0e65b53..4c35df696 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 0081c2f..16786aa 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -18,7 +18,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 76e2290..2b2f0a2 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -16,7 +16,6 @@ */ #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 3f78c4c..3bb622d 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 4802b9d..122e510 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 8dbd9e5..9ececa8 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 061764d..602faa2 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -27,7 +27,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 1e19b9e..af8fd2a 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index f587257..f71858a 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <device/pci_def.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 94d2abe..09fc200 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 9745895..a41b6cd 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 19b6022..5990c4d 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 252add0..33af7d6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 16d3068..078e19b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 9701193..d0c021f 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 6c405b8..9c36499 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -21,7 +21,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <timestamp.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index ef3a372..b4c08aa 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Gerrit-Change-Number: 31239 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

7 17

Change in ...coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Nico Huber (Code Review) 09 Mar '19

09 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster… File src/soc/intel/braswell/southcluster.c: https://review.coreboot.org/#/c/29398/6/src/soc/intel/braswell/southcluster… PS6, Line 621: > > SERIRQ in continuous mode, interrupts from serial appear on all cores through IOAPIC irq4 […] That IRQ4 was an example specifically for a serial UART. What really matters is the state of `ilb_base + ILB_OIC`. You can just dump it inside enable_serirq_quiet_mode(). -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 08 Mar 2019 13:34:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2019