coreboot-gerrit March 2019

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Change in ...coreboot[master]: {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h
by Kyösti Mälkki (Code Review) 13 Mar '19

13 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30321 ) Change subject: {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h ...................................................................... {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30321 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asrock/g41c-gs/dsdt.asl M src/mainboard/asus/p5qpl-am/dsdt.asl M src/mainboard/foxconn/g41s-k/dsdt.asl M src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl M src/mainboard/intel/dg41wv/dsdt.asl M src/mainboard/lenovo/thinkcentre_a58/dsdt.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/southbridge/intel/i82801gx/acpi/ich7.asl 8 files changed, 2 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/asrock/g41c-gs/dsdt.asl b/src/mainboard/asrock/g41c-gs/dsdt.asl index 4eade3d..002dfca 100644 --- a/src/mainboard/asrock/g41c-gs/dsdt.asl +++ b/src/mainboard/asrock/g41c-gs/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801gx/i82801gx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/asus/p5qpl-am/dsdt.asl b/src/mainboard/asus/p5qpl-am/dsdt.asl index 4eade3d..002dfca 100644 --- a/src/mainboard/asus/p5qpl-am/dsdt.asl +++ b/src/mainboard/asus/p5qpl-am/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801gx/i82801gx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/foxconn/g41s-k/dsdt.asl b/src/mainboard/foxconn/g41s-k/dsdt.asl index 4eade3d..002dfca 100644 --- a/src/mainboard/foxconn/g41s-k/dsdt.asl +++ b/src/mainboard/foxconn/g41s-k/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801gx/i82801gx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl index 4eade3d..002dfca 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801gx/i82801gx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/intel/dg41wv/dsdt.asl b/src/mainboard/intel/dg41wv/dsdt.asl index 4eade3d..002dfca 100644 --- a/src/mainboard/intel/dg41wv/dsdt.asl +++ b/src/mainboard/intel/dg41wv/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801gx/i82801gx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl index 4eade3d..002dfca 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <southbridge/intel/i82801gx/i82801gx.h> - #include <arch/acpi.h> DefinitionBlock( "dsdt.aml", diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 081b740..72f97e4 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -16,7 +16,6 @@ #include "hostbridge.asl" #include "../iomap.h" -#include <southbridge/intel/i82801gx/i82801gx.h> /* PCI Device Resource Consumption */ Device (PDRC) diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index d24c8af..d63b00e 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -16,6 +16,8 @@ /* Intel 82801Gx support */ +#include "../i82801gx.h" + Scope(\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. -- To view, visit https://review.coreboot.org/c/coreboot/+/30321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Gerrit-Change-Number: 30321 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h
by Kyösti Mälkki (Code Review) 13 Mar '19

13 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30321 ) Change subject: {mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.h ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Gerrit-Change-Number: 30321 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 13 Mar 2019 04:17:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
by Subrata Banik (Code Review) 13 Mar '19

13 Mar '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 ) Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 55: > Thanks Idwer. @Werner please check your requirements @Subrata, > let's wait before we merge it there are some tests ongoing. Yes @Idwer, can you please help me to know your requirements so that i can intercept the same in this CL or future CL as it required. -- To view, visit https://review.coreboot.org/c/coreboot/+/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 55 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 13 Mar 2019 02:41:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
by Philipp Deppenwiese (Code Review) 13 Mar '19

13 Mar '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 ) Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 55: Thanks Idwer. @Werner please check your requirements @Subrata, let's wait before we merge it there are some tests ongoing. -- To view, visit https://review.coreboot.org/c/coreboot/+/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 55 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 13 Mar 2019 00:52:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
by Idwer Vollering (Code Review) 13 Mar '19

13 Mar '19

Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 ) Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs ...................................................................... Patch Set 55: Code-Review-1 "I've indicated my unhappiness with this direction, but it's also clear that I am not connected enough to these decisions that I should block it. I'll leave it at -1 for now and let others with more knowledge make the call. Thanks." -- To view, visit https://review.coreboot.org/c/coreboot/+/25634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Gerrit-Change-Number: 25634 Gerrit-PatchSet: 55 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Tue, 12 Mar 2019 19:03:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake
by Subrata Banik (Code Review) 13 Mar '19

13 Mar '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31855 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake ...................................................................... vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake Update header files for FSP for cometlake platform version 1065 BUG=b:125439832 Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h 2 files changed, 1,420 insertions(+), 1,382 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h index a775116..85dbe70 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h @@ -1144,17 +1144,22 @@ **/ UINT8 SmbusEnable; -/** Offset 0x0251 - PCH HPET Enabled - Enable/disable PCH HPET. - $EN_DIS +/** Offset 0x0251 - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] + have the same setting + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), + 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC) **/ - UINT8 PchHpetEnable; + UINT8 PlatformDebugConsent; -/** Offset 0x0252 - PCH HPET BDF valid - Whether the BDF value is valid. 0: Disable; 1: Enable. - $EN_DIS +/** Offset 0x0252 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change **/ - UINT8 PchHpetBdfValid; + UINT8 DciUsb3TypecUfpDbg; /** Offset 0x0253 - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' @@ -1163,1061 +1168,1052 @@ **/ UINT8 PchTraceHubMode; -/** Offset 0x0254 - Enable Intel HD Audio (Azalia) +/** Offset 0x0254 - PCH Trace Hub Memory Region 0 buffer Size + Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg0Size; + +/** Offset 0x0255 - PCH Trace Hub Memory Region 1 buffer Size + Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg1Size; + +/** Offset 0x0256 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS **/ UINT8 PchHdaEnable; -/** Offset 0x0255 - Enable PCH ISH Controller +/** Offset 0x0257 - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS **/ UINT8 PchIshEnable; -/** Offset 0x0256 -**/ - UINT8 UnusedUpdSpace7[2]; - -/** Offset 0x0258 - The HPET Base Address - The HPET base address. Default is 0xFED00000. -**/ - UINT32 PchHpetBase; - -/** Offset 0x025C - PCH HPET Bus Number - Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0. -**/ - UINT8 PchHpetBusNumber; - -/** Offset 0x025D - PCH HPET Device Number - Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. -**/ - UINT8 PchHpetDeviceNumber; - -/** Offset 0x025E - PCH HPET Function Number - Function Number HPETn used as Requestor / Completer ID. Default is 0x00. -**/ - UINT8 PchHpetFunctionNumber; - -/** Offset 0x025F - Enable PCH HSIO PCIE Rx Set Ctle +/** Offset 0x0258 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtleEnable[24]; -/** Offset 0x0277 - PCH HSIO PCIE Rx Set Ctle Value +/** Offset 0x0270 - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtle[24]; -/** Offset 0x028F - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override +/** Offset 0x0288 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; -/** Offset 0x02A7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x02A0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; -/** Offset 0x02BF - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override +/** Offset 0x02B8 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; -/** Offset 0x02D7 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x02D0 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; -/** Offset 0x02EF - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override +/** Offset 0x02E8 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; -/** Offset 0x0307 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value +/** Offset 0x0300 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; -/** Offset 0x031F - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0318 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; -/** Offset 0x0337 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value +/** Offset 0x0330 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen1DeEmph[24]; -/** Offset 0x034F - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override +/** Offset 0x0348 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; -/** Offset 0x0367 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value +/** Offset 0x0360 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; -/** Offset 0x037F - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override +/** Offset 0x0378 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; -/** Offset 0x0397 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value +/** Offset 0x0390 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; -/** Offset 0x03AF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override +/** Offset 0x03A8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; -/** Offset 0x03B7 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value +/** Offset 0x03B0 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. **/ UINT8 PchSataHsioRxGen1EqBoostMag[8]; -/** Offset 0x03BF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override +/** Offset 0x03B8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; -/** Offset 0x03C7 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value +/** Offset 0x03C0 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. **/ UINT8 PchSataHsioRxGen2EqBoostMag[8]; -/** Offset 0x03CF - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override +/** Offset 0x03C8 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; -/** Offset 0x03D7 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value +/** Offset 0x03D0 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. **/ UINT8 PchSataHsioRxGen3EqBoostMag[8]; -/** Offset 0x03DF - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override +/** Offset 0x03D8 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; -/** Offset 0x03E7 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value +/** Offset 0x03E0 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchSataHsioTxGen1DownscaleAmp[8]; -/** Offset 0x03EF - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override +/** Offset 0x03E8 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; -/** Offset 0x03F7 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value +/** Offset 0x03F0 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchSataHsioTxGen2DownscaleAmp[8]; -/** Offset 0x03FF - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override +/** Offset 0x03F8 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; -/** Offset 0x0407 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value +/** Offset 0x0400 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchSataHsioTxGen3DownscaleAmp[8]; -/** Offset 0x040F - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0408 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen1DeEmphEnable[8]; -/** Offset 0x0417 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting +/** Offset 0x0410 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchSataHsioTxGen1DeEmph[8]; -/** Offset 0x041F - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0418 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen2DeEmphEnable[8]; -/** Offset 0x0427 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting +/** Offset 0x0420 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchSataHsioTxGen2DeEmph[8]; -/** Offset 0x042F - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0428 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen3DeEmphEnable[8]; -/** Offset 0x0437 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting +/** Offset 0x0430 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchSataHsioTxGen3DeEmph[8]; -/** Offset 0x043F - PCH LPC Enhance the port 8xh decoding +/** Offset 0x0438 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h. $EN_DIS **/ UINT8 PchLpcEnhancePort8xhDecoding; -/** Offset 0x0440 - PCH Acpi Base - Power management I/O base address. Default is 0x1800. -**/ - UINT16 PchAcpiBase; - -/** Offset 0x0442 - PCH Port80 Route +/** Offset 0x0439 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. $EN_DIS **/ UINT8 PchPort80Route; -/** Offset 0x0443 - Enable SMBus ARP support +/** Offset 0x043A - Enable SMBus ARP support Enable SMBus ARP support. $EN_DIS **/ UINT8 SmbusArpEnable; -/** Offset 0x0444 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x0446 - Number of RsvdSmbusAddressTable. +/** Offset 0x043B - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0447 +/** Offset 0x043C - SMBUS Base Address + SMBUS Base Address (IO space). **/ - UINT8 UnusedUpdSpace8; + UINT16 PchSmbusIoBase; -/** Offset 0x0448 - Point of RsvdSmbusAddressTable +/** Offset 0x043E - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x0440 - Point of RsvdSmbusAddressTable Array of addresses reserved for non-ARP-capable SMBus devices. **/ UINT32 RsvdSmbusAddressTablePtr; -/** Offset 0x044C - Trace Hub Memory Region 0 - Trace Hub Memory Region 0. -**/ - UINT32 TraceHubMemReg0Size; - -/** Offset 0x0450 - Trace Hub Memory Region 1 - Trace Hub Memory Region 1. -**/ - UINT32 TraceHubMemReg1Size; - -/** Offset 0x0454 - Enable PCIE RP Mask +/** Offset 0x0444 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x0458 - Debug Interfaces +/** Offset 0x0448 - Enable PCIe IMR + 0:Disable, 1:Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x0449 - Root port number for IMR. + Root port number for IMR. +**/ + UINT8 ImrRpSelection; + +/** Offset 0x044A - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x044B - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x0459 - SerialIo Uart Number Selection +/** Offset 0x044C - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 PcdSerialIoUartNumber; -/** Offset 0x045A - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x045B - ReservedPchPreMem +/** Offset 0x044D - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS **/ UINT8 ReservedPchPreMem[16]; -/** Offset 0x046B - ISA Serial Base selection +/** Offset 0x045D - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x046C - GT PLL voltage offset +/** Offset 0x045E - GT PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 GtPllVoltageOffset; -/** Offset 0x046D - Ring PLL voltage offset +/** Offset 0x045F - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 RingPllVoltageOffset; -/** Offset 0x046E - System Agent PLL voltage offset +/** Offset 0x0460 - System Agent PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 SaPllVoltageOffset; -/** Offset 0x046F - Memory Controller PLL voltage offset +/** Offset 0x0461 - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 McPllVoltageOffset; -/** Offset 0x0470 - MRC Safe Config +/** Offset 0x0462 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x0471 - PcdSerialDebugBaudRate +/** Offset 0x0463 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200 **/ UINT8 PcdSerialDebugBaudRate; -/** Offset 0x0472 - HobBufferSize +/** Offset 0x0464 - HobBufferSize Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value **/ UINT8 HobBufferSize; -/** Offset 0x0473 - Early Command Training +/** Offset 0x0465 - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x0474 - SenseAmp Offset Training +/** Offset 0x0466 - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS **/ UINT8 SOT; -/** Offset 0x0475 - Early ReadMPR Timing Centering 2D +/** Offset 0x0467 - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS **/ UINT8 ERDMPRTC2D; -/** Offset 0x0476 - Read MPR Training +/** Offset 0x0468 - Read MPR Training Enables/Disable Read MPR Training $EN_DIS **/ UINT8 RDMPRT; -/** Offset 0x0477 - Receive Enable Training +/** Offset 0x0469 - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS **/ UINT8 RCVET; -/** Offset 0x0478 - Jedec Write Leveling +/** Offset 0x046A - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS **/ UINT8 JWRL; -/** Offset 0x0479 - Early Write Time Centering 2D +/** Offset 0x046B - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS **/ UINT8 EWRTC2D; -/** Offset 0x047A - Early Read Time Centering 2D +/** Offset 0x046C - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS **/ UINT8 ERDTC2D; -/** Offset 0x047B - Write Timing Centering 1D +/** Offset 0x046D - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS **/ UINT8 WRTC1D; -/** Offset 0x047C - Write Voltage Centering 1D +/** Offset 0x046E - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS **/ UINT8 WRVC1D; -/** Offset 0x047D - Read Timing Centering 1D +/** Offset 0x046F - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS **/ UINT8 RDTC1D; -/** Offset 0x047E - Dimm ODT Training +/** Offset 0x0470 - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS **/ UINT8 DIMMODTT; -/** Offset 0x047F - DIMM RON Training +/** Offset 0x0471 - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS **/ UINT8 DIMMRONT; -/** Offset 0x0480 - Write Drive Strength/Equalization 2D +/** Offset 0x0472 - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_DIS **/ UINT8 WRDSEQT; -/** Offset 0x0481 - Write Slew Rate Training +/** Offset 0x0473 - Write Slew Rate Training Enables/Disable Write Slew Rate Training $EN_DIS **/ UINT8 WRSRT; -/** Offset 0x0482 - Read ODT Training +/** Offset 0x0474 - Read ODT Training Enables/Disable Read ODT Training $EN_DIS **/ UINT8 RDODTT; -/** Offset 0x0483 - Read Equalization Training +/** Offset 0x0475 - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS **/ UINT8 RDEQT; -/** Offset 0x0484 - Read Amplifier Training +/** Offset 0x0476 - Read Amplifier Training Enables/Disable Read Amplifier Training $EN_DIS **/ UINT8 RDAPT; -/** Offset 0x0485 - Write Timing Centering 2D +/** Offset 0x0477 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS **/ UINT8 WRTC2D; -/** Offset 0x0486 - Read Timing Centering 2D +/** Offset 0x0478 - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS **/ UINT8 RDTC2D; -/** Offset 0x0487 - Write Voltage Centering 2D +/** Offset 0x0479 - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS **/ UINT8 WRVC2D; -/** Offset 0x0488 - Read Voltage Centering 2D +/** Offset 0x047A - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS **/ UINT8 RDVC2D; -/** Offset 0x0489 - Command Voltage Centering +/** Offset 0x047B - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS **/ UINT8 CMDVC; -/** Offset 0x048A - Late Command Training +/** Offset 0x047C - Late Command Training Enables/Disable Late Command Training $EN_DIS **/ UINT8 LCT; -/** Offset 0x048B - Round Trip Latency Training +/** Offset 0x047D - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS **/ UINT8 RTL; -/** Offset 0x048C - Turn Around Timing Training +/** Offset 0x047E - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS **/ UINT8 TAT; -/** Offset 0x048D - Memory Test +/** Offset 0x047F - Memory Test Enables/Disable Memory Test $EN_DIS **/ UINT8 MEMTST; -/** Offset 0x048E - DIMM SPD Alias Test +/** Offset 0x0480 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS **/ UINT8 ALIASCHK; -/** Offset 0x048F - Receive Enable Centering 1D +/** Offset 0x0481 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS **/ UINT8 RCVENC1D; -/** Offset 0x0490 - Retrain Margin Check +/** Offset 0x0482 - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS **/ UINT8 RMC; -/** Offset 0x0491 - Write Drive Strength Up/Dn independently +/** Offset 0x0483 - Write Drive Strength Up/Dn independently Enables/Disable Write Drive Strength Up/Dn independently $EN_DIS **/ UINT8 WRDSUDT; -/** Offset 0x0492 - ECC Support +/** Offset 0x0484 - ECC Support Enables/Disable ECC Support $EN_DIS **/ UINT8 EccSupport; -/** Offset 0x0493 - Memory Remap +/** Offset 0x0485 - Memory Remap Enables/Disable Memory Remap $EN_DIS **/ UINT8 RemapEnable; -/** Offset 0x0494 - Rank Interleave support +/** Offset 0x0486 - Rank Interleave support Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time. $EN_DIS **/ UINT8 RankInterleave; -/** Offset 0x0495 - Enhanced Interleave support +/** Offset 0x0487 - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS **/ UINT8 EnhancedInterleave; -/** Offset 0x0496 - Memory Trace +/** Offset 0x0488 - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed. $EN_DIS **/ UINT8 MemoryTrace; -/** Offset 0x0497 - Ch Hash Support +/** Offset 0x0489 - Ch Hash Support Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ UINT8 ChHashEnable; -/** Offset 0x0498 - Extern Therm Status +/** Offset 0x048A - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS **/ UINT8 EnableExtts; -/** Offset 0x0499 - Closed Loop Therm Manage +/** Offset 0x048B - Closed Loop Therm Manage Enables/Disable Closed Loop Therm Manage $EN_DIS **/ UINT8 EnableCltm; -/** Offset 0x049A - Open Loop Therm Manage +/** Offset 0x048C - Open Loop Therm Manage Enables/Disable Open Loop Therm Manage $EN_DIS **/ UINT8 EnableOltm; -/** Offset 0x049B - DDR PowerDown and idle counter +/** Offset 0x048D - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter $EN_DIS **/ UINT8 EnablePwrDn; -/** Offset 0x049C - DDR PowerDown and idle counter - LPDDR +/** Offset 0x048E - DDR PowerDown and idle counter - LPDDR Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDnLpddr; -/** Offset 0x049D - Use user provided power weights, scale factor, and channel power floor values +/** Offset 0x048F - Use user provided power weights, scale factor, and channel power floor values Enables/Disable Use user provided power weights, scale factor, and channel power floor values $EN_DIS **/ UINT8 UserPowerWeightsEn; -/** Offset 0x049E - RAPL PL Lock +/** Offset 0x0490 - RAPL PL Lock Enables/Disable RAPL PL Lock $EN_DIS **/ UINT8 RaplLim2Lock; -/** Offset 0x049F - RAPL PL 2 enable +/** Offset 0x0491 - RAPL PL 2 enable Enables/Disable RAPL PL 2 enable $EN_DIS **/ UINT8 RaplLim2Ena; -/** Offset 0x04A0 - RAPL PL 1 enable +/** Offset 0x0492 - RAPL PL 1 enable Enables/Disable RAPL PL 1 enable $EN_DIS **/ UINT8 RaplLim1Ena; -/** Offset 0x04A1 - SelfRefresh Enable +/** Offset 0x0493 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS **/ UINT8 SrefCfgEna; -/** Offset 0x04A2 - Throttler CKEMin Defeature - LPDDR +/** Offset 0x0494 - Throttler CKEMin Defeature - LPDDR Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS **/ UINT8 ThrtCkeMinDefeatLpddr; -/** Offset 0x04A3 - Throttler CKEMin Defeature +/** Offset 0x0495 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x04A4 - Enable RH Prevention +/** Offset 0x0496 - Enable RH Prevention Enables/Disable RH Prevention $EN_DIS **/ UINT8 RhPrevention; -/** Offset 0x04A5 - Exit On Failure (MRC) +/** Offset 0x0497 - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS **/ UINT8 ExitOnFailure; -/** Offset 0x04A6 - LPDDR Thermal Sensor +/** Offset 0x0498 - LPDDR Thermal Sensor Enables/Disable LPDDR Thermal Sensor $EN_DIS **/ UINT8 DdrThermalSensor; -/** Offset 0x04A7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x0499 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedClock; -/** Offset 0x04A8 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x049A - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedZq; -/** Offset 0x04A9 +/** Offset 0x049B **/ - UINT8 UnusedUpdSpace9; + UINT8 UnusedUpdSpace7; -/** Offset 0x04AA - Ch Hash Mask +/** Offset 0x049C - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6 **/ UINT16 ChHashMask; -/** Offset 0x04AC - Base reference clock value +/** Offset 0x049E +**/ + UINT8 UnusedUpdSpace8[2]; + +/** Offset 0x04A0 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz **/ UINT32 BClkFrequency; -/** Offset 0x04B0 - Ch Hash Interleaved Bit +/** Offset 0x04A4 - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 **/ UINT8 ChHashInterleaveBit; -/** Offset 0x04B1 - Energy Scale Factor +/** Offset 0x04A5 - Energy Scale Factor Energy Scale Factor, Default is 4 **/ UINT8 EnergyScaleFact; -/** Offset 0x04B2 - EPG DIMM Idd3N +/** Offset 0x04A6 - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26 **/ UINT16 Idd3n; -/** Offset 0x04B4 - EPG DIMM Idd3P +/** Offset 0x04A8 - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11 **/ UINT16 Idd3p; -/** Offset 0x04B6 - CMD Slew Rate Training +/** Offset 0x04AA - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS **/ UINT8 CMDSR; -/** Offset 0x04B7 - CMD Drive Strength and Tx Equalization +/** Offset 0x04AB - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization $EN_DIS **/ UINT8 CMDDSEQ; -/** Offset 0x04B8 - CMD Normalization +/** Offset 0x04AC - CMD Normalization Enable/Disable CMD Normalization $EN_DIS **/ UINT8 CMDNORM; -/** Offset 0x04B9 - Early DQ Write Drive Strength and Equalization Training +/** Offset 0x04AD - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive Strength and Equalization Training $EN_DIS **/ UINT8 EWRDSEQ; -/** Offset 0x04BA - RH Activation Probability +/** Offset 0x04AE - RH Activation Probability RH Activation Probability, Probability value is 1/2^(inputvalue) **/ UINT8 RhActProbability; -/** Offset 0x04BB - RAPL PL 2 WindowX +/** Offset 0x04AF - RAPL PL 2 WindowX Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindX; -/** Offset 0x04BC - RAPL PL 2 WindowY +/** Offset 0x04B0 - RAPL PL 2 WindowY Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindY; -/** Offset 0x04BD - RAPL PL 1 WindowX +/** Offset 0x04B1 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) **/ UINT8 RaplLim1WindX; -/** Offset 0x04BE - RAPL PL 1 WindowY +/** Offset 0x04B2 - RAPL PL 1 WindowY Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) **/ UINT8 RaplLim1WindY; -/** Offset 0x04BF +/** Offset 0x04B3 **/ - UINT8 UnusedUpdSpace10; + UINT8 UnusedUpdSpace9; -/** Offset 0x04C0 - RAPL PL 2 Power +/** Offset 0x04B4 - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (222= Def) **/ UINT16 RaplLim2Pwr; -/** Offset 0x04C2 - RAPL PL 1 Power +/** Offset 0x04B6 - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (0= Def) **/ UINT16 RaplLim1Pwr; -/** Offset 0x04C4 - Warm Threshold Ch0 Dimm0 +/** Offset 0x04B8 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm0; -/** Offset 0x04C5 - Warm Threshold Ch0 Dimm1 +/** Offset 0x04B9 - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm1; -/** Offset 0x04C6 - Warm Threshold Ch1 Dimm0 +/** Offset 0x04BA - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm0; -/** Offset 0x04C7 - Warm Threshold Ch1 Dimm1 +/** Offset 0x04BB - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm1; -/** Offset 0x04C8 - Hot Threshold Ch0 Dimm0 +/** Offset 0x04BC - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm0; -/** Offset 0x04C9 - Hot Threshold Ch0 Dimm1 +/** Offset 0x04BD - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm1; -/** Offset 0x04CA - Hot Threshold Ch1 Dimm0 +/** Offset 0x04BE - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm0; -/** Offset 0x04CB - Hot Threshold Ch1 Dimm1 +/** Offset 0x04BF - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm1; -/** Offset 0x04CC - Warm Budget Ch0 Dimm0 +/** Offset 0x04C0 - Warm Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh0Dimm0; -/** Offset 0x04CD - Warm Budget Ch0 Dimm1 +/** Offset 0x04C1 - Warm Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh0Dimm1; -/** Offset 0x04CE - Warm Budget Ch1 Dimm0 +/** Offset 0x04C2 - Warm Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh1Dimm0; -/** Offset 0x04CF - Warm Budget Ch1 Dimm1 +/** Offset 0x04C3 - Warm Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh1Dimm1; -/** Offset 0x04D0 - Hot Budget Ch0 Dimm0 +/** Offset 0x04C4 - Hot Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh0Dimm0; -/** Offset 0x04D1 - Hot Budget Ch0 Dimm1 +/** Offset 0x04C5 - Hot Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh0Dimm1; -/** Offset 0x04D2 - Hot Budget Ch1 Dimm0 +/** Offset 0x04C6 - Hot Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh1Dimm0; -/** Offset 0x04D3 - Hot Budget Ch1 Dimm1 +/** Offset 0x04C7 - Hot Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh1Dimm1; -/** Offset 0x04D4 - Idle Energy Ch0Dimm0 +/** Offset 0x04C8 - Idle Energy Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh0Dimm0; -/** Offset 0x04D5 - Idle Energy Ch0Dimm1 +/** Offset 0x04C9 - Idle Energy Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh0Dimm1; -/** Offset 0x04D6 - Idle Energy Ch1Dimm0 +/** Offset 0x04CA - Idle Energy Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh1Dimm0; -/** Offset 0x04D7 - Idle Energy Ch1Dimm1 +/** Offset 0x04CB - Idle Energy Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh1Dimm1; -/** Offset 0x04D8 - PowerDown Energy Ch0Dimm0 +/** Offset 0x04CC - PowerDown Energy Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh0Dimm0; -/** Offset 0x04D9 - PowerDown Energy Ch0Dimm1 +/** Offset 0x04CD - PowerDown Energy Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh0Dimm1; -/** Offset 0x04DA - PowerDown Energy Ch1Dimm0 +/** Offset 0x04CE - PowerDown Energy Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh1Dimm0; -/** Offset 0x04DB - PowerDown Energy Ch1Dimm1 +/** Offset 0x04CF - PowerDown Energy Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh1Dimm1; -/** Offset 0x04DC - Activate Energy Ch0Dimm0 +/** Offset 0x04D0 - Activate Energy Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh0Dimm0; -/** Offset 0x04DD - Activate Energy Ch0Dimm1 +/** Offset 0x04D1 - Activate Energy Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh0Dimm1; -/** Offset 0x04DE - Activate Energy Ch1Dimm0 +/** Offset 0x04D2 - Activate Energy Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh1Dimm0; -/** Offset 0x04DF - Activate Energy Ch1Dimm1 +/** Offset 0x04D3 - Activate Energy Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh1Dimm1; -/** Offset 0x04E0 - Read Energy Ch0Dimm0 +/** Offset 0x04D4 - Read Energy Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh0Dimm0; -/** Offset 0x04E1 - Read Energy Ch0Dimm1 +/** Offset 0x04D5 - Read Energy Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh0Dimm1; -/** Offset 0x04E2 - Read Energy Ch1Dimm0 +/** Offset 0x04D6 - Read Energy Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh1Dimm0; -/** Offset 0x04E3 - Read Energy Ch1Dimm1 +/** Offset 0x04D7 - Read Energy Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh1Dimm1; -/** Offset 0x04E4 - Write Energy Ch0Dimm0 +/** Offset 0x04D8 - Write Energy Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh0Dimm0; -/** Offset 0x04E5 - Write Energy Ch0Dimm1 +/** Offset 0x04D9 - Write Energy Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh0Dimm1; -/** Offset 0x04E6 - Write Energy Ch1Dimm0 +/** Offset 0x04DA - Write Energy Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh1Dimm0; -/** Offset 0x04E7 - Write Energy Ch1Dimm1 +/** Offset 0x04DB - Write Energy Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh1Dimm1; -/** Offset 0x04E8 - Throttler CKEMin Timer +/** Offset 0x04DC - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30 **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x04E9 - Cke Rank Mapping +/** Offset 0x04DD - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to. **/ UINT8 CkeRankMapping; -/** Offset 0x04EA - Rapl Power Floor Ch0 +/** Offset 0x04DE - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh0; -/** Offset 0x04EB - Rapl Power Floor Ch1 +/** Offset 0x04DF - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh1; -/** Offset 0x04EC - Command Rate Support +/** Offset 0x04E0 - Command Rate Support CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS **/ UINT8 EnCmdRate; -/** Offset 0x04ED - REFRESH_2X_MODE +/** Offset 0x04E1 - REFRESH_2X_MODE 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only **/ UINT8 Refresh2X; -/** Offset 0x04EE - Energy Performance Gain +/** Offset 0x04E2 - Energy Performance Gain Enable/disable(default) Energy Performance Gain. $EN_DIS **/ UINT8 EpgEnable; -/** Offset 0x04EF - Row Hammer Solution +/** Offset 0x04E3 - Row Hammer Solution Type of method used to prevent Row Hammer. Default is Hardware RHP 0:Hardware RHP, 1:2x Refresh **/ UINT8 RhSolution; -/** Offset 0x04F0 - User Manual Threshold +/** Offset 0x04E4 - User Manual Threshold Disabled: Predefined threshold will be used.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserThresholdEnable; -/** Offset 0x04F1 - User Manual Budget +/** Offset 0x04E5 - User Manual Budget Disabled: Configuration of memories will defined the Budget value.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserBudgetEnable; -/** Offset 0x04F2 - TcritMax +/** Offset 0x04E6 - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax **/ UINT8 TsodTcritMax; -/** Offset 0x04F3 - Event mode +/** Offset 0x04E7 - Event mode Disable:Comparator mode.\n Enable:Interrupt mode $EN_DIS **/ UINT8 TsodEventMode; -/** Offset 0x04F4 - EVENT polarity +/** Offset 0x04E8 - EVENT polarity Disable:Active LOW.\n Enable:Active HIGH $EN_DIS **/ UINT8 TsodEventPolarity; -/** Offset 0x04F5 - Critical event only +/** Offset 0x04E9 - Critical event only Disable:Trips on alarm or critical.\n Enable:Trips only if criticaal temperature is reached $EN_DIS **/ UINT8 TsodCriticalEventOnly; -/** Offset 0x04F6 - Event output control +/** Offset 0x04EA - Event output control Disable:Event output disable.\n Enable:Event output enabled $EN_DIS **/ UINT8 TsodEventOutputControl; -/** Offset 0x04F7 - Alarm window lock bit +/** Offset 0x04EB - Alarm window lock bit Disable:Alarm trips are not locked and can be changed.\n Enable:Alarm trips are locked and cannot be changed $EN_DIS **/ UINT8 TsodAlarmwindowLockBit; -/** Offset 0x04F8 - Critical trip lock bit +/** Offset 0x04EC - Critical trip lock bit Disable:Critical trip is not locked and can be changed.\n Enable:Critical trip is locked and cannot be changed $EN_DIS **/ UINT8 TsodCriticaltripLockBit; -/** Offset 0x04F9 - Shutdown mode +/** Offset 0x04ED - Shutdown mode Disable:Temperature sensor enable.\n Enable:Temperature sensor disable $EN_DIS **/ UINT8 TsodShutdownMode; -/** Offset 0x04FA - ThighMax +/** Offset 0x04EE - ThighMax Thigh = ThighMax (Default is 93) **/ UINT8 TsodThigMax; -/** Offset 0x04FB - User Manual Thig and Tcrit +/** Offset 0x04EF - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\n Enabled: User Input will define for Thigh and Tcrit. @@ -2225,32 +2221,32 @@ **/ UINT8 TsodManualEnable; -/** Offset 0x04FC - Force OLTM or 2X Refresh when needed +/** Offset 0x04F0 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM.\n Enabled: = Force 2x Refresh. $EN_DIS **/ UINT8 ForceOltmOrRefresh2x; -/** Offset 0x04FD - Pwr Down Idle Timer +/** Offset 0x04F1 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo **/ UINT8 PwdwnIdleCounter; -/** Offset 0x04FE - Bitmask of ranks that have CA bus terminated +/** Offset 0x04F2 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating **/ UINT8 CmdRanksTerminated; -/** Offset 0x04FF - GDXC MOT enable +/** Offset 0x04F3 - GDXC MOT enable GDXC MOT enable. $EN_DIS **/ UINT8 GdxcEnable; -/** Offset 0x0500 - PcdSerialDebugLevel +/** Offset 0x04F4 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -2259,95 +2255,95 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0501 - Fivr Faults +/** Offset 0x04F5 - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 FivrFaults; -/** Offset 0x0502 - Fivr Efficiency +/** Offset 0x04F6 - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 FivrEfficiency; -/** Offset 0x0503 - Safe Mode Support +/** Offset 0x04F7 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x0504 - Ask MRC to clear memory content +/** Offset 0x04F8 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. $EN_DIS **/ UINT8 CleanMemory; -/** Offset 0x0505 - LpDdrDqDqsReTraining +/** Offset 0x04F9 - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining $EN_DIS **/ UINT8 LpDdrDqDqsReTraining; -/** Offset 0x0506 - Post Code Output Port +/** Offset 0x04FA - Post Code Output Port This option configures Post Code Output Port **/ UINT16 PostCodeOutputPort; -/** Offset 0x0508 - RMTLoopCount +/** Offset 0x04FC - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO **/ UINT8 RMTLoopCount; -/** Offset 0x0509 - BER Support +/** Offset 0x04FD - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation. 0:Disable, 1:Enable **/ UINT8 EnBER; -/** Offset 0x050A - Dual Dimm Per-Channel Board Type +/** Offset 0x04FE - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs. 0:1DPC, 1:2DPC **/ UINT8 DualDimmPerChannelBoardType; -/** Offset 0x050B - DDR4 Mixed U-DIMM 2DPC Limitation +/** Offset 0x04FF - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. Disable=0, Enable(Default)=1 $EN_DIS **/ UINT8 Ddr4MixedUDimm2DpcLimit; -/** Offset 0x050C - CFL Reserved +/** Offset 0x0500 - CFL Reserved Reserved FspmConfig CFL $EN_DIS **/ UINT8 ReservedFspmUpdCfl[2]; -/** Offset 0x050E - Memory Test on Warm Boot +/** Offset 0x0502 - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x050F - Throttler CKEMin Timer - LPDDR +/** Offset 0x0503 - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40 **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x0510 - State of X2APIC_OPT_OUT bit in the DMAR table +/** Offset 0x0504 - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 X2ApicOptOut; -/** Offset 0x0511 +/** Offset 0x0505 **/ - UINT8 UnusedUpdSpace11[6]; + UINT8 UnusedUpdSpace10[2]; -/** Offset 0x0517 +/** Offset 0x0507 **/ UINT8 ReservedFspmUpd[9]; } FSP_M_CONFIG; @@ -2356,51 +2352,51 @@ **/ typedef struct { -/** Offset 0x0520 +/** Offset 0x0510 **/ UINT32 Signature; -/** Offset 0x0524 - Skip external display device scanning +/** Offset 0x0514 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0525 - Generate BIOS Data ACPI Table +/** Offset 0x0515 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it $EN_DIS **/ UINT8 BdatEnable; -/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM +/** Offset 0x0516 - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 ScanExtGfxForLegacyOpRom; -/** Offset 0x0527 - Lock PCU Thermal Management registers +/** Offset 0x0517 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x0528 - DMI Max Link Speed +/** Offset 0x0518 - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 DmiMaxLinkSpeed; -/** Offset 0x0529 - DMI Equalization Phase 2 +/** Offset 0x0519 - DMI Equalization Phase 2 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method 0:Disable phase2, 1:Enable phase2, 2:Auto **/ UINT8 DmiGen3EqPh2Enable; -/** Offset 0x052A - DMI Gen3 Equalization Phase3 +/** Offset 0x051A - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2410,35 +2406,35 @@ **/ UINT8 DmiGen3EqPh3Method; -/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0. +/** Offset 0x051B - Phase2 EQ enable on the PEG 0:1:0. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg0Gen3EqPh2Enable; -/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1. +/** Offset 0x051C - Phase2 EQ enable on the PEG 0:1:1. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg1Gen3EqPh2Enable; -/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2. +/** Offset 0x051D - Phase2 EQ enable on the PEG 0:1:2. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg2Gen3EqPh2Enable; -/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3. +/** Offset 0x051E - Phase2 EQ enable on the PEG 0:1:3. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg3Gen3EqPh2Enable; -/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0. +/** Offset 0x051F - Phase3 EQ method on the PEG 0:1:0. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2448,7 +2444,7 @@ **/ UINT8 Peg0Gen3EqPh3Method; -/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1. +/** Offset 0x0520 - Phase3 EQ method on the PEG 0:1:1. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2458,7 +2454,7 @@ **/ UINT8 Peg1Gen3EqPh3Method; -/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2. +/** Offset 0x0521 - Phase3 EQ method on the PEG 0:1:2. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2468,7 +2464,7 @@ **/ UINT8 Peg2Gen3EqPh3Method; -/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3. +/** Offset 0x0522 - Phase3 EQ method on the PEG 0:1:3. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2478,14 +2474,14 @@ **/ UINT8 Peg3Gen3EqPh3Method; -/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming +/** Offset 0x0523 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 PegGen3ProgramStaticEq; -/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt +/** Offset 0x0524 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended @@ -2493,7 +2489,7 @@ **/ UINT8 Gen3SwEqAlwaysAttempt; -/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq +/** Offset 0x0525 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible @@ -2503,7 +2499,7 @@ **/ UINT8 Gen3SwEqNumberOfPresets; -/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq +/** Offset 0x0526 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default @@ -2511,7 +2507,7 @@ **/ UINT8 Gen3SwEqEnableVocTest; -/** Offset 0x0537 - PCIe Rx Compliance Testing Mode +/** Offset 0x0527 - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing @@ -2519,12 +2515,12 @@ **/ UINT8 PegRxCemTestingMode; -/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled +/** Offset 0x0528 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 **/ UINT8 PegRxCemLoopbackLane; -/** Offset 0x0539 - Generate PCIe BDAT Margin Table +/** Offset 0x0529 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data @@ -2532,7 +2528,7 @@ **/ UINT8 PegGenerateBdatMarginTable; -/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing +/** Offset 0x052A - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for @@ -2541,7 +2537,7 @@ **/ UINT8 PegRxCemNonProtocolAwareness; -/** Offset 0x053B - PCIe Override RxCTLE +/** Offset 0x052B - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified @@ -2549,7 +2545,7 @@ **/ UINT8 PegGen3RxCtleOverride; -/** Offset 0x053C - Rsvd +/** Offset 0x052C - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified @@ -2557,307 +2553,284 @@ **/ UINT8 PegGen3Rsvd; -/** Offset 0x053D - PEG Gen3 Root port preset values per lane +/** Offset 0x052D - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 PegGen3RootPortPreset[20]; -/** Offset 0x0551 - PEG Gen3 End port preset values per lane +/** Offset 0x0541 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 PegGen3EndPointPreset[20]; -/** Offset 0x0565 - PEG Gen3 End port Hint values per lane +/** Offset 0x0555 - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 PegGen3EndPointHint[20]; -/** Offset 0x0579 +/** Offset 0x0569 **/ - UINT8 UnusedUpdSpace12; + UINT8 UnusedUpdSpace11; -/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization +/** Offset 0x056A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default **/ UINT16 Gen3SwEqJitterDwellTime; -/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization +/** Offset 0x056C - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1. @warning Do not change from the default **/ UINT16 Gen3SwEqJitterErrorTarget; -/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization +/** Offset 0x056E - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000. @warning Do not change from the default **/ UINT16 Gen3SwEqVocDwellTime; -/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization +/** Offset 0x0570 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2. @warning Do not change from the default **/ UINT16 Gen3SwEqVocErrorTarget; -/** Offset 0x0582 - Panel Power Enable +/** Offset 0x0572 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 PanelPowerEnable; -/** Offset 0x0583 - BdatTestType +/** Offset 0x0573 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. 0:Rank Margin Tool, 1:Margin2D **/ UINT8 BdatTestType; -/** Offset 0x0584 - Disable VT-d +/** Offset 0x0574 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x0585 +/** Offset 0x0575 **/ - UINT8 UnusedUpdSpace13; + UINT8 UnusedUpdSpace12; -/** Offset 0x0586 - Delta T12 Power Cycle Delay required in ms +/** Offset 0x0576 - Delta T12 Power Cycle Delay required in ms Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay **/ UINT16 DeltaT12PowerCycleDelayPreMem; -/** Offset 0x0588 - SaPreMemTestRsvd +/** Offset 0x0578 - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ UINT8 SaPreMemTestRsvd[9]; -/** Offset 0x0591 +/** Offset 0x0581 **/ - UINT8 UnusedUpdSpace14; + UINT8 UnusedUpdSpace13; -/** Offset 0x0592 - TotalFlashSize +/** Offset 0x0582 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable **/ UINT16 TotalFlashSize; -/** Offset 0x0594 - BiosSize +/** Offset 0x0584 - BiosSize Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable **/ UINT16 BiosSize; -/** Offset 0x0596 - TxtAcheckRequest +/** Offset 0x0586 - TxtAcheckRequest Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. $EN_DIS **/ UINT8 TxtAcheckRequest; -/** Offset 0x0597 - SecurityTestRsvd +/** Offset 0x0587 - SecurityTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ UINT8 SecurityTestRsvd[3]; -/** Offset 0x059A - PCH Dci Enable - Enable/disable PCH Dci. - $EN_DIS -**/ - UINT8 PchDciEn; - -/** Offset 0x059B - Smbus dynamic power gating +/** Offset 0x058A - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x059C - Disable and Lock Watch Dog Register +/** Offset 0x058B - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x059D - SMBUS SPD Write Disable +/** Offset 0x058C - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x059E - ChipsetInit HECI message - Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. - If disabled, it prevents from sending ChipsetInit HECI message. - $EN_DIS -**/ - UINT8 ChipsetInitMessage; - -/** Offset 0x059F - Bypass ChipsetInit sync reset. - 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message. - $EN_DIS -**/ - UINT8 BypassPhySyncReset; - -/** Offset 0x05A0 - ReservedPchPreMemTest +/** Offset 0x058D - ReservedPchPreMemTest Reserved for Pch Pre-Mem Test $EN_DIS **/ UINT8 ReservedPchPreMemTest[16]; -/** Offset 0x05B0 - Force ME DID Init Status +/** Offset 0x059D - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x05B1 - CPU Replaced Polling Disable +/** Offset 0x059E - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x05B2 - ME DID Message +/** Offset 0x059F - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent) $EN_DIS **/ UINT8 SendDidMsg; -/** Offset 0x05B3 - Check HECI message before send +/** Offset 0x05A0 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x05B4 - Skip MBP HOB +/** Offset 0x05A1 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x05B5 - HECI2 Interface Communication +/** Offset 0x05A2 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x05B6 - Enable KT device +/** Offset 0x05A3 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x05B7 - tRd2RdSG +/** Offset 0x05A4 - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tRd2RdSG; -/** Offset 0x05B8 - tRd2RdDG +/** Offset 0x05A5 - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDG; -/** Offset 0x05B9 - tRd2RdDR +/** Offset 0x05A6 - tRd2RdDR Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDR; -/** Offset 0x05BA - tRd2RdDD +/** Offset 0x05A7 - tRd2RdDD Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDD; -/** Offset 0x05BB - tWr2RdSG +/** Offset 0x05A8 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. **/ UINT8 tWr2RdSG; -/** Offset 0x05BC - tWr2RdDG +/** Offset 0x05A9 - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDG; -/** Offset 0x05BD - tWr2RdDR +/** Offset 0x05AA - tWr2RdDR Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDR; -/** Offset 0x05BE - tWr2RdDD +/** Offset 0x05AB - tWr2RdDD Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDD; -/** Offset 0x05BF - tWr2WrSG +/** Offset 0x05AC - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tWr2WrSG; -/** Offset 0x05C0 - tWr2WrDG +/** Offset 0x05AD - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDG; -/** Offset 0x05C1 - tWr2WrDR +/** Offset 0x05AE - tWr2WrDR Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDR; -/** Offset 0x05C2 - tWr2WrDD +/** Offset 0x05AF - tWr2WrDD Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDD; -/** Offset 0x05C3 - tRd2WrSG +/** Offset 0x05B0 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tRd2WrSG; -/** Offset 0x05C4 - tRd2WrDG +/** Offset 0x05B1 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDG; -/** Offset 0x05C5 - tRd2WrDR +/** Offset 0x05B2 - tRd2WrDR Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDR; -/** Offset 0x05C6 - tRd2WrDD +/** Offset 0x05B3 - tRd2WrDD Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDD; -/** Offset 0x05C7 - tRRD_L +/** Offset 0x05B4 - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 **/ UINT8 tRRD_L; -/** Offset 0x05C8 - tRRD_S +/** Offset 0x05B5 - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31 **/ UINT8 tRRD_S; -/** Offset 0x05C9 - tWTR_L +/** Offset 0x05B6 - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60 **/ UINT8 tWTR_L; -/** Offset 0x05CA - tWTR_S +/** Offset 0x05B7 - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28 **/ UINT8 tWTR_S; -/** Offset 0x05CB -**/ - UINT8 UnusedUpdSpace15[1]; - -/** Offset 0x05CC +/** Offset 0x05B8 **/ UINT8 ReservedFspmTestUpd[4]; } FSP_M_TEST_CONFIG; @@ -2878,15 +2851,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0520 +/** Offset 0x0510 **/ FSP_M_TEST_CONFIG FspmTestConfig; -/** Offset 0x05D0 -**/ - UINT8 UnusedUpdSpace16[4]; - -/** Offset 0x05D4 +/** Offset 0x05BC **/ UINT32 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index 411bf90..c595fd3 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -689,81 +689,58 @@ **/ UINT8 ReservedCpuPostMemProduction[8]; -/** Offset 0x0184 - Enable Intel HD Audio (Azalia) - Enable/disable Azalia controller. - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0185 - Enable HD Audio DSP +/** Offset 0x0184 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x0186 - Select HDAudio IoBuffer Ownership - Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / - I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link - owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 - of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports - own all the I/O buffers. - 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports -**/ - UINT8 PchHdaIoBufferOwnership; - -/** Offset 0x0187 - Configure CLKSRC Number - Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid - clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for - port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkSrcNumber[24]; - -/** Offset 0x019F - Force Disable clock - Disables clock even if link is inactive default value is 0 -**/ - UINT8 PcieRpForceClkDisableWhenRpDisable[24]; - -/** Offset 0x01B7 - Enable CIO2 Controller - Enable/disable SKYCAM CIO2 Controller. - $EN_DIS -**/ - UINT8 PchCio2Enable; - -/** Offset 0x01B8 - SPI0 Chip Select Polarity +/** Offset 0x0185 - SPI0 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi0CsPolarity[2]; -/** Offset 0x01BA - SPI1 Chip Select Polarity +/** Offset 0x0187 - SPI1 Chip Select Polarity Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, 1:PchSerialIoCsActiveHigh **/ UINT8 SerialIoSpi1CsPolarity[2]; -/** Offset 0x01BC - SPI0 Chip Select Enable +/** Offset 0x0189 - SPI2 Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, + 1:PchSerialIoCsActiveHigh +**/ + UINT8 SerialIoSpi2CsPolarity[2]; + +/** Offset 0x018B - SPI0 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi0CsEnable[2]; -/** Offset 0x01BE - SPI1 Chip Select Enable +/** Offset 0x018D - SPI1 Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpi1CsEnable[2]; -/** Offset 0x01C0 - SPIn Device Mode +/** Offset 0x018F - SPI2 Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpi2CsEnable[2]; + +/** Offset 0x0191 - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ - UINT8 SerialIoSpiMode[2]; + UINT8 SerialIoSpiMode[3]; -/** Offset 0x01C2 - SPIn Default Chip Select Output +/** Offset 0x0194 - SPIn Default Chip Select Output Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1 **/ - UINT8 SerialIoSpiDefaultCsOutput[2]; + UINT8 SerialIoSpiDefaultCsOutput[3]; -/** Offset 0x01C4 - PCH SerialIo I2C Pads Termination +/** Offset 0x0197 - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 @@ -771,1489 +748,1580 @@ **/ UINT8 PchSerialIoI2cPadsTermination[6]; -/** Offset 0x01CA - I2Cn Device Mode +/** Offset 0x019D - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[6]; -/** Offset 0x01D0 - UARTn Device Mode +/** Offset 0x01A3 - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[3]; -/** Offset 0x01D3 +/** Offset 0x01A6 **/ - UINT8 UnusedUpdSpace8[1]; + UINT8 UnusedUpdSpace8[2]; -/** Offset 0x01D4 - Default BaudRate for each Serial IO UART +/** Offset 0x01A8 - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 **/ UINT32 SerialIoUartBaudRate[3]; -/** Offset 0x01E0 - Default ParityType for each Serial IO UART +/** Offset 0x01B4 - Default ParityType for each Serial IO UART Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartParity[3]; -/** Offset 0x01E3 - Default DataBits for each Serial IO UART +/** Offset 0x01B7 - Default DataBits for each Serial IO UART Set default word length. 0: Default, 5,6,7,8 **/ UINT8 SerialIoUartDataBits[3]; -/** Offset 0x01E6 - Default StopBits for each Serial IO UART +/** Offset 0x01BA - Default StopBits for each Serial IO UART Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartStopBits[3]; -/** Offset 0x01E9 - Power Gating mode for each Serial IO UART that works in COM mode +/** Offset 0x01BD - Power Gating mode for each Serial IO UART that works in COM mode Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto **/ UINT8 SerialIoUartPowerGating[3]; -/** Offset 0x01EC - Enable Dma for each Serial IO UART that supports it +/** Offset 0x01C0 - Enable Dma for each Serial IO UART that supports it Set DMA/PIO mode. 0: Disabled, 1: Enabled **/ UINT8 SerialIoUartDmaEnable[3]; -/** Offset 0x01EF - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x01C3 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[3]; -/** Offset 0x01F2 +/** Offset 0x01C6 **/ UINT8 UnusedUpdSpace9[2]; -/** Offset 0x01F4 - SerialIoUartRxPinMux +/** Offset 0x01C8 - SerialIoUartRxPinMux Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values. **/ UINT32 SerialIoUartRxPinMux[3]; -/** Offset 0x0200 - SerialIoUartTxPinMux +/** Offset 0x01D4 - SerialIoUartTxPinMux Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values. **/ UINT32 SerialIoUartTxPinMux[3]; -/** Offset 0x020C - SerialIoUartRtsPinMux +/** Offset 0x01E0 - SerialIoUartRtsPinMux Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values. **/ UINT32 SerialIoUartRtsPinMux[3]; -/** Offset 0x0218 - SerialIoUartCtsPinMux +/** Offset 0x01EC - SerialIoUartCtsPinMux Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values. **/ UINT32 SerialIoUartCtsPinMux[3]; -/** Offset 0x0224 - UART Number For Debug Purpose +/** Offset 0x01F8 - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:UART0, 1:UART1, 2:UART2 **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x0225 - Enable eMMC Controller +/** Offset 0x01F9 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[3]; + +/** Offset 0x01FC - Enable eMMC Controller Enable/disable eMMC Controller. $EN_DIS **/ UINT8 ScsEmmcEnabled; -/** Offset 0x0226 - Enable eMMC HS400 Mode +/** Offset 0x01FD - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. $EN_DIS **/ UINT8 ScsEmmcHs400Enabled; -/** Offset 0x0227 - Enable SdCard Controller +/** Offset 0x01FE - Enable SdCard Controller Enable/disable SD Card Controller. $EN_DIS **/ UINT8 ScsSdCardEnabled; -/** Offset 0x0228 - Enable PCH ISH Controller - Enable/disable ISH Controller. - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x0229 - Show SPI controller +/** Offset 0x01FF - Show SPI controller Enable/disable to show SPI controller. $EN_DIS **/ UINT8 ShowSpiController; -/** Offset 0x022A - Flash Configuration Lock Down - Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. - $EN_DIS -**/ - UINT8 SpiFlashCfgLockDown; - -/** Offset 0x022B - Enable SATA SALP Support +/** Offset 0x0200 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. $EN_DIS **/ UINT8 SataSalpSupport; -/** Offset 0x022C - Enable SATA ports +/** Offset 0x0201 - Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsEnable[8]; -/** Offset 0x0234 - Enable SATA DEVSLP Feature +/** Offset 0x0209 - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x023C - Enable USB2 ports +/** Offset 0x0211 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x024C - Enable USB3 ports +/** Offset 0x0221 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x0256 - Enable xDCI controller +/** Offset 0x022B - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x0257 - Enable XHCI SSIC Enable - Enable/disable XHCI SSIC port. - $EN_DIS +/** Offset 0x022C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ - UINT8 SsicPortEnable; + UINT32 DevIntConfigPtr; -/** Offset 0x0258 - Number of DevIntConfig Entry +/** Offset 0x0230 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x0259 -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x025C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x0260 - PIRQx to IRQx Map Config +/** Offset 0x0231 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. **/ UINT8 PxRcConfig[8]; -/** Offset 0x0268 - Select GPIO IRQ Route +/** Offset 0x0239 - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x0269 - Select SciIrqSelect +/** Offset 0x023A - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x026A - Select TcoIrqSelect +/** Offset 0x023B - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x026B - Enable/Disable Tco IRQ +/** Offset 0x023C - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x026C - PCH HDA Verb Table Entry Number +/** Offset 0x023D - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x026D +/** Offset 0x023E **/ - UINT8 UnusedUpdSpace11[3]; + UINT8 UnusedUpdSpace10[2]; -/** Offset 0x0270 - PCH HDA Verb Table Pointer +/** Offset 0x0240 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT32 PchHdaVerbTablePtr; -/** Offset 0x0274 - Enable SATA +/** Offset 0x0244 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x0245 - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x0275 - SATA Mode +/** Offset 0x0246 - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x0276 - USB Per Port HS Preemphasis Bias +/** Offset 0x0247 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2AfePetxiset[16]; -/** Offset 0x0286 - USB Per Port HS Transmitter Bias +/** Offset 0x0257 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2AfeTxiset[16]; -/** Offset 0x0296 - USB Per Port HS Transmitter Emphasis +/** Offset 0x0267 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2AfePredeemp[16]; -/** Offset 0x02A6 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x0277 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2AfePehalfbit[16]; -/** Offset 0x02B6 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x0287 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x02C0 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x0291 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x02CA - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x029B - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x02D4 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x02A5 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x02DE - Enable LAN +/** Offset 0x02AF - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x02DF - Delay USB PDO Programming - Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0: - disable, 1: enable +/** Offset 0x02B0 - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ - UINT8 DelayUsbPdoProgramming; + UINT8 PchHdaAudioLinkHda; -/** Offset 0x02E0 - Trace Hub Memory Base +/** Offset 0x02B1 - Enable HD Audio DMIC0 Link + Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic0; + +/** Offset 0x02B2 - Enable HD Audio DMIC1 Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic1; + +/** Offset 0x02B3 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp0; + +/** Offset 0x02B4 - Enable HD Audio SSP1 Link + Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp1; + +/** Offset 0x02B5 - Enable HD Audio SSP2 Link + Enable/disable HD Audio SSP2/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp2; + +/** Offset 0x02B6 - Enable HD Audio SoundWire#1 Link + Enable/disable HD Audio SNDW1 link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw1; + +/** Offset 0x02B7 - Enable HD Audio SoundWire#2 Link + Enable/disable HD Audio SNDW2 link. Muxed with SSP1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw2; + +/** Offset 0x02B8 - Enable HD Audio SoundWire#3 Link + Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw3; + +/** Offset 0x02B9 - Enable HD Audio SoundWire#4 Link + Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw4; + +/** Offset 0x02BA - Soundwire Clock Buffer GPIO RCOMP Setting + 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. + $EN_DIS +**/ + UINT8 PchHdaSndwBufferRcomp; + +/** Offset 0x02BB +**/ + UINT8 UnusedUpdSpace11; + +/** Offset 0x02BC - PTM for PCIE RP Mask + Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpPtmMask; + +/** Offset 0x02C0 - DPC for PCIE RP Mask + Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpDpcMask; + +/** Offset 0x02C4 - DPC Extensions PCIE RP Mask + Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpDpcExtensionsMask; + +/** Offset 0x02C8 - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x02C9 +**/ + UINT8 UnusedUpdSpace12[3]; + +/** Offset 0x02CC - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounce; + +/** Offset 0x02D0 - PCH eSPI Master and Slave BME enabled + PCH eSPI Master and Slave BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeMasterSlaveEnabled; + +/** Offset 0x02D1 - PCH SATA use RST Legacy OROM + Use PCH SATA RST Legacy OROM when CSM is Enabled + $EN_DIS +**/ + UINT8 SataRstLegacyOrom; + +/** Offset 0x02D2 +**/ + UINT8 UnusedUpdSpace13[2]; + +/** Offset 0x02D4 - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly. **/ UINT32 TraceHubMemBase; -/** Offset 0x02E4 - Enable PCIE RP CLKREQ Support - Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for - each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqSupport[24]; - -/** Offset 0x02FC - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can - be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 PcieRpClkReqNumber[24]; - -/** Offset 0x0314 - Enable CPU PCIE RP CLKREQ Support - Enable/disable CPU PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte - for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 CpuPcieRpClkReqSupport[4]; - -/** Offset 0x0318 - Configure CPU PCIE CLKREQ Number - Configure CPU Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary - can be between 0-3. One byte for each port, byte0 for port1, byte1 for port2, and so on. -**/ - UINT8 CpuPcieRpClkReqNumber[4]; - -/** Offset 0x031C - Enable SkyCam PortA Termination override - Enable/disable PortA Termination override. +/** Offset 0x02D8 - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix $EN_DIS **/ - UINT8 PchSkyCamPortATermOvrEnable; + UINT8 PmcDbgMsgEn; -/** Offset 0x031D - Enable SkyCam PortB Termination override - Enable/disable PortB Termination override. +/** Offset 0x02D9 +**/ + UINT8 UnusedUpdSpace14[3]; + +/** Offset 0x02DC - Pointer of ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x02E0 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x02E4 - Enable Ufs Controller + Enable/disable Ufs 2.0 Controller. $EN_DIS **/ - UINT8 PchSkyCamPortBTermOvrEnable; + UINT8 ScsUfsEnabled; -/** Offset 0x031E - Enable SkyCam PortC Termination override - Enable/disable PortC Termination override. +/** Offset 0x02E5 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x02E6 - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ - UINT8 PchSkyCamPortCTermOvrEnable; + UINT8 CnviBtCore; -/** Offset 0x031F - Enable SkyCam PortD Termination override - Enable/disable PortD Termination override. +/** Offset 0x02E7 - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ - UINT8 PchSkyCamPortDTermOvrEnable; + UINT8 CnviBtAudioOffload; -/** Offset 0x0320 - Enable SkyCam PortA Clk Trim - Enable/disable PortA Clk Trim. +/** Offset 0x02E8 - SdCard power enable polarity + Choose SD_PWREN# polarity + 0: Active low, 1: Active high +**/ + UINT8 SdCardPowerEnableActiveHigh; + +/** Offset 0x02E9 - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG $EN_DIS **/ - UINT8 PchSkyCamPortATrimEnable; + UINT8 PchUsb2PhySusPgEnable; -/** Offset 0x0321 - Enable SkyCam PortB Clk Trim - Enable/disable PortB Clk Trim. +/** Offset 0x02EA - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins $EN_DIS **/ - UINT8 PchSkyCamPortBTrimEnable; + UINT8 PchUsbOverCurrentEnable; -/** Offset 0x0322 - Enable SkyCam PortC Clk Trim - Enable/disable PortC Clk Trim. +/** Offset 0x02EB - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr $EN_DIS **/ - UINT8 PchSkyCamPortCTrimEnable; + UINT8 PchEspiLgmrEnable; -/** Offset 0x0323 - Enable SkyCam PortD Clk Trim - Enable/disable PortD Clk Trim. +/** Offset 0x02EC - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ - UINT8 PchSkyCamPortDTrimEnable; + UINT8 PchHotEnable; -/** Offset 0x0324 - Enable SkyCam PortA Ctle - Enable/disable PortA Ctle. +/** Offset 0x02ED - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ - UINT8 PchSkyCamPortACtleEnable; + UINT8 SataLedEnable; -/** Offset 0x0325 - Enable SkyCam PortB Ctle - Enable/disable PortB Ctle. +/** Offset 0x02EE - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ - UINT8 PchSkyCamPortBCtleEnable; + UINT8 PchPmVrAlert; -/** Offset 0x0326 - Enable SkyCam PortCD Ctle - Enable/disable PortCD Ctle. +/** Offset 0x02EF - SLP_S0 VM Dynamic Control + SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable $EN_DIS **/ - UINT8 PchSkyCamPortCDCtleEnable; + UINT8 PchPmSlpS0VmRuntimeControl; -/** Offset 0x0327 - Enable SkyCam PortA Ctle Cap Value - Enable/disable PortA Ctle Cap Value. -**/ - UINT8 PchSkyCamPortACtleCapValue; - -/** Offset 0x0328 - Enable SkyCam PortB Ctle Cap Value - Enable/disable PortB Ctle Cap Value. -**/ - UINT8 PchSkyCamPortBCtleCapValue; - -/** Offset 0x0329 - Enable SkyCam PortCD Ctle Cap Value - Enable/disable PortCD Ctle Cap Value. -**/ - UINT8 PchSkyCamPortCDCtleCapValue; - -/** Offset 0x032A - Enable SkyCam PortA Ctle Res Value - Enable/disable PortA Ctle Res Value. -**/ - UINT8 PchSkyCamPortACtleResValue; - -/** Offset 0x032B - Enable SkyCam PortB Ctle Res Value - Enable/disable PortB Ctle Res Value. -**/ - UINT8 PchSkyCamPortBCtleResValue; - -/** Offset 0x032C - Enable SkyCam PortCD Ctle Res Value - Enable/disable PortCD Ctle Res Value. -**/ - UINT8 PchSkyCamPortCDCtleResValue; - -/** Offset 0x032D - Enable SkyCam PortA Clk Trim Value - Enable/disable PortA Clk Trim Value. -**/ - UINT8 PchSkyCamPortAClkTrimValue; - -/** Offset 0x032E - Enable SkyCam PortB Clk Trim Value - Enable/disable PortB Clk Trim Value. -**/ - UINT8 PchSkyCamPortBClkTrimValue; - -/** Offset 0x032F - Enable SkyCam PortC Clk Trim Value - Enable/disable PortC Clk Trim Value. -**/ - UINT8 PchSkyCamPortCClkTrimValue; - -/** Offset 0x0330 - Enable SkyCam PortD Clk Trim Value - Enable/disable PortD Clk Trim Value. -**/ - UINT8 PchSkyCamPortDClkTrimValue; - -/** Offset 0x0331 -**/ - UINT8 UnusedUpdSpace12; - -/** Offset 0x0332 - Enable SkyCam Port A Data Trim Value - Enable/disable Port A Data Trim Value. -**/ - UINT16 PchSkyCamPortADataTrimValue; - -/** Offset 0x0334 - Enable SkyCam Port B Data Trim Value - Enable/disable Port B Data Trim Value. -**/ - UINT16 PchSkyCamPortBDataTrimValue; - -/** Offset 0x0336 - Enable SkyCam C/D Data Trim Value - Enable/disable C/D Data Trim Value. -**/ - UINT16 PchSkyCamPortCDDataTrimValue; - -/** Offset 0x0338 - Enable DMI ASPM - ASPM on PCH side of the DMI Link. +/** Offset 0x02F0 - SLP_S0 VM 0.70V Support + SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable $EN_DIS **/ - UINT8 PchDmiAspm; + UINT8 PchPmSlpS0Vm070VSupport; -/** Offset 0x0339 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. +/** Offset 0x02F1 - SLP_S0 VM 0.75V Support + SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable $EN_DIS **/ - UINT8 PchPwrOptEnable; + UINT8 PchPmSlpS0Vm075VSupport; -/** Offset 0x033A - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. +/** Offset 0x02F2 - PCH PCIe root port connection type + 0: built-in device, 1:slot **/ - UINT8 PchWriteProtectionEnable[5]; + UINT8 PcieRpSlotImplemented[24]; -/** Offset 0x033F - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. +/** Offset 0x030A - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used **/ - UINT8 PchReadProtectionEnable[5]; + UINT8 PcieClkSrcUsage[16]; -/** Offset 0x0344 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. +/** Offset 0x031A - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc **/ - UINT16 PchProtectedRangeLimit[5]; + UINT8 PcieClkSrcClkReq[16]; -/** Offset 0x034E - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +/** Offset 0x032A - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability **/ - UINT16 PchProtectedRangeBase[5]; + UINT8 PcieRpAcsEnabled[24]; -/** Offset 0x0358 - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x0359 - IO Buffer Voltage - I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V. -**/ - UINT8 PchHdaIoBufferVoltage; - -/** Offset 0x035A - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. -**/ - UINT8 PchHdaVcType; - -/** Offset 0x035B - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz. -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x035C - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x035D - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x035E - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x035F - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x0360 - Enable PCH Io Apic - Set to 1 if BDF value is valid. - $EN_DIS -**/ - UINT8 PchIoApicBdfValid; - -/** Offset 0x0361 - PCH Io Apic Bus Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. -**/ - UINT8 PchIoApicBusNumber; - -/** Offset 0x0362 - PCH Io Apic Device Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. -**/ - UINT8 PchIoApicDeviceNumber; - -/** Offset 0x0363 - PCH Io Apic Function Number - Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. -**/ - UINT8 PchIoApicFunctionNumber; - -/** Offset 0x0364 - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x0365 - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x0366 - PCH Io Apic Range Select - Define address bits 19:12 for the IOxAPIC range. Default is 0. -**/ - UINT8 PchIoApicRangeSelect; - -/** Offset 0x0367 - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x0368 - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x0369 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x036A - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x036B - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x036C - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x036D - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x036E - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x036F - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x0370 - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x0371 - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x0372 - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x0373 - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x0374 - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x0375 - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x0376 - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x0377 - Enable PCH Lan use CLKREQ for GbE power management - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanK1OffEnable; - -/** Offset 0x0378 - Indicate whether dedicated CLKREQ# is supported - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanClkReqSupported; - -/** Offset 0x0379 - CLKREQ# used by GbE - Valid if ClkReqSupported is TRUE. -**/ - UINT8 PchLanClkReqNumber; - -/** Offset 0x037A - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x037B - Enable LOCKDOWN SPI Eiss - Enable InSMM.STS (EISS) in SPI. - $EN_DIS -**/ - UINT8 PchLockDownSpiEiss; - -/** Offset 0x037C - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x037D - PCH Legacy IO Low Latency Enable - todo - $EN_DIS -**/ - UINT8 PchLegacyIoLowLatency; - -/** Offset 0x037E - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x0396 - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x03AE - Enable PCIE RP Ext Sync - Indicate whether the extended synch is enabled. -**/ - UINT8 PcieRpExtSync[24]; - -/** Offset 0x03C6 - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x03DE - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x03F6 - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x040E - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x0426 - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x043E - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x0456 - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x046E - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x0486 - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x049E - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x04B6 - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x04CE - PCIE RP Device Reset Pad Active High - Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad. -**/ - UINT8 PcieRpDeviceResetPadActiveHigh[24]; - -/** Offset 0x04E6 - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x04FE - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; - 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x0516 - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x052E - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x0546 -**/ - UINT8 UnusedUpdSpace13[2]; - -/** Offset 0x0548 - PCIE RP Device Reset Pad - The PCH pin assigned to device PERST# signal if available, zero otherwise. See - also DeviceResetPadActiveHigh. -**/ - UINT32 PcieRpDeviceResetPad[24]; - -/** Offset 0x05A8 - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x05C0 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x05D8 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x05F0 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x0608 - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x0620 - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x0638 - PCIE RP Clock Power Management +/** Offset 0x0342 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[24]; -/** Offset 0x0650 - PCIE RP Detect Timeout Ms +/** Offset 0x035A - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[24]; -/** Offset 0x0680 - PCIE Sw Eq CoeffList Cm +/** Offset 0x038A - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x038B - SlpS0WithGbeSupport + Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping + CPU and 1 for all other CPUs. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 SlpS0WithGbeSupport; + +/** Offset 0x038C - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x038D - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x0392 - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x0397 +**/ + UINT8 UnusedUpdSpace15[1]; + +/** Offset 0x0398 - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x03A2 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x03AC - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x03AD - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x03AE - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x03AF - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x03B0 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. + 0: 2T, 1: 1T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x03B1 - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x03B2 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x03B3 - USB LFPS Filter selection + For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, + 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. +**/ + UINT8 PchUsbHsioFilterSel[10]; + +/** Offset 0x03BD - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x03BE - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x03BF - Enable PCH ISH SPI GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshSpiGpioAssign; + +/** Offset 0x03C0 - Enable PCH ISH UART0 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshUart0GpioAssign; + +/** Offset 0x03C1 - Enable PCH ISH UART1 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshUart1GpioAssign; + +/** Offset 0x03C2 - Enable PCH ISH I2C0 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshI2c0GpioAssign; + +/** Offset 0x03C3 - Enable PCH ISH I2C1 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshI2c1GpioAssign; + +/** Offset 0x03C4 - Enable PCH ISH I2C2 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshI2c2GpioAssign; + +/** Offset 0x03C5 - Enable PCH ISH GP_0 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp0GpioAssign; + +/** Offset 0x03C6 - Enable PCH ISH GP_1 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp1GpioAssign; + +/** Offset 0x03C7 - Enable PCH ISH GP_2 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp2GpioAssign; + +/** Offset 0x03C8 - Enable PCH ISH GP_3 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp3GpioAssign; + +/** Offset 0x03C9 - Enable PCH ISH GP_4 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp4GpioAssign; + +/** Offset 0x03CA - Enable PCH ISH GP_5 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp5GpioAssign; + +/** Offset 0x03CB - Enable PCH ISH GP_6 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp6GpioAssign; + +/** Offset 0x03CC - Enable PCH ISH GP_7 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp7GpioAssign; + +/** Offset 0x03CD - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x03CE - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x03CF - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x03D0 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x03D1 - RTC CMOS MEMORY LOCK + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 PchLockDownRtcMemoryLock; + +/** Offset 0x03D2 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[24]; + +/** Offset 0x03EA - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[24]; + +/** Offset 0x0402 - Enable PCIE RP Ext Sync + Indicate whether the extended synch is enabled. +**/ + UINT8 PcieRpExtSync[24]; + +/** Offset 0x041A - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[24]; + +/** Offset 0x0432 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[24]; + +/** Offset 0x044A - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[24]; + +/** Offset 0x0462 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[24]; + +/** Offset 0x047A - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[24]; + +/** Offset 0x0492 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[24]; + +/** Offset 0x04AA - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[24]; + +/** Offset 0x04C2 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[24]; + +/** Offset 0x04DA - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[24]; + +/** Offset 0x04F2 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[24]; + +/** Offset 0x050A - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[24]; + +/** Offset 0x0522 - PCH USB3 RX HSIO Tuning parameters + Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for + controlling the input offset +**/ + UINT8 PchUsbHsioRxTuningParameters[10]; + +/** Offset 0x052C - PCH USB3 HSIO Rx Tuning Enable + Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, + 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable +**/ + UINT8 PchUsbHsioRxTuningEnable[10]; + +/** Offset 0x0536 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCH_PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[24]; + +/** Offset 0x054E - PCIE RP Gen3 Equalization Phase Method + PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 PcieRpGen3EqPh3Method[24]; + +/** Offset 0x0566 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[24]; + +/** Offset 0x057E - PCIE RP Completion Timeout + The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[24]; + +/** Offset 0x0596 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[24]; + +/** Offset 0x05AE - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[24]; + +/** Offset 0x05C6 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[24]; + +/** Offset 0x05DE - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[24]; + +/** Offset 0x05F6 - PCIE Eq Ph3 Lane Param Cm + PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. +**/ + UINT8 PcieEqPh3LaneParamCm[24]; + +/** Offset 0x060E - PCIE Eq Ph3 Lane Param Cp + PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. +**/ + UINT8 PcieEqPh3LaneParamCp[24]; + +/** Offset 0x0626 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. Coefficient C-1. **/ UINT8 PcieSwEqCoeffListCm[5]; -/** Offset 0x0685 - PCIE Sw Eq CoeffList Cp +/** Offset 0x062B - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. Coefficient C+1. **/ UINT8 PcieSwEqCoeffListCp[5]; -/** Offset 0x068A - PCIE Disable RootPort Clock Gating +/** Offset 0x0630 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieDisableRootPortClockGating; -/** Offset 0x068B - PCIE Enable Peer Memory Write +/** Offset 0x0631 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite; -/** Offset 0x068C - PCIE Allow No Ltr Icc PLL Shutdown - Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable - or leaving untouched. - $EN_DIS -**/ - UINT8 PcieAllowNoLtrIccPllShutdown; - -/** Offset 0x068D - PCIE Compliance Test Mode +/** Offset 0x0632 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x068E - PCIE Rp Function Swap +/** Offset 0x0633 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x068F - PCH Pm PME_B0_S5_DIS +/** Offset 0x0634 - Teton Glacier Cycle Router + Specify to which cycle router Teton Glacier is connected, it is valid only when + Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system +**/ + UINT8 TetonGlacierCR; + +/** Offset 0x0635 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0690 - PCH Pm Slp S0 Voltage Margining Enable - Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. +/** Offset 0x0636 - PCIE IMR + Enables Isolated Memory Region for PCIe. $EN_DIS **/ - UINT8 PchPmSlpS0VmEnable; + UINT8 PcieRpImrEnabled; -/** Offset 0x0691 - PCH Pm Wol Enable Override +/** Offset 0x0637 - PCIE IMR port number + Selects PCIE root port number for IMR feature. +**/ + UINT8 PcieRpImrSelection; + +/** Offset 0x0638 - Teton Glacier Detection and Configuration Mode + Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Static + Configuration 2: Dynamic Configuration. Default is 0: Disabled + 0: Disabled, 1: Static Configuration, 2: Dynamic Configuration +**/ + UINT8 TetonGlacierMode; + +/** Offset 0x0639 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x0692 - PCH Pm Pcie Wake From DeepSx +/** Offset 0x063A - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x0693 - PCH Pm WoW lan Enable +/** Offset 0x063B - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x0694 - PCH Pm WoW lan DeepSx Enable +/** Offset 0x063C - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x0695 - PCH Pm Lan Wake From DeepSx +/** Offset 0x063D - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x0696 - PCH Pm Deep Sx Pol +/** Offset 0x063E - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x0697 - PCH Pm Slp S3 Min Assert +/** Offset 0x063F - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0698 - PCH Pm Slp S4 Min Assert +/** Offset 0x0640 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0699 - PCH Pm Slp Sus Min Assert +/** Offset 0x0641 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x069A - PCH Pm Slp A Min Assert +/** Offset 0x0642 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x069B - PCH Pm Lpc Clock Run +/** Offset 0x0643 - SLP_S0# Override + Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' + will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion + when debug is enabled. \n + Note: This BIOS option should keep 'Auto', other options are intended for advanced + configuration only. + 0:Disabled, 1:Enabled, 2:Auto +**/ + UINT8 SlpS0Override; + +/** Offset 0x0644 - S0ix Override Settings + Select 'Auto', it will be auto-configured according to probe type. 'No Change' will + keep PMC default settings. Or select the desired debug probe type for S0ix Override + settings.\n + Reminder: DCI OOB (aka BSSB) uses CCA probe.\n + Note: This BIOS option should keep 'Auto', other options are intended for advanced + configuration only. + 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto +**/ + UINT8 SlpS0DisQForDebug; + +/** Offset 0x0645 - USB Overcurrent Override for DbC + This option overrides USB Over Current enablement state that USB OC will be disabled + after enabling this option. Enable when DbC is used to avoid signaling conflicts. + $EN_DIS +**/ + UINT8 PchEnableDbcObs; + +/** Offset 0x0646 - PCH Legacy IO Low Latency Enable + Set to enable low latency of legacy IO. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 PchLegacyIoLowLatency; + +/** Offset 0x0647 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. + Default value is Disabled $EN_DIS **/ UINT8 PchPmLpcClockRun; -/** Offset 0x069C - PCH Pm Slp Strch Sus Up +/** Offset 0x0648 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x069D - PCH Pm Slp Lan Low Dc +/** Offset 0x0649 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x069E - PCH Pm Pwr Btn Override Period +/** Offset 0x064A - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x069F - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x064B - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x06A0 - PCH Pm Disable Native Power Button +/** Offset 0x064C - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x06A1 - PCH Pm Slp S0 Enable +/** Offset 0x064D - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. $EN_DIS **/ UINT8 PchPmSlpS0Enable; -/** Offset 0x06A2 - PCH Pm ME_WAKE_STS +/** Offset 0x064E - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x06A3 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x064F - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x06A4 - PCH Pm Reset Power Cycle Duration +/** Offset 0x0650 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x06A5 - PCH Port 61h Config Enable/Disable - Used for the emulation feature for Port61h read. The port is trapped and the SMI - handler will toggle bit4 according to the handler's internal state. - $EN_DIS +/** Offset 0x0651 - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. **/ - UINT8 PchPort61hEnable; + UINT8 PchPmPciePllSsc; -/** Offset 0x06A6 - PCH Sata Pwr Opt Enable +/** Offset 0x0652 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x06A7 - PCH Sata eSATA Speed Limit +/** Offset 0x0653 - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x06A8 - PCH Sata Speed Limit +/** Offset 0x0654 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x06A9 - Enable SATA Port HotPlug +/** Offset 0x0655 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x06B1 - Enable SATA Port Interlock Sw +/** Offset 0x065D - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x06B9 - Enable SATA Port External +/** Offset 0x0665 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x06C1 - Enable SATA Port SpinUp +/** Offset 0x066D - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x06C9 - Enable SATA Port Solid State Drive +/** Offset 0x0675 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x06D1 - Enable SATA Port Enable Dito Config +/** Offset 0x067D - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x06D9 - Enable SATA Port DmVal +/** Offset 0x0685 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x06E1 +/** Offset 0x068D **/ - UINT8 UnusedUpdSpace14[1]; + UINT8 UnusedUpdSpace16[1]; -/** Offset 0x06E2 - Enable SATA Port DmVal +/** Offset 0x068E - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x06F2 - Enable SATA Port ZpOdd +/** Offset 0x069E - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x06FA - PCH Sata Rst Raid Alternate Id +/** Offset 0x06A6 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID. 0:Client, 1:Alternate, 2:Server **/ - UINT8 SataRstRaidAlternateId; + UINT8 SataRstRaidDeviceId; -/** Offset 0x06FB - PCH Sata Rst Raid0 +/** Offset 0x06A7 - PCH Sata Rst Raid0 RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x06FC - PCH Sata Rst Raid1 +/** Offset 0x06A8 - PCH Sata Rst Raid1 RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x06FD - PCH Sata Rst Raid10 +/** Offset 0x06A9 - PCH Sata Rst Raid10 RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x06FE - PCH Sata Rst Raid5 +/** Offset 0x06AA - PCH Sata Rst Raid5 RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x06FF - PCH Sata Rst Irrt +/** Offset 0x06AB - PCH Sata Rst Irrt Intel Rapid Recovery Technology. $EN_DIS **/ UINT8 SataRstIrrt; -/** Offset 0x0700 - PCH Sata Rst Orom Ui Banner +/** Offset 0x06AC - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. $EN_DIS **/ UINT8 SataRstOromUiBanner; -/** Offset 0x0701 - PCH Sata Rst Orom Ui Delay +/** Offset 0x06AD - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). **/ UINT8 SataRstOromUiDelay; -/** Offset 0x0702 - PCH Sata Rst Hdd Unlock +/** Offset 0x06AE - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. $EN_DIS **/ UINT8 SataRstHddUnlock; -/** Offset 0x0703 - PCH Sata Rst Led Locate +/** Offset 0x06AF - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. $EN_DIS **/ UINT8 SataRstLedLocate; -/** Offset 0x0704 - PCH Sata Rst Irrt Only +/** Offset 0x06B0 - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. $EN_DIS **/ UINT8 SataRstIrrtOnly; -/** Offset 0x0705 - PCH Sata Rst Smart Storage +/** Offset 0x06B1 - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. $EN_DIS **/ UINT8 SataRstSmartStorage; -/** Offset 0x0706 - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x06B2 - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x0709 - PCH Sata Rst Pcie Storage Port +/** Offset 0x06B5 - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x070C - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x06B8 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x070F - Enable eMMC HS400 Training - Determine if HS400 Training is required. +/** Offset 0x06BB - Enable eMMC HS400 Training + Deprecated. $EN_DIS **/ UINT8 PchScsEmmcHs400TuningRequired; -/** Offset 0x0710 - Set HS400 Tuning Data Valid +/** Offset 0x06BC - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. $EN_DIS **/ UINT8 PchScsEmmcHs400DllDataValid; -/** Offset 0x0711 - Rx Strobe Delay Control +/** Offset 0x06BD - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). **/ UINT8 PchScsEmmcHs400RxStrobeDll1; -/** Offset 0x0712 - Tx Data Delay Control +/** Offset 0x06BE - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). **/ UINT8 PchScsEmmcHs400TxDataDll; -/** Offset 0x0713 - I/O Driver Strength - I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm. +/** Offset 0x06BF - I/O Driver Strength + Deprecated. + 0:33 Ohm, 1:40 Ohm, 2:50 Ohm **/ UINT8 PchScsEmmcHs400DriverStrength; -/** Offset 0x0714 - Enable Pch Serial IO GPIO - Determines if enable Serial IO GPIO. - $EN_DIS -**/ - UINT8 SerialIoGpio; - -/** Offset 0x0715 - IO voltage for I2C controllers - Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. -**/ - UINT8 SerialIoI2cVoltage[6]; - -/** Offset 0x071B - Enable Serial IRQ +/** Offset 0x06C0 - Enable Serial IRQ Determines if enable Serial IRQ. $EN_DIS **/ UINT8 PchSirqEnable; -/** Offset 0x071C - Serial IRQ Mode Select +/** Offset 0x06C1 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. $EN_DIS **/ UINT8 PchSirqMode; -/** Offset 0x071D - Start Frame Pulse Width +/** Offset 0x06C2 - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. + 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk **/ UINT8 PchStartFramePulse; -/** Offset 0x071E - Enable Thermal Device - Enable Thermal Device. +/** Offset 0x06C3 - Reserved + Reserved $EN_DIS **/ - UINT8 PchThermalDeviceEnable; + UINT8 ReservedForFuture1; -/** Offset 0x071F -**/ - UINT8 UnusedUpdSpace15; - -/** Offset 0x0720 - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x0722 - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x0724 - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x0726 - Thermal Device SMI Enable +/** Offset 0x06C4 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. $EN_DIS **/ UINT8 PchTsmicLock; -/** Offset 0x0727 - Enable The Thermal Throttle +/** Offset 0x06C5 +**/ + UINT8 UnusedUpdSpace17; + +/** Offset 0x06C6 - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x06C8 - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x06CA - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x06CC - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x0728 - PMSync State 13 +/** Offset 0x06CD - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x0729 - Thermal Throttle Lock +/** Offset 0x06CE - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x072A - Thermal Throttling Suggested Setting +/** Offset 0x06CF - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x072B - Enable PCH Cross Throttling +/** Offset 0x06D0 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x072C - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x06D1 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x072D - DMI Thermal Sensor Suggested Setting +/** Offset 0x06D2 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x072E - Thermal Sensor 0 Target Width - Thermal Sensor 0 Target Width. +/** Offset 0x06D3 - Thermal Sensor 0 Target Width + DMT thermal sensor suggested representative values. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x072F - Thermal Sensor 1 Target Width +/** Offset 0x06D4 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x0730 - Thermal Sensor 2 Target Width +/** Offset 0x06D5 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x0731 - Thermal Sensor 3 Target Width +/** Offset 0x06D6 - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x0732 - Port 0 T1 Multipler +/** Offset 0x06D7 - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x0733 - Port 0 T2 Multipler +/** Offset 0x06D8 - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x0734 - Port 0 T3 Multipler +/** Offset 0x06D9 - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x0735 - Port 0 Tdispatch +/** Offset 0x06DA - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x0736 - Port 1 T1 Multipler +/** Offset 0x06DB - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x0737 - Port 1 T2 Multipler +/** Offset 0x06DC - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x0738 - Port 1 T3 Multipler +/** Offset 0x06DD - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x0739 - Port 1 Tdispatch +/** Offset 0x06DE - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x073A - Port 0 Tinactive +/** Offset 0x06DF - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x073B - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x06E0 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x073C - Port 1 Tinactive +/** Offset 0x06E1 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x073D - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x06E2 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x073E - Sata Thermal Throttling Suggested Setting +/** Offset 0x06E3 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x073F - Enable Memory Thermal Throttling +/** Offset 0x06E4 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x0740 - Memory Thermal Throttling +/** Offset 0x06E5 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x0742 - Enable Memory Thermal Throttling +/** Offset 0x06E7 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x0744 - Enable Memory Thermal Throttling +/** Offset 0x06E9 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x0746 - Thermal Device Temperature +/** Offset 0x06EB +**/ + UINT8 UnusedUpdSpace18; + +/** Offset 0x06EC - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x0748 - Disable XHCI Compliance Mode - This policy will disable XHCI compliance mode on all ports. Complicance Mode should - be default enabled. +/** Offset 0x06EE - Enable xHCI Compliance Mode + Compliance Mode can be enabled for testing through this option but this is disabled + by default. $EN_DIS **/ - UINT8 PchDisableComplianceMode; + UINT8 PchEnableComplianceMode; -/** Offset 0x0749 - USB2 Port Over Current Pin +/** Offset 0x06EF - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0759 - USB3 Port Over Current Pin +/** Offset 0x06FF - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0763 - Enable 8254 Static Clock Gating in early POST time - Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might - fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy - OS boot before enabling this. +/** Offset 0x0709 - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. $EN_DIS **/ - UINT8 Early8254ClockGatingEnable; + UINT8 Enable8254ClockGating; -/** Offset 0x0764 - PCH Sata Rst Optane Memory +/** Offset 0x070A - PCH Sata Rst Optane Memory Optane Memory $EN_DIS **/ UINT8 SataRstOptaneMemory; -/** Offset 0x0765 - PCH SATA RST CPU attached storage - RST CPU attached storage +/** Offset 0x070B - PCH Sata Rst CPU Attached Storage + CPU Attached Storage $EN_DIS **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x0766 +/** Offset 0x070C - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS **/ - UINT8 UnusedUpdSpace16[2]; + UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0768 - Pch PCIE device override table pointer +/** Offset 0x070D +**/ + UINT8 UnusedUpdSpace19[3]; + +/** Offset 0x0710 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId @@ -2261,7 +2329,7 @@ **/ UINT32 PchPcieDeviceOverrideTablePtr; -/** Offset 0x076C - Enable TCO timer. +/** Offset 0x0714 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2269,7 +2337,7 @@ **/ UINT8 EnableTcoTimer; -/** Offset 0x076D - Enable PS_ON. +/** Offset 0x0715 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2277,98 +2345,107 @@ **/ UINT8 PsOnEnable; -/** Offset 0x076E - ReservedPchPostMem +/** Offset 0x0716 - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x0717 - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspmCtrl; + +/** Offset 0x0718 - ReservedPchPostMem Reserved for Pch Post-Mem $EN_DIS **/ UINT8 ReservedPchPostMem[16]; -/** Offset 0x077E -**/ - UINT8 UnusedUpdSpace17[2]; - -/** Offset 0x0780 - BgpdtHash[4] +/** Offset 0x0728 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x07A0 - BiosGuardAttr +/** Offset 0x0748 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x07A4 +/** Offset 0x074C **/ - UINT8 UnusedUpdSpace18[4]; + UINT8 UnusedUpdSpace20[4]; -/** Offset 0x07A8 - BiosGuardModulePtr +/** Offset 0x0750 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x07B0 - SendEcCmd +/** Offset 0x0758 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x07B8 - EcCmdProvisionEav +/** Offset 0x0760 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x07B9 - EcCmdLock +/** Offset 0x0761 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x07BA +/** Offset 0x0762 **/ - UINT8 UnusedUpdSpace19[6]; + UINT8 UnusedUpdSpace21[6]; -/** Offset 0x07C0 - SgxEpoch0 +/** Offset 0x0768 - SgxEpoch0 SgxEpoch0 default values **/ UINT64 SgxEpoch0; -/** Offset 0x07C8 - SgxEpoch1 +/** Offset 0x0770 - SgxEpoch1 SgxEpoch1 default values **/ UINT64 SgxEpoch1; -/** Offset 0x07D0 - SgxSinitNvsData +/** Offset 0x0778 - SgxSinitNvsData SgxSinitNvsData default values **/ UINT8 SgxSinitNvsData; -/** Offset 0x07D1 - Si Config CSM Flag. +/** Offset 0x0779 - Si Config CSM Flag. Platform specific common policies that used by several silicon components. CSM status flag. $EN_DIS **/ UINT8 SiCsmFlag; -/** Offset 0x07D2 +/** Offset 0x077A **/ - UINT8 UnusedUpdSpace20[2]; + UINT8 UnusedUpdSpace22[2]; -/** Offset 0x07D4 - SVID SDID table Poniter. +/** Offset 0x077C - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. **/ UINT32 SiSsidTablePtr; -/** Offset 0x07D8 - Number of ssid table. +/** Offset 0x0780 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x07DA - SATA RST Interrupt Mode +/** Offset 0x0782 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x07DB - ME Unconfig on RTC clear +/** Offset 0x0783 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2376,11 +2453,11 @@ **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x07DC +/** Offset 0x0784 **/ - UINT8 UnusedUpdSpace21[3]; + UINT8 UnusedUpdSpace23[3]; -/** Offset 0x07DF +/** Offset 0x0787 **/ UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; @@ -2389,74 +2466,74 @@ **/ typedef struct { -/** Offset 0x07E0 +/** Offset 0x0788 **/ UINT32 Signature; -/** Offset 0x07E4 - Enable/Disable Device 7 +/** Offset 0x078C - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS **/ UINT8 ChapDeviceEnable; -/** Offset 0x07E5 - Skip PAM register lock +/** Offset 0x078D - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x07E6 - EDRAM Test Mode +/** Offset 0x078E - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x07E7 - DMI Extended Sync Control +/** Offset 0x078F - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS **/ UINT8 DmiExtSync; -/** Offset 0x07E8 - DMI IOT Control +/** Offset 0x0790 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS **/ UINT8 DmiIot; -/** Offset 0x07E9 - PEG Max Payload size per root port +/** Offset 0x0791 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B **/ UINT8 PegMaxPayload[4]; -/** Offset 0x07ED - Enable/Disable IGFX RenderStandby +/** Offset 0x0795 - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x07EE - Enable/Disable IGFX PmSupport +/** Offset 0x0796 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x07EF - Enable/Disable CdynmaxClamp +/** Offset 0x0797 - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x07F0 - Disable VT-d +/** Offset 0x0798 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisableDeprecated; -/** Offset 0x07F1 - GT Frequency Limit +/** Offset 0x0799 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2470,19 +2547,19 @@ **/ UINT8 GtFreqMax; -/** Offset 0x07F2 - Disable Turbo GT +/** Offset 0x079A - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x07F3 - SaPostMemTestRsvd +/** Offset 0x079B - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS **/ UINT8 SaPostMemTestRsvd[11]; -/** Offset 0x07FE - 1-Core Ratio Limit +/** Offset 0x07A6 - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, @@ -2490,79 +2567,79 @@ **/ UINT8 OneCoreRatioLimit; -/** Offset 0x07FF - 2-Core Ratio Limit +/** Offset 0x07A7 - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 TwoCoreRatioLimit; -/** Offset 0x0800 - 3-Core Ratio Limit +/** Offset 0x07A8 - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 ThreeCoreRatioLimit; -/** Offset 0x0801 - 4-Core Ratio Limit +/** Offset 0x07A9 - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 FourCoreRatioLimit; -/** Offset 0x0802 - Enable or Disable HWP +/** Offset 0x07AA - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0803 - Hardware Duty Cycle Control +/** Offset 0x07AB - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x0804 - Package Long duration turbo mode time +/** Offset 0x07AC - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x0805 - Short Duration Turbo Mode +/** Offset 0x07AD - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x0806 - Turbo settings Lock +/** Offset 0x07AE - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x0807 - Package PL3 time window +/** Offset 0x07AF - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x0808 - Package PL3 Duty Cycle +/** Offset 0x07B0 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x0809 - Package PL3 Lock +/** Offset 0x07B1 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x080A - Package PL4 Lock +/** Offset 0x07B2 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x080B - TCC Activation Offset +/** Offset 0x07B3 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, @@ -2570,7 +2647,7 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x080C - Tcc Offset Clamp Enable/Disable +/** Offset 0x07B4 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -2578,345 +2655,345 @@ **/ UINT8 TccOffsetClamp; -/** Offset 0x080D - Tcc Offset Lock +/** Offset 0x07B5 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x080E - Custom Ratio State Entries +/** Offset 0x07B6 - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x080F - Custom Short term Power Limit time window +/** Offset 0x07B7 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x0810 - Custom Turbo Activation Ratio +/** Offset 0x07B8 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x0811 - Custom Config Tdp Control +/** Offset 0x07B9 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x0812 - Custom Short term Power Limit time window +/** Offset 0x07BA - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x0813 - Custom Turbo Activation Ratio +/** Offset 0x07BB - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x0814 - Custom Config Tdp Control +/** Offset 0x07BC - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x0815 - Custom Short term Power Limit time window +/** Offset 0x07BD - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x0816 - Custom Turbo Activation Ratio +/** Offset 0x07BE - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x0817 - Custom Config Tdp Control +/** Offset 0x07BF - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x0818 - ConfigTdp mode settings Lock +/** Offset 0x07C0 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x0819 - Load Configurable TDP SSDT +/** Offset 0x07C1 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x081A - PL1 Enable value +/** Offset 0x07C2 - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x081B - PL1 timewindow +/** Offset 0x07C3 - PL1 timewindow PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x081C - PL2 Enable Value +/** Offset 0x07C4 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x081D - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x07C5 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x081E - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x07C6 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x081F - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x07C7 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0820 - Enable or Disable initialization of machine check registers +/** Offset 0x07C8 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0821 - Deprecated DO NOT USE Enable or Disable processor debug features +/** Offset 0x07C9 - Deprecated DO NOT USE Enable or Disable processor debug features @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; -/** Offset 0x0822 - Lock or Unlock debug interface features +/** Offset 0x07CA - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x0823 - AP Idle Manner of waiting for SIPI +/** Offset 0x07CB - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x0824 - Control on Processor Trace output scheme +/** Offset 0x07CC - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0825 - Enable or Disable Processor Trace feature +/** Offset 0x07CD - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0826 +/** Offset 0x07CE **/ - UINT8 UnusedUpdSpace22[2]; + UINT8 UnusedUpdSpace24[2]; -/** Offset 0x0828 - Base of memory region allocated for Processor Trace +/** Offset 0x07D0 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT64 ProcessorTraceMemBase; -/** Offset 0x0830 - Memory region allocation for Processor Trace +/** Offset 0x07D8 - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT32 ProcessorTraceMemLength; -/** Offset 0x0834 - Enable or Disable Voltage Optimization feature +/** Offset 0x07DC - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS **/ UINT8 VoltageOptimization; -/** Offset 0x0835 - Enable or Disable Intel SpeedStep Technology +/** Offset 0x07DD - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x0836 - Enable or Disable Energy Efficient P-state +/** Offset 0x07DE - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x0837 - Enable or Disable Energy Efficient Turbo +/** Offset 0x07DF - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x0838 - Enable or Disable T states +/** Offset 0x07E0 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x0839 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x07E1 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x083A - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x07E2 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x083B - Enable or Disable PROCHOT# Response +/** Offset 0x07E3 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x083C - Enable or Disable VR Thermal Alert +/** Offset 0x07E4 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x083D - Enable or Disable Thermal Reporting +/** Offset 0x07E5 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 AutoThermalReporting; -/** Offset 0x083E - Enable or Disable Thermal Monitor +/** Offset 0x07E6 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x083F - Enable or Disable CPU power states (C-states) +/** Offset 0x07E7 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0840 - Configure C-State Configuration Lock +/** Offset 0x07E8 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x0841 - Enable or Disable Enhanced C-states +/** Offset 0x07E9 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x0842 - Enable or Disable Package Cstate Demotion +/** Offset 0x07EA - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x0843 - Enable or Disable Package Cstate UnDemotion +/** Offset 0x07EB - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x0844 - Enable or Disable CState-Pre wake +/** Offset 0x07EC - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x0845 - Enable or Disable TimedMwait Support. +/** Offset 0x07ED - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x0846 - Enable or Disable IO to MWAIT redirection +/** Offset 0x07EE - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x0847 - Set the Max Pkg Cstate +/** Offset 0x07EF - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x0848 - TimeUnit for C-State Latency Control0 +/** Offset 0x07F0 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x0849 - TimeUnit for C-State Latency Control1 +/** Offset 0x07F1 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x084A - TimeUnit for C-State Latency Control2 +/** Offset 0x07F2 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x084B - TimeUnit for C-State Latency Control3 +/** Offset 0x07F3 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x084C - TimeUnit for C-State Latency Control4 +/** Offset 0x07F4 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x084D - TimeUnit for C-State Latency Control5 +/** Offset 0x07F5 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x084E - Interrupt Redirection Mode Select +/** Offset 0x07F6 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x084F - Lock prochot configuration +/** Offset 0x07F7 - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x0850 - Configuration for boot TDP selection +/** Offset 0x07F8 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ UINT8 ConfigTdpLevel; -/** Offset 0x0851 - Race To Halt +/** Offset 0x07F9 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -2924,19 +3001,19 @@ **/ UINT8 RaceToHalt; -/** Offset 0x0852 - Max P-State Ratio +/** Offset 0x07FA - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x0853 - P-state ratios for custom P-state table +/** Offset 0x07FB - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x087B - P-state ratios for max 16 version of custom P-state table +/** Offset 0x0823 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -2945,399 +3022,391 @@ **/ UINT8 StateRatioMax16[16]; -/** Offset 0x088B +/** Offset 0x0833 **/ - UINT8 UnusedUpdSpace23; + UINT8 UnusedUpdSpace25; -/** Offset 0x088C - Platform Power Pmax +/** Offset 0x0834 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x088E - Interrupt Response Time Limit of C-State LatencyContol0 +/** Offset 0x0836 - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl0Irtl; -/** Offset 0x0890 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0838 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x0892 - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x083A - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x0894 - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x0896 - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0898 - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x089A +/** Offset 0x0842 **/ - UINT8 UnusedUpdSpace24[2]; + UINT8 UnusedUpdSpace26[2]; -/** Offset 0x089C - Package Long duration turbo mode power limit +/** Offset 0x0844 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x08A0 - Package Short duration turbo mode power limit +/** Offset 0x0848 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x08A4 - Package PL3 power limit +/** Offset 0x084C - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x08A8 - Package PL4 power limit +/** Offset 0x0850 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x08AC - Tcc Offset Time Window for RATL +/** Offset 0x0854 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x08B0 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0858 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x08B4 - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x085C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x08B8 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0860 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x08BC - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x0864 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x08C0 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x0868 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x08C4 - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x086C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x08C8 - Platform PL1 power +/** Offset 0x0870 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x08CC - Platform PL2 power +/** Offset 0x0874 - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x08D0 - Set Three Strike Counter Disable +/** Offset 0x0878 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x08D1 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x0879 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x08D2 - 5-Core Ratio Limit +/** Offset 0x087A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 FiveCoreRatioLimit; -/** Offset 0x08D3 - 6-Core Ratio Limit +/** Offset 0x087B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SixCoreRatioLimit; -/** Offset 0x08D4 - 7-Core Ratio Limit +/** Offset 0x087C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SevenCoreRatioLimit; -/** Offset 0x08D5 - 8-Core Ratio Limit +/** Offset 0x087D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 EightCoreRatioLimit; -/** Offset 0x08D6 - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x087E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x08D7 - Intel Turbo Boost Max Technology 3.0 Driver +/** Offset 0x087F - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbmDriver; -/** Offset 0x08D8 - Enable or Disable C1 Cstate Demotion +/** Offset 0x0880 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x08D9 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x0881 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x08DA - CpuWakeUpTimer +/** Offset 0x0882 - CpuWakeUpTimer Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CpuWakeUpTimer; -/** Offset 0x08DB - Minimum Ring ratio limit override +/** Offset 0x0883 - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x08DC - Minimum Ring ratio limit override +/** Offset 0x0884 - Minimum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x08DD - Enable or Disable C3 Cstate Demotion +/** Offset 0x0885 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateAutoDemotion; -/** Offset 0x08DE - Enable or Disable C3 Cstate UnDemotion +/** Offset 0x0886 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateUnDemotion; -/** Offset 0x08DF - ReservedCpuPostMemTest +/** Offset 0x0887 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ UINT8 ReservedCpuPostMemTest[19]; -/** Offset 0x08F2 - SgxSinitDataFromTpm +/** Offset 0x089A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values **/ UINT8 SgxSinitDataFromTpm; -/** Offset 0x08F3 - End of Post message +/** Offset 0x089B - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x08F4 - D0I3 Setting for HECI Disable +/** Offset 0x089C - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x08F5 - Enable LOCKDOWN SMI +/** Offset 0x089D +**/ + UINT8 UnusedUpdSpace27; + +/** Offset 0x089E - HD Audio Reset Wait Timer + The delay timer after Azalia reset, the value is number of microseconds. Default is 600. +**/ + UINT16 PchHdaResetWaitTimer; + +/** Offset 0x08A0 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x08F6 - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x08F8 - Enable LOCKDOWN BIOS Interface +/** Offset 0x08A1 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x08F9 - RTC CMOS RAM LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. +/** Offset 0x08A2 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ - UINT8 PchLockDownRtcLock; + UINT8 PchUnlockGpioPads; -/** Offset 0x08FA - PCH Sbi lock bit - This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchSbiUnlock; - -/** Offset 0x08FB - PCH Psf lock bit - The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable. +/** Offset 0x08A3 - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x08FC - PCIE RP Ltr Max Snoop Latency +/** Offset 0x08A4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x092C - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x08D4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x095C - PCIE RP Snoop Latency Override Mode +/** Offset 0x0904 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[24]; -/** Offset 0x0974 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x091C - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x098C - PCIE RP Snoop Latency Override Value +/** Offset 0x0934 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x09BC - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0964 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; -/** Offset 0x09D4 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x097C - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x09EC - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x0A1C - PCIE RP Slot Power Limit Scale +/** Offset 0x09C4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[24]; -/** Offset 0x0A34 - PCIE RP Slot Power Limit Value +/** Offset 0x09DC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0A64 - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0A0C - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 5. **/ UINT8 PcieRpUptp[24]; -/** Offset 0x0A7C - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0A24 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 PcieRpDptp[24]; -/** Offset 0x0A94 - PCIE RP Enable Port8xh Decode +/** Offset 0x0A3C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0A95 - PCIE Port8xh Decode Port Index +/** Offset 0x0A3D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0A96 - PCH Pm Disable Energy Report - Disable/Enable PCH to CPU enery report feature. +/** Offset 0x0A3E - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0A97 - PCH Sata Test Mode +/** Offset 0x0A3F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0A98 - PCH USB OverCurrent mapping lock enable +/** Offset 0x0A40 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0A99 - Xhci OverCurrent enable - Xhci Overcurrent enable. +/** Offset 0x0A41 - ReservedPchPostMemTest + Reserved for Pch Post-Mem Test $EN_DIS **/ - UINT8 PchXhciOcEnable; + UINT8 ReservedPchPostMemTest[16]; -/** Offset 0x0A9A - ReservedPchPostMemTest - Reserved for Pch Post-Mem - $EN_DIS -**/ - UINT8 ReservedPchPostMem[16]; - -/** Offset 0x0AAA - Mctp Broadcast Cycle +/** Offset 0x0A51 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0AAB +/** Offset 0x0A52 **/ - UINT8 UnusedUpdSpace25[1]; + UINT8 UnusedUpdSpace28[2]; -/** Offset 0x0AAC +/** Offset 0x0A54 **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -3354,15 +3423,15 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x07E0 +/** Offset 0x0788 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0AB8 +/** Offset 0x0A60 **/ - UINT8 UnusedUpdSpace26[6]; + UINT8 UnusedUpdSpace29[6]; -/** Offset 0x0ABE +/** Offset 0x0A66 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/31855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Gerrit-Change-Number: 31855 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake
by Furquan Shaikh (Code Review) 13 Mar '19

13 Mar '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31855 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Gerrit-Change-Number: 31855 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Mar 2019 14:33:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake
by Rizwan Qureshi (Code Review) 13 Mar '19

13 Mar '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31855 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for Cometlake ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Gerrit-Change-Number: 31855 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Mar 2019 13:32:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add DRAM resources
by Sricharan Ramabadhran (Code Review) 13 Mar '19

13 Mar '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29954 ) Change subject: qcs405: Add DRAM resources ...................................................................... Patch Set 13: (2 comments) https://review.coreboot.org/#/c/29954/13/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/symbols.h: https://review.coreboot.org/#/c/29954/13/src/soc/qualcomm/qcs405/include/so… PS13, Line 29: extern u8 _dram_reserved[]; > DECLARE_REGION as introduced in 7e0dea6317d ok https://review.coreboot.org/#/c/29954/13/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29954/13/src/soc/qualcomm/qcs405/soc.c@24 PS13, Line 24: ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE1GB / KiB); > 1 * GiB […] ok, will fix -- To view, visit https://review.coreboot.org/c/coreboot/+/29954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Gerrit-Change-Number: 29954 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Mar 2019 13:29:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support
by Sricharan Ramabadhran (Code Review) 12 Mar '19

12 Mar '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 14: > Patch Set 14: > > > Hi Julius, > > So this patch is without the interface table support. Only loading the qclib blob. Will add the support for the interface table in later patches. Was planning to add all the relevant structures at that time. Hence trimmed this patch to be minimal like this. Not ok ? > > Well... I'm just generally not a fan of landing premature hacks. It's just taking time away from working on the actual fix. You might as well leave this floating until you can clean it up. > > Note that this patch also has the same problem in the Makefile as the other one I pointed out anyway. We shouldn't submit those hacks which work around valid build errors, we should rather spend our energy on getting the licensing issues worked out for good. Ok, the interface table support is not yet added. But will add that in the coming week. Apart from that, i have already started checking with Qualcomm internal team to solve the issue with Blobs sharing for Qcs405. Till that point, this patch and the subsequent ones that depends on blobs will anyways have to be floating though. Will try to push to get the solution ASAP. -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 14 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Mar 2019 11:11:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2019