Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31545
Change subject: acpi: Sort the reported APIC-IDs in the MADT table
......................................................................
acpi: Sort the reported APIC-IDs in the MADT table
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, The OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
enviroinment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.
Though there is a way on discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.
Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/arch/x86/acpi.c
1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31545/1
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 0c85d3a..c7b9214 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -8,7 +8,7 @@
* Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>,
* Raptor Engineering
- * Copyright (C) 2016-2017 Siemens AG
+ * Copyright (C) 2016-2019 Siemens AG
*
* ACPI FADT, FACS, and DSDT table support added by
* Nick Barker <nick.barker9(a)btinternet.com>, and those portions
@@ -47,6 +47,7 @@
#include <cpu/x86/lapic_def.h>
#include <cpu/cpu.h>
#include <cbfs.h>
+#include <sort.h>
u8 acpi_checksum(u8 *table, u32 length)
{
@@ -148,7 +149,7 @@
unsigned long acpi_create_madt_lapics(unsigned long current)
{
struct device *cpu;
- int index = 0;
+ int index, apic_ids[CONFIG_MAX_CPUS], num_cpus = 0;
for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
@@ -157,9 +158,12 @@
}
if (!cpu->enabled)
continue;
+ apic_ids[num_cpus++] = cpu->path.apic.apic_id;
+ }
+ bubblesort(apic_ids, num_cpus, NUM_ASCENDING);
+ for (index = 0; index < num_cpus; index++) {
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
- index, cpu->path.apic.apic_id);
- index++;
+ index, apic_ids[index]);
}
return current;
--
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Gerrit-Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
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You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31843
Change subject: mediatek: Read AP watchdog flag from Chrome EC if needed
......................................................................
mediatek: Read AP watchdog flag from Chrome EC if needed
On some boards (e.g., Kukui), AP doesn't remember if the last AP reset
was due to AP watchdog. In this case, we should query the reset reason
from EC.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=none
Change-Id: I08af1fea38e4e49b0f14cb25551512244ef0690a
Signed-off-by: You-Cheng Syu <youcheng(a)google.com>
---
M src/soc/mediatek/common/wdt.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31843/1
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c
index 54ce8c0..e21fab0 100644
--- a/src/soc/mediatek/common/wdt.c
+++ b/src/soc/mediatek/common/wdt.c
@@ -15,6 +15,7 @@
#include <device/mmio.h>
#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
#include <soc/wdt.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -25,8 +26,11 @@
/* Write Mode register will clear status register */
wdt_sta = read32(&mtk_wdt->wdt_status);
+ bool hw_rst = (CONFIG(EC_GOOGLE_CHROMEEC_AP_WATCHDOG_FLAG) ?
+ google_chromeec_get_ap_watchdog_flag() :
+ (wdt_sta & MTK_WDT_STA_HW_RST));
printk(BIOS_INFO, "WDT: Last reset was ");
- if (wdt_sta & MTK_WDT_STA_HW_RST) {
+ if (hw_rst) {
printk(BIOS_INFO, "hardware watchdog\n");
mark_watchdog_tombstone();
} else if (wdt_sta & MTK_WDT_STA_SW_RST)
--
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31839
Change subject: Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI
......................................................................
Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI
Some new feature added into FSP specification to perform dispatching
of external PPI service from boot firmware (coreboot) to FSP.
Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M Documentation/soc/intel/fsp/index.md
A Documentation/soc/intel/fsp/ppi/ppi.md
2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31839/1
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index 039a389..d7f44c6 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -11,3 +11,7 @@
* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical…
* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical…
+
+## Additional Features in FSP 2.1 specification
+
+- [PPI](ppi/ppi.md)
diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md
new file mode 100644
index 0000000..66dbf07
--- /dev/null
+++ b/Documentation/soc/intel/fsp/ppi/ppi.md
@@ -0,0 +1,9 @@
+# PEIM to PEIM Interface (PPI)
+
+This section is intended to document the purpose of creating PPI service
+inside coreboot space to perform some specific operation related to CPU,
+chipset using Intel FSP. This feature is added into FSP specification 2.1
+where FSP should be able to locate PPI, published by boot firmware and
+able to execute the same in FSP's context.
+
+* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference…
--
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31836
Change subject: drivers/intel/fsp2_0: Add provision to include PPI directory
......................................................................
drivers/intel/fsp2_0: Add provision to include PPI directory
This patch adds a generic provision into FSP2.0 driver to implement
dedicated PEIM to PEIM interface as per Intel FSP requirement.
Change-Id: I988d55890f8dd95ccf80c1f1ec2eba8196ddf9a7
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31836/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 8e64c6b..3951e9a 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -172,4 +172,15 @@
This allows deployed systems to bump their version number
with the same FSP which will trigger a retrain of the memory.
+config FSP_PEIM_TO_PEIM_INTERFACE
+ bool
+ help
+ This option allows SOC user to create specific PPI for Intel FSP
+ usage, coreboot will provide required PPI structure definitions
+ along with all APIs as per EFI specification.
+
+if FSP_PEIM_TO_PEIM_INTERFACE
+source "src/drivers/intel/fsp2_0/ppi/Kconfig"
+endif
+
endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 79fe5f8..f26a776 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -82,4 +82,7 @@
CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH)
endif
+# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable
+subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi
+
endif
--
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25634 )
Change subject: drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIs
......................................................................
Patch Set 54:
(1 comment)
> Patch Set 54: Code-Review+2
HI Idwer Vollering,
Can you please help to review your previous vote (-2) now?
https://review.coreboot.org/#/c/25634/52/src/drivers/intel/fsp2_0/include/f…
File src/drivers/intel/fsp2_0/include/fsp/fsp_mp_service_ppi.h:
PS52:
> If we start here with a PPI (interface) also make it part of the include/fsp/ppi/mp_service. […]
Done
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Hello Patrick Rudolph, Aamir Bohra, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30310
to look at the new patch set (#10).
Change subject: drivers/intel/fsp2_0: Add support for FSP minor version update
......................................................................
drivers/intel/fsp2_0: Add support for FSP minor version update
This patch adds support for FSP2.1 Kconfig which is backward compatible
with FSP2.0 specification and added below coreboot impacted features as below:
1. Remove FSP stack switch and use the same stack with boot firmware
2. FSP should support external PPI interface pulled in via
FSP_PEIM_TO_PEIM_INTERFACE
Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30310/10
--
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Change subject: drivers/intel/fsp2_0: Add support for FSP minor version update
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30310/8/src/drivers/intel/fsp2_0/Kconfig
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/#/c/30310/8/src/drivers/intel/fsp2_0/Kconfig@32
PS8, Line 32: 2. FSP should support external EFI_PEI_MP_SERVICES_PPI service
> FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE
Done
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Hello Patrick Rudolph, Aamir Bohra, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
Change subject: drivers/intel/fsp2_0: Add support for FSP minor version update
......................................................................
drivers/intel/fsp2_0: Add support for FSP minor version update
This patch adds support for FSP2.1 Kconfig which is backward compatible
with FSP2.0 specification and added below coreboot impacted features as below:
1. Remove FSP stack switch and use the same stack with boot firmware
2. FSP should support external EFI_PEI_MP_SERVICES_PPI service
Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30310/9
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Change subject: soc/intel/common: Remove common chip config use_fsp_mp_init
......................................................................
Patch Set 10: Code-Review-1
(1 comment)
https://review.coreboot.org/#/c/30289/10/src/mainboard/google/dragonegg/Kco…
File src/mainboard/google/dragonegg/Kconfig:
https://review.coreboot.org/#/c/30289/10/src/mainboard/google/dragonegg/Kco…
PS10, Line 14: select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
Make this selectable by previous kconfig menu. USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI can be default but remove this as hard selection here.
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