Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31140
Change subject: lib/hardwaremain: Remove unused acpi_is_wakeup() function
......................................................................
lib/hardwaremain: Remove unused acpi_is_wakeup() function
Looks like acpi_is_wakeup() return value is not getting honoured,
hence this function is not doing anything rather reading from romstage
buffer.
Change-Id: Icc57804074a58315e72e276fcae799febc10612d
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/lib/hardwaremain.c
1 file changed, 1 insertion(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31140/1
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 98b8841..3ec7e8e 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2019 Intel Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -469,11 +470,6 @@
timestamp_add_now(TS_START_RAMSTAGE);
post_code(POST_ENTRY_RAMSTAGE);
- /* Handoff sleep type from romstage. */
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
- acpi_is_wakeup();
-#endif
-
exception_init();
threads_initialize();
--
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Gerrit-Change-Id: Icc57804074a58315e72e276fcae799febc10612d
Gerrit-Change-Number: 31140
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27329 )
Change subject: timestamps: denote "end of romstage" right before loading ramstage
......................................................................
Patch Set 2:
Probably obsolete?
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Gerrit-Change-Number: 27329
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31755 )
Change subject: device/pci_ops: Define pci_find_capability() just once
......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/#/c/31755/3/src/device/pci_ops.c
File src/device/pci_ops.c:
https://review.coreboot.org/#/c/31755/3/src/device/pci_ops.c@33
PS3, Line 33: unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last)
Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/#/c/31755/3/src/device/pci_ops.c@33
PS3, Line 33: unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last)
Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/#/c/31755/3/src/device/pci_ops.c@35
PS3, Line 35: unsigned pos = 0;
Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/#/c/31755/3/src/device/pci_ops.c@37
PS3, Line 37: unsigned reps = 48;
Prefer 'unsigned int' to bare use of 'unsigned'
https://review.coreboot.org/#/c/31755/3/src/device/pci_ops.c@84
PS3, Line 84: unsigned int pci_find_capability(pci_devfn_t dev, unsigned cap)
Prefer 'unsigned int' to bare use of 'unsigned'
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31757
to look at the new patch set (#3).
Change subject: [WIP] device/pci_ops: Store pci_devfn_t in devicetree
......................................................................
[WIP] device/pci_ops: Store pci_devfn_t in devicetree
This allows for tighter inlining of PCI config accessors
in ramstage, as invariant PCI bus:dev.fn is already encoded
during device enumeration.
Change-Id: Ie36a43ee0cc4770f5dbd2671ce188c9ade9af2cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/arch/x86/include/arch/pci_io_cfg.h
M src/include/device/pci_ops.h
M src/include/device/pci_type.h
3 files changed, 18 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31757/3
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Hello Patrick Rudolph, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31755
to look at the new patch set (#3).
Change subject: device/pci_ops: Define pci_find_capability() just once
......................................................................
device/pci_ops: Define pci_find_capability() just once
Use same implementation for romstage and ramstage.
Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/device/hypertransport.c
M src/device/pci_device.c
M src/device/pci_early.c
M src/device/pci_ops.c
M src/device/pciexp_device.c
M src/device/pcix_device.c
M src/drivers/usb/pci_ehci.c
M src/include/device/pci.h
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/cavium/common/ecam.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/fsp_baytrail/southcluster.c
M src/southbridge/amd/amd8132/bridge.c
M src/southbridge/amd/sr5650/sr5650.c
16 files changed, 104 insertions(+), 147 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31755/3
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Hello Aaron Durbin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: device/pci: Rewrite PCI MMCONF with symbol reference
......................................................................
device/pci: Rewrite PCI MMCONF with symbol reference
Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
A src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
M src/arch/x86/include/arch/pci_ops.h
M src/device/Makefile.inc
M src/device/pci_ops.c
M src/include/device/pci_mmio_cfg.h
5 files changed, 112 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31752/3
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