coreboot-gerrit November 2019

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Change in coreboot[master]: [TESTONLY, DONOTMERGE] nb/gm45/rcven: Fill to the brim with spam
by Angel Pons (Code Review) 10 Sep '20

10 Sep '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34865 ) Change subject: [TESTONLY, DONOTMERGE] nb/gm45/rcven: Fill to the brim with spam ...................................................................... [TESTONLY, DONOTMERGE] nb/gm45/rcven: Fill to the brim with spam Change-Id: I4de1d7fc70877c11c37549cf1d723cbdcc6b1910 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 1 file changed, 162 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/34865/1 diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 7c7f56d..0385160 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -42,6 +42,7 @@ #define CxDRT3_C_SHIFT 7 #define CxDRT3_C_MASK (0xf << CxDRT3_C_SHIFT) #define CxDRT3_C(c) ((c << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) + /* group to byte-lane mapping: (cardF X group X 2 per group) */ static const char bytelane_map[2][4][2] = { /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, @@ -51,93 +52,156 @@ #define PH_BOUND 4 #define PH_STEP 2 #define PM_BOUND 3 -#define C_BOUND 16 +#define C_BOUND 16 typedef struct { - int c; - int pre; - int ph; - int t; + int c; // Coarse + int pre; // NOT! Preamble, per bytelane additional delay to Coarse + int ph; // Phase + int t; // TAP const int t_bound; - int p; + int p; // PI const int p_bound; } rec_timing_t; + +#define RCVEN_SPEW BIOS_DEBUG + +static void print_timings(int channel, int group, rec_timing_t timings[][4]) +{ + printk(RCVEN_SPEW, "ch %d, group %d: ", channel, group); + print_timing(&timings[channel][group]); +} + +static void print_timing(rec_timing_t *const timing) +{ + printk(RCVEN_SPEW, "\t%d.%d.%d.%d.%d\n", + timing->c, + timing->pre, + timing->ph, + timing->t, + timing->p + ); +} + static void normalize_rec_timing(rec_timing_t *const timing) { + unsigned int tmp = 0; + + printk(RCVEN_SPEW, "NORMALIZE START\n"); + while (timing->p >= timing->p_bound) { + tmp++; timing->t++; timing->p -= timing->p_bound; } + printk(RCVEN_SPEW, "\tafter %u t++: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->p < 0) { + tmp++; timing->t--; timing->p += timing->p_bound; } + printk(RCVEN_SPEW, "\tafter %u t--: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->t >= timing->t_bound) { + tmp++; timing->ph += PH_STEP; timing->t -= timing->t_bound; } + printk(RCVEN_SPEW, "\tafter %u ph++: " tmp); + print_timing(timing); + tmp = 0; + while (timing->t < 0) { + tmp++; timing->ph -= PH_STEP; timing->t += timing->t_bound; } + printk(RCVEN_SPEW, "\tafter %u ph--: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->ph >= PH_BOUND) { + tmp++; timing->c++; timing->ph -= PH_BOUND; } + printk(RCVEN_SPEW, "\tafter %u c++: ", tmp); + print_timing(timing); + tmp = 0; + while (timing->ph < 0) { + tmp++; timing->c--; timing->ph += PH_BOUND; } - if (timing->c < 0 || timing->c >= C_BOUND) - die("Timing under-/overflow during " - "receive-enable calibration.\n"); + printk(RCVEN_SPEW, "\tafter %u c--: ", tmp); + print_timing(timing); + + if (timing->c < 0) + die("Timing under during receive-enable calibration.\n"); + + else if (timing->c >= C_BOUND) + die("Timing overflow during receive-enable calibration.\n"); + + printk(RCVEN_SPEW, "NORMALIZE END\n"); } static void rec_full_backstep(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "full backstep, "); timing->c--; } static void rec_half_backstep(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "half backstep, "); timing->ph -= PH_STEP; } static void rec_quarter_step(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "quarter step, "); timing->t += (timing->t_bound) >> 1; timing->p += (timing->t_bound & 1) * (timing->p_bound >> 1); } static void rec_quarter_backstep(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "quarter backstep, "); timing->t -= (timing->t_bound) >> 1; timing->p -= (timing->t_bound & 1) * (timing->p_bound >> 1); } static void rec_smallest_step(rec_timing_t *const timing) { + printk(RCVEN_SPEW, "pi step, "); timing->p++; } -static void program_timing(int channel, int group, - rec_timing_t timings[][4]) +static void program_timing(int channel, int group, rec_timing_t timings[][4]) { rec_timing_t *const timing = &timings[channel][group]; + printk(RCVEN_SPEW, "%s: will normalize: ", __func__); + print_timing(timing); normalize_rec_timing(timing); /* C value is per channel. */ unsigned int mchbar = CxDRT3_MCHBAR(channel); - MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | - CxDRT3_C(timing->c); + MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | CxDRT3_C(timing->c); /* All other per group. */ mchbar = CxRECy_MCHBAR(channel, group); u32 reg = MCHBAR32(mchbar); reg &= ~CxRECy_TIMING_MASK; - reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | - CxRECy_PH(timing->ph) | CxRECy_PM(timing->pre); + reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | CxRECy_PH(timing->ph); + reg |= CxRECy_PM(timing->pre); MCHBAR32(mchbar) = reg; } static int read_dqs_level(const int channel, const int lane) { + unsigned int mchbar = 0x14f0 + (channel * 0x0100); MCHBAR32(mchbar) &= ~(1 << 9); MCHBAR32(mchbar) |= (1 << 9); @@ -146,58 +210,97 @@ read32((u32 *)raminit_get_rank_addr(channel, 0)); mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); - return MCHBAR32(mchbar) & (1 << 30); + + int level = MCHBAR32(mchbar) & (1 << 30); + + printk(RCVEN_SPEW, "DQS for channel %d lane %d: %s\n", + channel, lane, (level ? "HIGH" : "LOW"); + + return level; } static void find_dqs_low(const int channel, const int group, rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); + + printk(RCVEN_SPEW, "Look for DQS low, using quarter steps.\n"); /* Look for DQS low, using quarter steps. */ while (read_dqs_level(channel, lane_map[group][0]) || read_dqs_level(channel, lane_map[group][1])) { + rec_quarter_step(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void find_dqs_high(const int channel, const int group, rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); /* Look for _any_ DQS high, using quarter steps. */ while (!read_dqs_level(channel, lane_map[group][0]) && !read_dqs_level(channel, lane_map[group][1])) { + rec_quarter_step(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void find_dqs_edge_lowhigh(const int channel, const int group, - rec_timing_t timings[][4], - const char lane_map[][2]) + rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); + + printk(RCVEN_SPEW, "Advance beyond previous high to low transition.\n"); /* Advance beyond previous high to low transition. */ timings[channel][group].t += 2; + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); + printk(RCVEN_SPEW, "Coarsely look for DQS high.\n"); /* Coarsely look for DQS high. */ find_dqs_high(channel, group, timings, lane_map); + printk(RCVEN_SPEW, "Go back.\n"); /* Go back and perform finer search. */ rec_quarter_backstep(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); + + printk(RCVEN_SPEW, "Perform finer DQS high search.\n"); while (!read_dqs_level(channel, lane_map[group][0]) || !read_dqs_level(channel, lane_map[group][1])) { + rec_smallest_step(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void find_preamble(const int channel, const int group, rec_timing_t timings[][4], const char lane_map[][2]) { + printk(RCVEN_SPEW, "BEGIN %s\n" __func__); + + printk(RCVEN_SPEW, "Look for DQS low, backstepping.\n"); /* Look for DQS low, backstepping. */ while (read_dqs_level(channel, lane_map[group][0]) || read_dqs_level(channel, lane_map[group][1])) { + rec_full_backstep(&timings[channel][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(channel, group, timings); } + printk(RCVEN_SPEW, "FINISH %s\n" __func__); } static void receive_enable_calibration(const timings_t *const timings, @@ -213,11 +316,13 @@ dimms[0].card_type == 0xf, dimms[1].card_type == 0xf, }; + printk(RCVEN_SPEW, "cardF: ch0 = %d, ch1 = %d.\n", cardF[0], cardF[1]); - const unsigned int t_bound = - (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12; - const unsigned int p_bound = - (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; + const unsigned int t_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12; + const unsigned int p_bound = (timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1; + + printk(RCVEN_SPEW, "TAP bound = %u\n", t_bound); + printk(RCVEN_SPEW, "PI bound = %u\n", p_bound); rec_timing_t rec_timings[2][4] = { { @@ -233,35 +338,61 @@ } }; + printk(RCVEN_SPEW, "BEGIN MAIN LOOP\n"); + int ch, group; FOR_EACH_POPULATED_CHANNEL(dimms, ch) { const char (*const map)[2] = over_bytelane_map[cardF[ch]]; + printk(RCVEN_SPEW, "Begin channel %d\n", ch); + for (group = 0; group < 4; ++group) { + printk(RCVEN_SPEW, "RUNNING ON: channel %d, group %d\n", ch, group); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(ch, group, rec_timings); + find_dqs_low(ch, group, rec_timings, map); + find_dqs_edge_lowhigh(ch, group, rec_timings, map); rec_quarter_step(&rec_timings[ch][group]); + + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(ch, group, rec_timings); + find_preamble(ch, group, rec_timings, map); + find_dqs_edge_lowhigh(ch, group, rec_timings, map); + rec_half_backstep(&rec_timings[ch][group]); + + printk(RCVEN_SPEW, "Normalize in %s: " __func__); + print_timings(channel, group, rec_timings) + normalize_rec_timing(&rec_timings[ch][group]); + if (cardF[ch]) { rec_timings[ch][group].t++; + printk(RCVEN_SPEW, "%s: program timings\n" __func__); program_timing(ch, group, rec_timings); } + printk(RCVEN_SPEW, "DONE FOR: channel %d, group %d\n", ch, group); } int c_min = C_BOUND; for (group = 0; group < 4; ++group) { if (rec_timings[ch][group].c < c_min) c_min = rec_timings[ch][group].c; } + + printk(RCVEN_SPEW, "Min coarse for channel %d: %d\n", ch, c_min); + for (group = 0; group < 4; ++group) { - rec_timings[ch][group].pre = - rec_timings[ch][group].c - c_min; - rec_timings[ch][group].c = c_min; + rec_timings[ch][group].pre = rec_timings[ch][group].c - c_min; + rec_timings[ch][group].c = c_min; + + printk(RCVEN_SPEW, "%s: program final timings\n" __func__); program_timing(ch, group, rec_timings); + printk(RAM_DEBUG, "Final timings for "); printk(BIOS_DEBUG, "group %d, ch %d: %d.%d.%d.%d.%d\n", group, ch, @@ -271,18 +402,20 @@ rec_timings[ch][group].t, rec_timings[ch][group].p); } + printk(RCVEN_SPEW, "End channel %d\n", ch); } + printk(RCVEN_SPEW, "END MAIN LOOP\n"); } void raminit_receive_enable_calibration(const timings_t *const timings, const dimminfo_t *const dimms) { + printk(RCVEN_SPEW, "BEGIN rcven\n"); int ch; /* Setup group to byte-lane mapping. */ FOR_EACH_POPULATED_CHANNEL(dimms, ch) { - const char (*const map)[2] = - bytelane_map[dimms[ch].card_type == 0xf]; + const char (*const map)[2] = bytelane_map[dimms[ch].card_type == 0xf]; unsigned int group; for (group = 0; group < 4; ++group) { const unsigned int mchbar = CxRECy_MCHBAR(ch, group); @@ -299,9 +432,11 @@ MCHBAR32(0x14f0) = (MCHBAR32(0x14f0) & ~(3 << 9)) | (1 << 9); MCHBAR32(0x15f0) = (MCHBAR32(0x15f0) & ~(3 << 9)) | (1 << 9); + printk(RCVEN_SPEW, "Start calibration\n"); receive_enable_calibration(timings, dimms); MCHBAR32(0x12a4) &= ~(1 << 31); MCHBAR32(0x13a4) &= ~(1 << 31); + printk(RCVEN_SPEW, "FINISH rcven\n"); raminit_reset_readwrite_pointers(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4de1d7fc70877c11c37549cf1d723cbdcc6b1910 Gerrit-Change-Number: 34865 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: sc7180: enable bl31
by mturney mturney (Code Review) 09 Sep '20

09 Sep '20

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35504 to review the following change. Change subject: sc7180: enable bl31 ...................................................................... sc7180: enable bl31 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/28014/44 Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35504/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index df5d116..28f7522 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index f4e6f05..e47f881 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -72,7 +72,7 @@ REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000) REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) /* Various hardware/software subsystems make use of this area */ - BL31(0x85000000, 0x1A800000) + BL31(0x80C00000, 0x1A800000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) RAMSTAGE(0x9F860000, 2M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/35504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Gerrit-Change-Number: 35504 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

7 24

Change in coreboot[master]: HACK trogdor: Memlayout changed to support QcLib Size increase
by mturney mturney (Code Review) 09 Sep '20

09 Sep '20

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36277 to review the following change. Change subject: HACK trogdor: Memlayout changed to support QcLib Size increase ...................................................................... HACK trogdor: Memlayout changed to support QcLib Size increase Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36277/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index ce260aa..6ca3e95 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -59,10 +59,10 @@ REGION(ddr_training, 0x14850000, 8K, 4K) REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) - REGION(dcb, 0x14870000, 16K, 4K) - REGION(pmic, 0x14874000, 44K, 4K) - REGION(limits_cfg, 0x1487F000, 4K, 4K) - REGION(qclib, 0x14880000, 512K, 4K) + REGION(dcb, 0x1485b000, 16K, 4K) + REGION(pmic, 0x1485f000, 44K, 4K) + REGION(limits_cfg, 0x1486a000, 4K, 4K) + REGION(qclib, 0x1486b000, 596K, 4K) BSRAM_END(0x14900000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/36277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4 Gerrit-Change-Number: 36277 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: postcar_loader: Use size_t
by Patrick Rudolph (Code Review) 08 Sep '20

08 Sep '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32375 Change subject: postcar_loader: Use size_t ...................................................................... postcar_loader: Use size_t To make it easier to pop arguments from stack use size_t instead of int. This is a noop on x86_32. Change-Id: I226f79eaea425229eb2e3d9b9a312c9bf47d3b6a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar_loader.c 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32375/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 61b17a6..1cdf2db 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -310,8 +310,8 @@ struct postcar_frame { uintptr_t stack; uint32_t upper_mask; - int max_var_mtrrs; - int num_var_mtrrs; + size_t max_var_mtrrs; + size_t num_var_mtrrs; }; /* diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d62487e..a043f1b 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -25,13 +25,13 @@ #include <stage_cache.h> #include <timestamp.h> -static inline void stack_push(struct postcar_frame *pcf, uint32_t val) -{ - uint32_t *ptr; - - pcf->stack -= sizeof(val); - ptr = (void *)pcf->stack; - *ptr = val; +#define stack_push(pcf, val) \ +{ \ + typeof(val) *ptr; \ + \ + pcf->stack -= sizeof(val); \ + ptr = (void *)pcf->stack; \ + *ptr = val; \ } static void postcar_frame_prepare(struct postcar_frame *pcf) @@ -74,7 +74,7 @@ uint32_t mtrr_size; if (pcf->num_var_mtrrs >= pcf->max_var_mtrrs) { - printk(BIOS_ERR, "No more variable MTRRs: %d\n", + printk(BIOS_ERR, "No more variable MTRRs: %zd\n", pcf->max_var_mtrrs); return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I226f79eaea425229eb2e3d9b9a312c9bf47d3b6a Gerrit-Change-Number: 32375 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by Mike Banon (Code Review) 19 Aug '20

19 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33887 Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... tint: introduce the new tint build system with checksum verification Three stages of the new tint build system: 1) generate_core.sh extracts the core part from buildgcc script, most importantly the checksum calculation/verification functions. 2) tintify_core.sh adds the tint-specific footer/header to the core, such as the properties of current version including its checksum. 3) tint.sh - generated and "tintified" core script - builds a tint. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I20d7cd477595aa73f3cab9c78235f4de9813b989 --- M payloads/external/tint/Makefile A payloads/external/tint/generate_core.sh R payloads/external/tint/tint-0.04-nmu1_libpayload.patch A payloads/external/tint/tintify_core.sh 4 files changed, 252 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33887/1 diff --git a/payloads/external/tint/Makefile b/payloads/external/tint/Makefile index 253bfea..95cbd87 100644 --- a/payloads/external/tint/Makefile +++ b/payloads/external/tint/Makefile @@ -1,5 +1,25 @@ -project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.04+nmu1.tar.gz -archive_name=tint_0.04+nmu1.tar.gz +# +# TINT build system - helps to securely download TINT with a checksum verification and build it. +# + +# +# Properties of the current TINT version +# + +TINT_VERSION=0.04-nmu1 +TINT_EXT_VERSION=0.04+nmu1 +TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.t…" +TINT_ARCHIVE="tint_${TINT_VERSION}.tar.gz" +TINT_DIR="tint-${TINT_VERSION}" +TINT_CHECKSUM="7fcaa428c6d0de7096d1e4fbfd14848096ae5aad" + +# +# Locations of the input/output scripts +# + +buildgcc="./../../../util/crossgcc/buildgcc" +corescript="./core.sh" +tintified="./tint.sh" unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -10,28 +30,39 @@ all: tint -tint: patch - echo " MAKE TINT " - $(MAKE) -C tint +################################################################################ +# +# Three stages of TINT build system: +# +# 1) generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# 2) tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current version including its checksum. +# +# 3) tint.sh - generated and "tintified" core script - builds a TINT. +# +################################################################################ -patch: download - cd tint; \ - if [ -e debian ]; then \ - rm -rf debian typedefs.h Makefile; \ - touch Makefile; \ - patch -l -p1 < ../libpayload_tint.patch; \ - fi - -download: - test -d tint || { wget $(project_url); \ - tar -xvf $(archive_name); \ - rm $(archive_name); \ - mv tint-0.04+nmu1 tint; } +tint: + if [ ! -f ${tintified} ]; then \ + chmod +x "./generate_core.sh" ; \ + "./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \ + chmod +x "./tintify_core.sh" ; \ + "./tintify_core.sh" ${corescript} ${tintified} \ + ${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_CHECKSUM} ; \ + fi ; \ + chmod +x ${tintified} + ${tintified} clean: - test -d tint && $(MAKE) -C tint clean || exit 0 + test -d "./tint/" && $(MAKE) -C "./tint/" clean || exit 0 distclean: - rm -rf tint + rm -rf "./tint/" + rm -f ${corescript} + rm -f ${tintified} -.PHONY: download patch tint clean distclean +.PHONY: tint clean distclean + +# diff --git a/payloads/external/tint/generate_core.sh b/payloads/external/tint/generate_core.sh new file mode 100755 index 0000000..bb0de2d --- /dev/null +++ b/payloads/external/tint/generate_core.sh @@ -0,0 +1,102 @@ +#!/bin/sh +# +# generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +############################################################################## +# +# USAGE: +# ./generate_core.sh <buildgcc> <corescript> prepare_before_patch +# where +# buildgcc - path to input buildgcc script +# corescript - path to output core part script +# prepare_before_patch - optional argument to insert prepare_${package} +# call into the unpack_and_patch function, e.g. +# for removing some files with rm command +# in order to reduce the size of patch file +# +############################################################################## + +buildgcc="$1" +corescript="$2" +prepare_before_patch="$3" + +# +# Imports the source file fragment between start and end into the +# destination file, optionally excluding the last line if not needed +# + +import_from_file() { + source="$1" + destination="$2" + start="$3" + end="$4" + last_line_disabled="$5" + if [ -z "${last_line_disabled}" ] ; then + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" "$source" >> "$destination" + else + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" "$source" >> "$destination" + fi +} + +# +# Import the color defines together with UNAME/HALT_FOR_TOOLS variables +# + +import_from_file "$buildgcc" "$corescript" "red=" "HALT_FOR_TOOLS=0" || exit "$?" + +# +# Import the core functions +# + +FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" + +for F in $FUNCTIONS ; do + import_from_file "$buildgcc" "$corescript" "$F()" "}" || exit "$?" +done + +# +# Import a fragment where we find tar/patch/make and other essential tools +# + +import_from_file "$buildgcc" "$corescript" "# Find all the required tools" "# Allow" "last_line_disabled" || exit "$?" + +# +# Import a fragment with conditional exit if some required tools were not found +# + +import_from_file "$buildgcc" "$corescript" "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" + +# +# Avoid the unnecessary subdirectories holding a single file each +# + +sed -i -e "s/patches\///g" "$corescript" +sed -i -e "s/sum\///g" "$corescript" +sed -i -e "s/tarballs\///g" "$corescript" +sed -i -e "s/cd tarballs || exit 1//g" "$corescript" +sed -i -e "s/cd \.\.//g" "$corescript" + +# +# Get the known checksum without using a dedicated single-line file +# + +sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" "$corescript" + +# +# Update the paths printed at the error messages +# + +sed -i -e "s/util\/crossgcc\///g" "$corescript" + +# +# Insert prepare_${package} function call between the unpack and patch operations +# + +if [ ! -z "${prepare_before_patch}" ] ; then + sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript" +fi + +# diff --git a/payloads/external/tint/libpayload_tint.patch b/payloads/external/tint/tint-0.04-nmu1_libpayload.patch similarity index 100% rename from payloads/external/tint/libpayload_tint.patch rename to payloads/external/tint/tint-0.04-nmu1_libpayload.patch diff --git a/payloads/external/tint/tintify_core.sh b/payloads/external/tint/tintify_core.sh new file mode 100755 index 0000000..77abc14 --- /dev/null +++ b/payloads/external/tint/tintify_core.sh @@ -0,0 +1,98 @@ +#!/bin/sh +# +# tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current TINT version including its checksum. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +################################################################################ +# +# USAGE: +# ./tintify_core.sh <corescript> <tintified> \ +# <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> +# where +# corescript - path to input core script +# tintified - path to output tint script +# +################################################################################ + +corescript="$1" +tintified="$2" + +# +# TINT-specific header +# + +# +# Insert the properties of the current TINT version +# + +echo "#!/bin/sh" > "$tintified" +echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified" +echo "TINT_ARCHIVE=${4}" >> "$tintified" +echo "TINT_DIR=${5}" >> "$tintified" +echo "TINT_CHECKSUM=${6}" >> "$tintified" + +# +# Add the replace_plus_with_minus() function - needed to fix the version number +# + +echo "replace_plus_with_minus() {" >> "$tintified" +echo "for x in *\"+\"*; do" >> "$tintified" +echo "y=\$(printf %sa \"\$x\" | tr \"+\" \"-\")" >> "$tintified" +echo "mv -- \"\$x\" \"\${y%a}\"" >> "$tintified" +echo "done" >> "$tintified" +echo "}" >> "$tintified" + +# +# Add the prepare_TINT() function, it will remove the unneeded debian directory +# as well as typedefs.h and old Makefile to significantly reduce the patch size +# + +echo "prepare_TINT() {" >> "$tintified" +echo "replace_plus_with_minus" >> "$tintified" +echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ] ; then" >> "$tintified" +echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "touch ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "fi" >> "$tintified" +echo "}" >> "$tintified" + +# +# Importing the core script +# + +cat "$corescript" >> "$tintified" + +# +# download() function adjustments - became necessary after a version number fix +# + +sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" "$tintified" +sed -i -e "s/downloading from \$archive/&_link/g" "$tintified" +sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" "$tintified" + +# +# TINT-specific footer +# + +echo "if [ ! -d tint ] ; then" >> "$tintified" + +echo "printf \"Downloading and verifying TINT tarball ... \\n\"" >> "$tintified" +echo "download TINT || exit \"\$?\"" >> "$tintified" +echo "verify_hash TINT \${TINT_CHECKSUM} || exit \"\$?\"" >> "$tintified" +echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "printf \"Unpacking and patching TINT... \\n\"" >> "$tintified" +echo "unpack_and_patch TINT || exit 1" >> "$tintified" +echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "mv ./\${TINT_DIR} ./tint" >> "$tintified" +echo "fi" >> "$tintified" + +echo "printf \"Building TINT ... \\n\"" >> "$tintified" +echo "make -C ./tint" >> "$tintified" +echo "printf \"TINT built ... \${green}ok\${NC}\\n\"" >> "$tintified" + +chmod +x "$tintified" + +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20d7cd477595aa73f3cab9c78235f4de9813b989 Gerrit-Change-Number: 33887 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: configs: Build test experimental x86_64 code
by Patrick Rudolph (Code Review) 19 Aug '20

19 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31472 Change subject: configs: Build test experimental x86_64 code ...................................................................... configs: Build test experimental x86_64 code Add additional build config to test qemu-i440fx x86_64 code. Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A configs/config.emulation_qemu_x86_i440fx_x86_64 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31472/1 diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 new file mode 100644 index 0000000..0ddb3f1 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -0,0 +1 @@ +CONFIG_CPU_QEMU_X86_64=y -- To view, visit https://review.coreboot.org/c/coreboot/+/31472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16 Gerrit-Change-Number: 31472 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram
by Arthur Heymans (Code Review) 17 Aug '20

17 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37212 ) Change subject: arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram ...................................................................... arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram INVD is called below so if postcar is running in a cached environment it needs to happen. NOTE: postcar cannot execute in a cached environment if clflush is not supported! Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/exit_car.S 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37212/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 8c28784..ceb0321 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -38,7 +38,14 @@ movl 4(%esp), %eax movl %eax, _cbmem_top_ptr #endif + /* Make sure _cbmem_top_ptr hits dram before invd */ + movl $1, %eax + cpuid + btl $19, %edx + jz skip_clflush + clflush _cbmem_top_ptr +skip_clflush: /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car -- To view, visit https://review.coreboot.org/c/coreboot/+/37212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc Gerrit-Change-Number: 37212 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: cpu/x86/mtrr: Add helper function to cache cbmem in romstage
by Arthur Heymans (Code Review) 07 Aug '20

07 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37199 ) Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ...................................................................... cpu/x86/mtrr: Add helper function to cache cbmem in romstage Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB. Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR. Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/1 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..2658388 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -11,3 +11,5 @@ bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c + +romstage-y += cbmem_cache.c \ No newline at end of file diff --git a/src/cpu/x86/mtrr/cbmem_cache.c b/src/cpu/x86/mtrr/cbmem_cache.c new file mode 100644 index 0000000..8753e9e --- /dev/null +++ b/src/cpu/x86/mtrr/cbmem_cache.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <stage_cache.h> +#include <cpu/x86/cache.h> +#include <arch/cpu.h> +#include <program_loading.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> + +void setup_romstage_wb_cbmem_cache(void) +{ + int mtrr_num = get_free_var_mtrr(); + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t stage_cache_base, stage_cache_end; + size_t stage_cache_size; + size_t stage_cache_mtrr_size = 4 * KiB; + + printk(BIOS_DEBUG, "Setting MTRR's for cbmem and stage cache\n"); + + /* postcar will do invd so we need a way to make sure things are in memory + which is only possible if clflush is supported. */ + if (!clflush_supported()) { + printk(BIOS_WARNING, "CLFLUSH not supported, not caching cbmem!\n"); + if (CONFIG(COMPRESS_POSTCAR)) + printk(BIOS_WARNING, "Decompressing POSTCAR will be slow!\n"); + + return; + } + if (mtrr_num < 0) { + printk(BIOS_DEBUG, "No MTRR free to cache cbmem\n!"); + return; + } + /* Often cbmem_top is chosen to be aligned already to optimize MTRR + usage in the postcar frame so this should not be too worrisome. */ + top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB); + set_var_mtrr(mtrr_num, top_of_ram - 4 * MiB, 4 * MiB, MTRR_TYPE_WRBACK); + + if (!CONFIG(TSEG_STAGE_CACHE)) + return; + mtrr_num = get_free_var_mtrr(); + if (mtrr_num < 0) { + printk(BIOS_DEBUG, "No MTRR free to cache TSEG stage cache\n!"); + return; + } + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + stage_cache_end = stage_cache_base + stage_cache_size; + + /* Find MTRR to cover TSEG stage cache */ + while (1) { + /* Do some sanity check before it gets absurdly. */ + if (stage_cache_mtrr_size > 64 * MiB) { + printk(BIOS_WARNING, "Not caching stage cache, too large\n"); + return; + } + if (ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size) + + stage_cache_mtrr_size > stage_cache_end) + break; + stage_cache_mtrr_size *= 2; + } + set_var_mtrr(mtrr_num, ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size), + stage_cache_mtrr_size, MTRR_TYPE_WRBACK); +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..abdecfe 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -95,6 +95,8 @@ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void); +void setup_romstage_wb_cbmem_cache(void); + /* Insert a temporary MTRR range for the duration of coreboot's runtime. * This function needs to be called after the first MTRR solution is derived. */ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type); -- To view, visit https://review.coreboot.org/c/coreboot/+/37199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Gerrit-Change-Number: 37199 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: payload/seabios: Fix CBFS location on APL platform
by Felix Singer (Code Review) 04 Aug '20

04 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32327 Change subject: payload/seabios: Fix CBFS location on APL platform ...................................................................... payload/seabios: Fix CBFS location on APL platform Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M payloads/external/SeaBIOS/Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32327/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..594d37a 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -39,6 +39,9 @@ config: checkout echo " CONFIG SeaBIOS $(TAG-y)" echo "CONFIG_COREBOOT=y" > seabios/.config +ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) + echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config +endif ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config -- To view, visit https://review.coreboot.org/c/coreboot/+/32327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Gerrit-Change-Number: 32327 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

8 32

Change in coreboot[master]: cpu/x86: Define INSTALL_SMM option
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34257 ) Change subject: cpu/x86: Define INSTALL_SMM option ...................................................................... cpu/x86: Define INSTALL_SMM option Change-Id: Ibe827193527b7e16a3360b92bc0be25ceec8d1e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/smm/smm_init.c M src/cpu/x86/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/smm/Makefile.inc M src/drivers/elog/Kconfig M src/drivers/spi/Kconfig M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c 8 files changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34257/1 diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 60e506c..612557e 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -23,6 +23,16 @@ #include <cpu/x86/smm.h> #include <string.h> +static void smm_install(void) +{ + enable_cache(); + /* copy the real SMM handler */ + memcpy((void *)SMM_BASE, _binary_smm_start, + _binary_smm_end - _binary_smm_start); + wbinvd(); + disable_cache(); +} + void smm_init(void) { msr_t msr, syscfg_orig, mtrr_aseg_orig; @@ -55,12 +65,8 @@ msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - enable_cache(); - /* copy the real SMM handler */ - memcpy((void *)SMM_BASE, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); - disable_cache(); + if (CONFIG(INSTALL_SMM)) + smm_install(); /* Restore SYSCFG and MTRR */ wrmsr(SYSCFG_MSR, syscfg_orig); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index caee5db..25eee72 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -86,6 +86,11 @@ bool default y +config INSTALL_SMM + bool + default y + depends on HAVE_SMI_HANDLER + config HAVE_SMI_HANDLER bool default n diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9528149..7855ebf 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -789,6 +789,9 @@ if (mp_state.ops.adjust_smm_params != NULL) mp_state.ops.adjust_smm_params(&smm_params, 1); + if (!CONFIG(INSTALL_SMM)) + return -1; + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08lx\n", smbase); if (smm_load_module((void *)smbase, smsize, &smm_params)) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 5c7aab3..57013da 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -36,7 +36,7 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +ifeq ($(CONFIG_INSTALL_SMM),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig index 4a66e78..7848f7b 100644 --- a/src/drivers/elog/Kconfig +++ b/src/drivers/elog/Kconfig @@ -43,7 +43,7 @@ This option will enable event logging from the preram stage. config ELOG_GSMI - depends on HAVE_SMI_HANDLER + depends on INSTALL_SMM bool "SMI interface to write and clear event log" select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP default n diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b15a502..3013087 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -63,7 +63,7 @@ config SPI_FLASH_SMM bool - depends on HAVE_SMI_HANDLER + depends on INSTALL_SMM help Select this option if you want SPI flash support in SMM. diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 7dfed9d..86e75d0 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -328,7 +328,8 @@ void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + if (CONFIG(INSTALL_SMM)) + smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ smm_relocate(); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5d898cc..d50432b 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -157,7 +157,8 @@ void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + if (CONFIG(INSTALL_SMM)) + smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ smm_relocate(); -- To view, visit https://review.coreboot.org/c/coreboot/+/34257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe827193527b7e16a3360b92bc0be25ceec8d1e6 Gerrit-Change-Number: 34257 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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