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Change in coreboot[master]: cpu/x86/smm/smihandler.c: Clean up unused save state handler
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37009 ) Change subject: cpu/x86/smm/smihandler.c: Clean up unused save state handler ...................................................................... cpu/x86/smm/smihandler.c: Clean up unused save state handler This was only used to print out the save state which is now done by the common save state handler. Change-Id: I98b17ab370ff58e0444cda1f8bfc05ea38ec6b71 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c 1 file changed, 0 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37009/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 0adf591..da1cd7b 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -17,32 +17,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/x86/smi_deprecated.h> -#include <cpu/amd/amd64_save_state.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/x86/legacy_save_state.h> #if CONFIG(SPI_FLASH_SMM) #include <spi-generic.h> #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -126,12 +105,6 @@ outl(pci_orig, 0xcf8); } -static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) -{ - base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); - return (void *)base; -} - uint8_t *smm_get_save_state_top(int cpu) { const uint32_t smm_base = 0xa0000; @@ -148,8 +121,6 @@ void smi_handler(u32 smm_revision) { unsigned int node; - smm_state_save_area_t state_save; - u32 smm_base = 0xa0000; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -177,42 +148,6 @@ smm_save_state_ops_init(); - switch (smm_revision) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); - /* Don't release lock, so no further SMI will happen, - * if we don't handle it anyways. - */ - return; - } - /* Allow drivers to initialize variables in SMM context. */ if (do_driver_init) { #if CONFIG(SPI_FLASH_SMM) -- To view, visit https://review.coreboot.org/c/coreboot/+/37009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b17ab370ff58e0444cda1f8bfc05ea38ec6b71 Gerrit-Change-Number: 37009 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]cpu/x86/smm: Add a unified way of handling save_states
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36661 ) Change subject: [RFC]cpu/x86/smm: Add a unified way of handling save_states ...................................................................... [RFC]cpu/x86/smm: Add a unified way of handling save_states This adds common code to handle SMM save states based on the SMM revision. example: SMM code needing access to eax from save state would do the following struct smm_save_state_ops ops = get_save_state_ops(); uint64_t rax; int node; for (node = 0; node < CONFIG_MAX_CPUS; node++) { if (ops.get_reg(node, RAX, &rax)) error... rax &= MAX_UINT32; do_stuff... } UNTESTED. Change-Id: Ide7ccc44dbcc864e70463ef318dc1858b51183dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/smm_save_state.c M src/include/cpu/x86/smm.h 3 files changed, 311 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36661/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..6c74c88 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -47,6 +47,7 @@ smmstub-y += smm_stub.S smm-y += smm_module_handler.c +smm-y += smm_save_state.c ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual diff --git a/src/cpu/x86/smm/smm_save_state.c b/src/cpu/x86/smm/smm_save_state.c new file mode 100644 index 0000000..8a7f347 --- /dev/null +++ b/src/cpu/x86/smm/smm_save_state.c @@ -0,0 +1,283 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <string.h> +#include <cpu/amd/amd64_save_state.h> +#include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/legacy_save_state.h> + +static const struct smm_runtime *smm_runtime; +static const struct smm_save_state_ops *ops; + +static void *smm_get_save_state_top(int cpu) +{ + char *base; + + /* This function assumes all save states start at top of default + * SMRAM size space and are staggered down by save state size. */ + base = (void *)smm_runtime->smbase; + base += SMM_DEFAULT_SIZE; + base -= cpu * smm_runtime->save_state_size; + + return base; +} + +static uint32_t smm_get_revision(uint32_t base) +{ + uint8_t *top = (uint8_t *)smm_get_save_state_top(0); + /* SMM revision offset from top */ + return *(uint32_t *)(top - (0x8000 - 0x7efc)); +} + +const struct smm_save_state_ops *get_save_state_ops(void) +{ + return ops; +} + +/* We only have 32bit registers so we'll fake 64bit registers with 0 + in the upper part. */ +static void *legacy_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + legacy_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL; + base = smm_get_save_state_top(cpu); + base -= sizeof(legacy_smm_state_save_area_t); + state = (legacy_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->eax; + case RBX: + return &state->ebx; + case RCX: + return &state->ecx; + case RDX: + return &state->edx; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static void *em64t100_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + em64t100_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL;; + base = smm_get_save_state_top(cpu); + base -= sizeof(em64t100_smm_state_save_area_t); + state = (em64t100_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->rax; + case RBX: + return &state->rbx; + case RCX: + return &state->rcx; + case RDX: + return &state->rdx; + case IO_MISC_INFO: + return &state->io_misc_info; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static void *em64t101_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + em64t101_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL; + base = smm_get_save_state_top(cpu); + base -= sizeof(em64t101_smm_state_save_area_t); + state = (em64t101_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->rax; + case RBX: + return &state->rbx; + case RCX: + return &state->rcx; + case RDX: + return &state->rdx; + case IO_MISC_INFO: + return &state->io_misc_info; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static void *amd64_get_reg_ptr(unsigned int cpu, enum smm_reg reg) +{ + uint8_t *base; + amd64_smm_state_save_area_t *state; + if (cpu > CONFIG_MAX_CPUS) + return NULL; + base = smm_get_save_state_top(cpu); + base -= sizeof(amd64_smm_state_save_area_t); + state = (amd64_smm_state_save_area_t *)(base); + switch (reg) { + case RAX: + return &state->rax; + case RBX: + return &state->rbx; + case RCX: + return &state->rcx; + case RDX: + return &state->rdx; + case SMM_IO_TRAP_OFFSET: + return &state->smm_io_trap_offset; + default: + break; + } + printk(BIOS_DEBUG, "SMM get_reg: Unknown reg requested\n"); + return NULL; +} + +static int ss_get_helper(unsigned int cpu, enum smm_reg reg, void *val, size_t val_size, + void *(*get_reg_ptr_fn)(unsigned int, enum smm_reg)) +{ + void *ss_entry = get_reg_ptr_fn(cpu, reg); + if (!ss_entry) + return -1; + memcpy(val, ss_entry, val_size); + return 0; +} + +static int ss_set_helper(unsigned int cpu, enum smm_reg reg, void *val, size_t val_size, + void *(*get_reg_ptr_fn)(unsigned int, enum smm_reg)) +{ + void *ss_entry = get_reg_ptr_fn(cpu, reg); + if (!ss_entry) + return -1; + memcpy(ss_entry, val, val_size); + return 0; +} + +static int legacy_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(uint32_t), legacy_get_reg_ptr); +} + +static int legacy_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(uint32_t), legacy_get_reg_ptr); +} + +static int em64t100_get_io_misc_info(unsigned int cpu, uint32_t *misc_info) +{ + return ss_get_helper(cpu, IO_MISC_INFO, misc_info, sizeof(*misc_info), em64t100_get_reg_ptr); +} + +static int em64t100_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(*val), em64t100_get_reg_ptr); +} + +static int em64t100_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(val), em64t100_get_reg_ptr); +} + +static int em64t101_get_io_misc_info(unsigned int cpu, uint32_t *misc_info) +{ + return ss_get_helper(cpu, IO_MISC_INFO, misc_info, sizeof(*misc_info), em64t101_get_reg_ptr); +} + +static int em64t101_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(*val), em64t101_get_reg_ptr); +} + +static int em64t101_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(val), em64t101_get_reg_ptr); +} + +static int amd64_get_io_trap(unsigned int cpu, uint32_t *io_trap) +{ + return ss_get_helper(cpu, SMM_IO_TRAP_OFFSET, io_trap, sizeof(*io_trap), amd64_get_reg_ptr); +} + +static int amd64_get_reg(unsigned int cpu, enum smm_reg reg, uint64_t *val) +{ + return ss_get_helper(cpu, reg, val, sizeof(*val), amd64_get_reg_ptr); +} + +static int amd64_set_reg(unsigned int cpu, enum smm_reg reg, uint64_t val) +{ + return ss_set_helper(cpu, reg, &val, sizeof(val), amd64_get_reg_ptr); +} + +static const struct smm_save_state_ops legacy_save_state_ops = { + .get_reg = legacy_get_reg, + .set_reg = legacy_set_reg, +}; + +static const struct smm_save_state_ops em64t100_save_state_ops = { + .get_io_misc_info = em64t100_get_io_misc_info, + .get_reg = em64t100_get_reg, + .set_reg = em64t100_set_reg, +}; + +static const struct smm_save_state_ops em64t101_save_state_ops = { + .get_io_misc_info = em64t101_get_io_misc_info, + .get_reg = em64t101_get_reg, + .set_reg = em64t101_set_reg, +}; + +static const struct smm_save_state_ops amd64_save_state_ops = { + .get_io_trap = amd64_get_io_trap, + .get_reg = amd64_get_reg, + .set_reg = amd64_set_reg, +}; + +int smm_save_state_ops_init(const struct smm_runtime *runtime) +{ + uint32_t smm_revision = smm_get_revision(runtime->smbase); + smm_runtime = runtime; + + switch (smm_revision) { + case 0x00030002: + case 0x00030007: + ops = &legacy_save_state_ops; + return 0; + break; + case 0x00030100: + ops = &em64t100_save_state_ops; + return 0; + break; + case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ + ops = &em64t101_save_state_ops; + return 0; + case 0x00020064: + case 0x00030064: + ops = &amd64_save_state_ops; + return 0; + default: + printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); + printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + return 1; + } +} + diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..b389e77 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -95,6 +95,33 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); + +enum smm_reg { + RAX, + RBX, + RCX, + RDX, + IO_MISC_INFO, + SMM_IO_TRAP_OFFSET, +}; + +/* SMM save state ops. + WARNING1: This does not take into account CPUs which are configured to not + save their state to RAM. Returns -1 on failure, 0 on succes. */ +struct smm_save_state_ops { + /* Intel 64: misc info */ + int (*get_io_misc_info)(unsigned int cpu, uint32_t *misc_info); + /* AMD64: smm_io_trap */ + int (*get_io_trap)(unsigned int cpu, uint32_t *misc_info); + /* return value of the requested register from + * SMM Save State Area. + */ + int (*get_reg)(unsigned int cpu, enum smm_reg reg, uint64_t *val); + int (*set_reg)(unsigned int cpu, enum smm_reg reg, uint64_t val); +}; + +const struct smm_save_state_ops *get_save_state_ops(void); +int smm_save_state_ops_init(const struct smm_runtime *runtime); #endif /* __SMM__ */ /* SMM Module Loading API */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7ccc44dbcc864e70463ef318dc1858b51183dc Gerrit-Change-Number: 36661 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Rename save state accessors
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37110 ) Change subject: soc/intel/common: Rename save state accessors ...................................................................... soc/intel/common: Rename save state accessors This avoids name collision with follow-up code that intends to reuse these names and replace this code. Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 8 files changed, 71 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37110/1 diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..f26d8ba 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -29,7 +29,7 @@ return 1; } -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t100_smm_ops; } diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241..1d57c7e 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -32,7 +32,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index d8520f1..afe8505 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -25,32 +25,32 @@ /* * The register value is used with get_reg and set_reg */ -enum smm_reg { - RAX, - RBX, - RCX, - RDX, +enum intel_smm_reg { + SMM_RAX, + SMM_RBX, + SMM_RCX, + SMM_RDX, }; -struct smm_save_state_ops { +struct intel_smm_save_state_ops { /* return io_misc_info from SMM Save State Area */ uint32_t (*get_io_misc_info)(void *state); /* return value of the requested register from * SMM Save State Area */ - uint64_t (*get_reg)(void *state, enum smm_reg reg); + uint64_t (*get_reg)(void *state, enum intel_smm_reg reg); - void (*set_reg)(void *state, enum smm_reg reg, uint64_t val); + void (*set_reg)(void *state, enum intel_smm_reg reg, uint64_t val); }; -typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops); +typedef void (*smi_handler_t)(const struct intel_smm_save_state_ops *save_state_ops); /* * SOC SMI Handler has to provide this structure which has methods to access * the SOC specific SMM Save State Area */ -const struct smm_save_state_ops *get_smm_save_state_ops(void); +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void); /* * southbridge_smi should be defined inside SOC specific code and should have @@ -67,7 +67,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -75,7 +75,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -83,7 +83,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -91,7 +91,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -99,7 +99,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -107,14 +107,14 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -122,7 +122,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -130,7 +130,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * This function should be implemented in SOC specific code to handle @@ -138,7 +138,7 @@ * soc/intel/common/block/smm/smihandler.c */ void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops); + const struct intel_smm_save_state_ops *save_state_ops); /* * Returns gnvs pointer within SMM context @@ -173,7 +173,7 @@ /* Mainboard handler for ESPI EMIs */ void mainboard_smi_espi_handler(void); -extern const struct smm_save_state_ops em64t100_smm_ops; +extern const struct intel_smm_save_state_ops em64t100_smm_ops; -extern const struct smm_save_state_ops em64t101_smm_ops; +extern const struct intel_smm_save_state_ops em64t101_smm_ops; #endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0581d23..d76fb0a 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -87,7 +87,7 @@ /* Common Functions */ -static void *find_save_state(const struct smm_save_state_ops *save_state_ops, +static void *find_save_state(const struct intel_smm_save_state_ops *save_state_ops, int cmd) { int node; @@ -111,7 +111,7 @@ if (((io_misc_info >> 16) & 0xff) != APM_CNT) continue; /* Check AL against the requested command */ - reg_al = save_state_ops->get_reg(state, RAX); + reg_al = save_state_ops->get_reg(state, SMM_RAX); if (reg_al != cmd) continue; break; @@ -179,7 +179,7 @@ void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t reg32; uint8_t slp_typ; @@ -275,7 +275,7 @@ } static void southbridge_smi_gsmi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u8 sub_command, ret; void *io_smi = NULL; @@ -285,19 +285,19 @@ if (!io_smi) return; /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) + sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX); /* drivers/elog/gsmi.c */ ret = gsmi_exec(sub_command, &reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + save_state_ops->set_reg(io_smi, SMM_RAX, ret); } static void southbridge_smi_store( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u8 sub_command, ret; void *io_smi; @@ -307,14 +307,14 @@ if (!io_smi) return; /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff; + sub_command = (save_state_ops->get_reg(io_smi, SMM_RAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + reg_ebx = save_state_ops->get_reg(io_smi, SMM_RBX); /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + save_state_ops->set_reg(io_smi, SMM_RAX, ret); } static void finalize(void) @@ -336,7 +336,7 @@ } void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint8_t reg8; void *state = NULL; @@ -379,7 +379,7 @@ state = find_save_state(save_state_ops, reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); + uint32_t reg_ebx = save_state_ops->get_reg(state, SMM_RBX); gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx; smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); @@ -402,7 +402,7 @@ } void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint16_t pm1_sts = pmc_clear_pm1_status(); u16 pm1_en = pmc_read_pm1_enable(); @@ -420,13 +420,13 @@ } void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { pmc_clear_all_gpe_status(); } void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t tco_sts = pmc_clear_tco_status(); @@ -443,7 +443,7 @@ } void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { uint32_t reg32; @@ -456,7 +456,7 @@ } void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { struct gpi_status smi_sts; @@ -468,7 +468,7 @@ } void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { mainboard_smi_espi_handler(); } @@ -477,7 +477,7 @@ { int i; uint32_t smi_sts; - const struct smm_save_state_ops *save_state_ops; + const struct intel_smm_save_state_ops *save_state_ops; /* * We need to clear the SMI status registers, or we won't see what's @@ -519,22 +519,22 @@ return smm_state->io_misc_info; } -static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) +static uint64_t em64t100_smm_save_state_get_reg(void *state, enum intel_smm_reg reg) { uintptr_t value = 0; em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: value = smm_state->rax; break; - case RBX: + case SMM_RBX: value = smm_state->rbx; break; - case RCX: + case SMM_RCX: value = smm_state->rcx; break; - case RDX: + case SMM_RDX: value = smm_state->rdx; break; default: @@ -543,21 +543,21 @@ return value; } -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, +static void em64t100_smm_save_state_set_reg(void *state, enum intel_smm_reg reg, uint64_t val) { em64t100_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: smm_state->rax = val; break; - case RBX: + case SMM_RBX: smm_state->rbx = val; break; - case RCX: + case SMM_RCX: smm_state->rcx = val; break; - case RDX: + case SMM_RDX: smm_state->rdx = val; break; default: @@ -571,22 +571,22 @@ return smm_state->io_misc_info; } -static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) +static uint64_t em64t101_smm_save_state_get_reg(void *state, enum intel_smm_reg reg) { uintptr_t value = 0; em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: value = smm_state->rax; break; - case RBX: + case SMM_RBX: value = smm_state->rbx; break; - case RCX: + case SMM_RCX: value = smm_state->rcx; break; - case RDX: + case SMM_RDX: value = smm_state->rdx; break; default: @@ -595,21 +595,21 @@ return value; } -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, +static void em64t101_smm_save_state_set_reg(void *state, enum intel_smm_reg reg, uint64_t val) { em64t101_smm_state_save_area_t *smm_state = state; switch (reg) { - case RAX: + case SMM_RAX: smm_state->rax = val; break; - case RBX: + case SMM_RBX: smm_state->rbx = val; break; - case RCX: + case SMM_RCX: smm_state->rcx = val; break; - case RDX: + case SMM_RDX: smm_state->rdx = val; break; default: @@ -617,13 +617,13 @@ } } -const struct smm_save_state_ops em64t100_smm_ops = { +const struct intel_smm_save_state_ops em64t100_smm_ops = { .get_io_misc_info = em64t100_smm_save_state_get_io_misc_info, .get_reg = em64t100_smm_save_state_get_reg, .set_reg = em64t100_smm_save_state_set_reg, }; -const struct smm_save_state_ops em64t101_smm_ops = { +const struct intel_smm_save_state_ops em64t101_smm_ops = { .get_io_misc_info = em64t101_smm_save_state_get_io_misc_info, .get_reg = em64t101_smm_save_state_get_reg, .set_reg = em64t101_smm_save_state_set_reg, diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 974c489..b7e25e4 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -56,7 +56,7 @@ } void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -68,7 +68,7 @@ } void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops) + const struct intel_smm_save_state_ops *save_state_ops) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_cycle; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4..039900e 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -29,7 +29,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..50a82f9 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -20,7 +20,7 @@ #include <intelblocks/smihandler.h> #include <soc/pm.h> -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07bea..25bdacc 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -29,7 +29,7 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) +const struct intel_smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24ab09e7f35bb231a8069905860c612d5e35454 Gerrit-Change-Number: 37110 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: cpu/x86/smm: Add a helper function returning top of save state
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37008 ) Change subject: cpu/x86/smm: Add a helper function returning top of save state ...................................................................... cpu/x86/smm: Add a helper function returning top of save state Some entries like smm base and smm revision have a fixed location in the save w.r.t. the save state top. Change-Id: I82dadcb966ee686c1652c7a1298dcb9938ae888c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c M src/cpu/x86/smm/smm_module_handler.c M src/include/cpu/x86/smm.h 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37008/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 20417d1..79a3936 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -132,6 +132,13 @@ return (void *)base; } +uint8_t *smm_get_save_state_top(int cpu) +{ + const uint32_t smm_base = 0xa0000; + + return (uint8_t *)smm_base + SMM_ENTRY_OFFSET * 2 - (cpu * 0x400); +} + /** * @brief Interrupt handler for SMI# * diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index bd4d48c..80bff9f 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -114,6 +114,19 @@ return base; } +uint8_t *smm_get_save_state_top(int cpu) +{ + uint8_t *base; + + /* This function assumes all save states start at top of default + * SMRAM size space and are staggered down by save state size. */ + base = (void *)smm_runtime->smbase; + base += SMM_DEFAULT_SIZE; + base -= cpu * smm_runtime->save_state_size; + + return base; +} + asmlinkage void smm_handler_start(void *arg) { const struct smm_module_params *p; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b1..0ade970 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -94,6 +94,7 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); +uint8_t *smm_get_save_state_top(int cpu); /* SMM Module Loading API */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82dadcb966ee686c1652c7a1298dcb9938ae888c Gerrit-Change-Number: 37008 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: HACK sdm845: Drag in all of the binary blobs
by T.Michael Turney (Code Review) 10 Nov '20

10 Nov '20

Hello T Michael Turney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32450 to review the following change. Change subject: HACK sdm845: Drag in all of the binary blobs ...................................................................... HACK sdm845: Drag in all of the binary blobs This patch is a hack until licensing issues are resolved. There is a lot of ugliness in the Makefile.inc to allow build-bot to accept this patch without having access to the binary blobs required to run on Napali hardware. Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/sdm845/Makefile.inc 1 file changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32450/1 diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 34064a1..8c64a2f 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -73,13 +73,117 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include +SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845 + BL31_MAKEARGS += PLAT=sdm845 ifeq ($(CONFIG_QC_SDI_ENABLE),y) BL31_MAKEARGS += DEBUG=1 endif +################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(SDM845_BLOB)/QcSdi.elf +qcsdi_file := $(shell ls $(QCSDI_FILE)) +ifneq (,$(findstring $(QCSDI_FILE),$(qcsdi_file))) + QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi + $(QCSDI_CBFS)-file := $(QCSDI_FILE) + $(QCSDI_CBFS)-type := stage + $(QCSDI_CBFS)-compression := none + cbfs-files-y += $(QCSDI_CBFS) +endif +endif + +################################################################################ +QCLIB_FILE := $(SDM845_BLOB)/QcLib.elf +qclib_file := $(shell ls $(QCLIB_FILE)) +ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file))) + QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib + $(QCLIB_CBFS)-file := $(QCLIB_FILE) + $(QCLIB_CBFS)-type := stage + $(QCLIB_CBFS)-compression := none + cbfs-files-y += $(QCLIB_CBFS) +endif + +################################################################################ +PMIC_FILE := $(SDM845_BLOB)/Pmic.bin +pmic_file := $(shell ls $(PMIC_FILE)) +ifneq (,$(findstring $(PMIC_FILE),$(pmic_file))) + PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg + $(PMIC_CBFS)-file := $(PMIC_FILE) + $(PMIC_CBFS)-type := raw + $(PMIC_CBFS)-compression := none + cbfs-files-y += $(PMIC_CBFS) +endif + +################################################################################ +DCB_FILE := $(SDM845_BLOB)/6000_0200_1_dcb.bin +dcb_file := $(shell ls $(DCB_FILE)) +ifneq (,$(findstring $(DCB_FILE),$(dcb_file))) + DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb + $(DCB_CBFS)-file := $(DCB_FILE) + $(DCB_CBFS)-type := raw + $(DCB_CBFS)-compression := none + cbfs-files-y += $(DCB_CBFS) +endif + +################################################################################ +AOP_FILE := $(SDM845_BLOB)/aop.mbn +aop_file := $(shell ls $(AOP_FILE)) +ifneq (,$(findstring $(AOP_FILE),$(aop_file))) + AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop + $(AOP_CBFS)-file := $(AOP_FILE) + $(AOP_CBFS)-type := payload + $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += $(AOP_CBFS) +endif + +################################################################################ +UART_FW_FILE := $(SDM845_BLOB)/uart_fw.bin +uart_fw_file := $(shell ls $(UART_FW_FILE)) +ifneq (,$(findstring $(UART_FW_FILE),$(uart_fw_file))) + UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw + $(UART_FW_CBFS)-file := $(UART_FW_FILE) + $(UART_FW_CBFS)-type := raw + $(UART_FW_CBFS)-compression := none + cbfs-files-y += $(UART_FW_CBFS) +endif + +################################################################################ +SPI_FW_FILE := $(SDM845_BLOB)/spi_fw.bin +spi_fw_file := $(shell ls $(SPI_FW_FILE)) +ifneq (,$(findstring $(SPI_FW_FILE),$(spi_fw_file))) + SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw + $(SPI_FW_CBFS)-file := $(SPI_FW_FILE) + $(SPI_FW_CBFS)-type := raw + $(SPI_FW_CBFS)-compression := none + cbfs-files-y += $(SPI_FW_CBFS) +endif + +################################################################################ +I2C_FW_FILE := $(SDM845_BLOB)/i2c_fw.bin +i2c_fw_file := $(shell ls $(I2C_FW_FILE)) +ifneq (,$(findstring $(I2C_FW_FILE),$(i2c_fw_file))) + I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw + $(I2C_FW_CBFS)-file := $(I2C_FW_FILE) + $(I2C_FW_CBFS)-type := raw + $(I2C_FW_CBFS)-compression := none + cbfs-files-y += $(I2C_FW_CBFS) +endif + +################################################################################ +QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn +qc_sec_file := $(shell ls $(QC_SEC_FILE)) +ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf + @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +else $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a Gerrit-Change-Number: 32450 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34517 ) Change subject: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides ...................................................................... soc/intel/{cnl,icl}: Enable support to configure interrupt overrides This implementation selects SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE config. It would enable support from SOC to dynamically populate the PCI IRQ routing table based on the devices enabled from the mainboard. And pass the same to FSP to configure the IRQ entries in ITSS PIRx register. The same table can be used to generate the ACPI PIRQ mapping table. Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34517/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..0283f2c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 5dca44b..79a19ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Gerrit-Change-Number: 34517 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34349 ) Change subject: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides ...................................................................... src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/fsp_params.c 4 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34349/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4235b7a..c8dfc13 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fe5b3dd..4eef58e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -408,6 +409,11 @@ configure_gspi_cs(i, config, &params->SerialIoSpiCsPolarity[0], NULL, NULL); #endif + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2261a0..d31c8eb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ed86c27..ee45024 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -241,6 +242,12 @@ params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Gerrit-Change-Number: 34349 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: src/soc/intel/*/include: Get list of devices that needs IRQ programming
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 ) Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming ...................................................................... src/soc/intel/*/include: Get list of devices that needs IRQ programming This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices. Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..ed0d09c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/cannonlake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd02934..2973e15 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/icelake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Gerrit-Change-Number: 34348 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp-car: Use the coreboot defined stack
by Arthur Heymans (Code Review) 02 Nov '20

02 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37278 ) Change subject: soc/intel/fsp-car: Use the coreboot defined stack ...................................................................... soc/intel/fsp-car: Use the coreboot defined stack The stack needs to be in the coreboot defined region to not collide with other symbols. Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37278/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index ec43311..d7ef834 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,7 +87,7 @@ jnz .halt_forever /* Setup bootblock stack */ - mov %edx, %esp + movl _ecar_stack, %esp /* coreboot assumes CAR region will be zero */ cld -- To view, visit https://review.coreboot.org/c/coreboot/+/37278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Gerrit-Change-Number: 37278 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg
by Arthur Heymans (Code Review) 30 Oct '20

30 Oct '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35872 ) Change subject: {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg ...................................................................... {soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfg The last argument for acpi_fill_mcfg is the last PCI bus, not the total number of busses. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/northbridge.c M src/soc/amd/stoneyridge/northbridge.c M src/southbridge/amd/pi/hudson/lpc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35872/1 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f9..756537b 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -167,7 +167,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..2304e73 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -183,7 +183,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 02123a1..cf73a8c 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -336,7 +336,7 @@ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER); + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Gerrit-Change-Number: 35872 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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