coreboot-gerrit November 2019

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Change in coreboot[master]: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot
by Arthur Heymans (Code Review) 19 Nov '20

19 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37281 ) Change subject: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot ...................................................................... drivers/intel/fsp1.1/car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37281/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fb39884..748c267 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -143,6 +143,11 @@ cmp $0, %eax jne halt2 + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup BSP stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Gerrit-Change-Number: 37281 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37019 ) Change subject: soc/amd/picasso: Use common SMM save state ops ...................................................................... soc/amd/picasso: Use common SMM save state ops Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37019/1 diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 39c2dfd..b04eddb 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Gerrit-Change-Number: 37019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37018 ) Change subject: soc/amd/stoneyridge: Use common SMM save state ops ...................................................................... soc/amd/stoneyridge: Use common SMM save state ops Change-Id: I2f98062dd254528c0c72e8739035c9e620a8497f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37018/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 2b88397..d2945c8 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f98062dd254528c0c72e8739035c9e620a8497f Gerrit-Change-Number: 37018 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37017 ) Change subject: soc/intel/denverton_ns: Use common SMM save state ops ...................................................................... soc/intel/denverton_ns: Use common SMM save state ops Change-Id: Ieb5baaa4e36d97414d87addf5c8e318b881e8996 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/smihandler.c 1 file changed, 36 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37017/1 diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index c292e4d..ce0022f 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> @@ -168,35 +167,39 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void finalize(void) @@ -217,7 +220,7 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); /* Emulate B2 register as the FADT / Linux expects it */ @@ -254,13 +257,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb5baaa4e36d97414d87addf5c8e318b881e8996 Gerrit-Change-Number: 37017 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37015 ) Change subject: soc/intel/common: Use common SMM save state ops ...................................................................... soc/intel/common: Use common SMM save state ops Change-Id: I656aad823a96eafb507e8b30d2177d21efcf2416 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 8 files changed, 98 insertions(+), 269 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37015/1 diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..ede073d 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -29,11 +29,6 @@ return 1; } -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t100_smm_ops; -} - /* SMI handlers that should be serviced in SCI mode too. */ uint32_t smihandler_soc_get_sci_mask(void) { diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241..31ec9e3 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -32,11 +32,6 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index d8520f1..91bf88f 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -22,29 +22,7 @@ struct gpi_status; struct global_nvs_t; -/* - * The register value is used with get_reg and set_reg - */ -enum smm_reg { - RAX, - RBX, - RCX, - RDX, -}; - -struct smm_save_state_ops { - /* return io_misc_info from SMM Save State Area */ - uint32_t (*get_io_misc_info)(void *state); - - /* return value of the requested register from - * SMM Save State Area - */ - uint64_t (*get_reg)(void *state, enum smm_reg reg); - - void (*set_reg)(void *state, enum smm_reg reg, uint64_t val); -}; - -typedef void (*smi_handler_t)(const struct smm_save_state_ops *save_state_ops); +typedef void (*smi_handler_t)(void); /* * SOC SMI Handler has to provide this structure which has methods to access @@ -66,79 +44,69 @@ * the SMI event on SLP_EN. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_sleep(void); /* * This function should be implemented in SOC specific code to handle * SMI_APM event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_apmc(void); /* * This function should be implemented in SOC specific code to handle * SMI_PM1 event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_pm1(void); /* * This function should be implemented in SOC specific code to handle * SMI_GPE0 event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpe0(void); /* * This function should be implemented in SOC specific code to handle * MC event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_mc(void); /* * This function should be implemented in SOC specific code to handle * minitor event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_monitor(void); /* * This function should be implemented in SOC specific code to handle * SMI_TCO event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_tco(void); /* * This function should be implemented in SOC specific code to handle * SMI PERIODIC_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_periodic(void); /* * This function should be implemented in SOC specific code to handle * SMI GPIO_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_gpi(void); /* * This function should be implemented in SOC specific code to handle * SMI ESPI_STS event. The default functionality is provided in * soc/intel/common/block/smm/smihandler.c */ -void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops); +void smihandler_southbridge_espi(void); /* * Returns gnvs pointer within SMM context @@ -172,8 +140,4 @@ /* Mainboard handler for ESPI EMIs */ void mainboard_smi_espi_handler(void); - -extern const struct smm_save_state_ops em64t100_smm_ops; - -extern const struct smm_save_state_ops em64t101_smm_ops; #endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0581d23..d7330df 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -20,8 +20,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> -#include <cpu/intel/em64t101_save_state.h> #include <delay.h> #include <device/pci_def.h> #include <elog.h> @@ -87,36 +85,44 @@ /* Common Functions */ -static void *find_save_state(const struct smm_save_state_ops *save_state_ops, - int cmd) +/* + * Look for Synchronous IO SMI and use save state from that + * core in case we are not running on the same core that + * initiated the IO transaction. + */ +static int smi_apmc_find_state_save_node(u8 cmd) { + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; - void *state = NULL; - uint32_t io_misc_info; - uint8_t reg_al; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ + /* Check AX against the requested command */ + if ((rax & 0xff) != cmd) + continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - io_misc_info = save_state_ops->get_io_misc_info(state); + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; - /* Check for Synchronous IO (bit0==1) */ - if (!(io_misc_info & (1 << 0))) - continue; - /* Make sure it was a write (bit4==0) */ - if (io_misc_info & (1 << 4)) - continue; - /* Check for APMC IO port */ - if (((io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - /* Check AL against the requested command */ - reg_al = save_state_ops->get_reg(state, RAX); - if (reg_al != cmd) - continue; - break; + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return state; + + return -1; } /* Inherited from cpu/x86/smm.h resulting in a different signature */ @@ -178,8 +184,7 @@ } -void smihandler_southbridge_sleep( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_sleep(void) { uint32_t reg32; uint8_t slp_typ; @@ -274,47 +279,56 @@ } } -static void southbridge_smi_gsmi( - const struct smm_save_state_ops *save_state_ops) +static void southbridge_smi_gsmi(void) { - u8 sub_command, ret; - void *io_smi = NULL; - uint32_t reg_ebx; + u32 ret, param; + u8 sub_command; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(save_state_ops, APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) - & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - ret = gsmi_exec(sub_command, &reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } -static void southbridge_smi_store( - const struct smm_save_state_ops *save_state_ops) +static void southbridge_smi_store(void) { u8 sub_command, ret; - void *io_smi; - uint32_t reg_ebx; + void *param; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); + if (ops->get_reg(node, RBX, &reg)) + return; + param = (void *)(uint32_t)reg; /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); + ret = smmstore_exec(sub_command, param); + ops->set_reg(node, RAX, ret); } static void finalize(void) @@ -335,11 +349,10 @@ smihandler_soc_at_finalize(); } -void smihandler_southbridge_apmc( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_apmc(void) { uint8_t reg8; - void *state = NULL; + const struct smm_save_state_ops *ops = get_save_state_ops(); static int smm_initialized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -376,22 +389,26 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = find_save_state(save_state_ops, reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - uint32_t reg_ebx = save_state_ops->get_reg(state, RBX); - gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx; - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(save_state_ops); + southbridge_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(save_state_ops); + southbridge_smi_store(); break; case APM_CNT_FINALIZE: finalize(); @@ -401,8 +418,7 @@ mainboard_smi_apmc(reg8); } -void smihandler_southbridge_pm1( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_pm1(void) { uint16_t pm1_sts = pmc_clear_pm1_status(); u16 pm1_en = pmc_read_pm1_enable(); @@ -419,14 +435,12 @@ } } -void smihandler_southbridge_gpe0( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpe0(void) { pmc_clear_all_gpe_status(); } -void smihandler_southbridge_tco( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_tco(void) { uint32_t tco_sts = pmc_clear_tco_status(); @@ -442,8 +456,7 @@ } } -void smihandler_southbridge_periodic( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_periodic(void) { uint32_t reg32; @@ -455,8 +468,7 @@ printk(BIOS_DEBUG, "Periodic SMI.\n"); } -void smihandler_southbridge_gpi( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_gpi(void) { struct gpi_status smi_sts; @@ -467,8 +479,7 @@ gpi_clear_get_smi_status(&smi_sts); } -void smihandler_southbridge_espi( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_espi(void) { mainboard_smi_espi_handler(); } @@ -477,7 +488,6 @@ { int i; uint32_t smi_sts; - const struct smm_save_state_ops *save_state_ops; /* * We need to clear the SMI status registers, or we won't see what's @@ -496,15 +506,13 @@ if (!smi_sts) return; - save_state_ops = get_smm_save_state_ops(); - /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { if (!(smi_sts & (1 << i))) continue; if (southbridge_smi[i] != NULL) { - southbridge_smi[i](save_state_ops); + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no " @@ -512,119 +520,3 @@ } } } - -static uint32_t em64t100_smm_save_state_get_io_misc_info(void *state) -{ - em64t100_smm_state_save_area_t *smm_state = state; - return smm_state->io_misc_info; -} - -static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg) -{ - uintptr_t value = 0; - em64t100_smm_state_save_area_t *smm_state = state; - - switch (reg) { - case RAX: - value = smm_state->rax; - break; - case RBX: - value = smm_state->rbx; - break; - case RCX: - value = smm_state->rcx; - break; - case RDX: - value = smm_state->rdx; - break; - default: - break; - } - return value; -} - -static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, - uint64_t val) -{ - em64t100_smm_state_save_area_t *smm_state = state; - switch (reg) { - case RAX: - smm_state->rax = val; - break; - case RBX: - smm_state->rbx = val; - break; - case RCX: - smm_state->rcx = val; - break; - case RDX: - smm_state->rdx = val; - break; - default: - break; - } -} - -static uint32_t em64t101_smm_save_state_get_io_misc_info(void *state) -{ - em64t101_smm_state_save_area_t *smm_state = state; - return smm_state->io_misc_info; -} - -static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg) -{ - uintptr_t value = 0; - em64t101_smm_state_save_area_t *smm_state = state; - - switch (reg) { - case RAX: - value = smm_state->rax; - break; - case RBX: - value = smm_state->rbx; - break; - case RCX: - value = smm_state->rcx; - break; - case RDX: - value = smm_state->rdx; - break; - default: - break; - } - return value; -} - -static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, - uint64_t val) -{ - em64t101_smm_state_save_area_t *smm_state = state; - switch (reg) { - case RAX: - smm_state->rax = val; - break; - case RBX: - smm_state->rbx = val; - break; - case RCX: - smm_state->rcx = val; - break; - case RDX: - smm_state->rdx = val; - break; - default: - break; - } -} - -const struct smm_save_state_ops em64t100_smm_ops = { - .get_io_misc_info = em64t100_smm_save_state_get_io_misc_info, - .get_reg = em64t100_smm_save_state_get_reg, - .set_reg = em64t100_smm_save_state_set_reg, -}; - -const struct smm_save_state_ops em64t101_smm_ops = { - .get_io_misc_info = em64t101_smm_save_state_get_io_misc_info, - .get_reg = em64t101_smm_save_state_get_reg, - .set_reg = em64t101_smm_save_state_set_reg, -}; diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 974c489..3652cde 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -55,8 +55,7 @@ return 0; } -void smihandler_southbridge_mc( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_mc(void) { u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); @@ -67,8 +66,7 @@ printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } -void smihandler_southbridge_monitor( - const struct smm_save_state_ops *save_state_ops) +void smihandler_southbridge_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_cycle; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4..23e0834 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -29,11 +29,6 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..5d01bae 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -20,11 +20,6 @@ #include <intelblocks/smihandler.h> #include <soc/pm.h> -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - void smihandler_soc_check_illegal_access(uint32_t tco_sts) { if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07bea..cbc37f8 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -29,11 +29,6 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 -const struct smm_save_state_ops *get_smm_save_state_ops(void) -{ - return &em64t101_smm_ops; -} - static void pch_disable_heci(void) { struct pcr_sbi_msg msg = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I656aad823a96eafb507e8b30d2177d21efcf2416 Gerrit-Change-Number: 37015 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 8

Change in coreboot[master]: soc/intel/broadwell: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37014 ) Change subject: soc/intel/broadwell: Use common SMM save state ops ...................................................................... soc/intel/broadwell: Use common SMM save state ops Change-Id: I07f576b586622cfff73dea39af0fbb0cfbab04b4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/smihandler.c 1 file changed, 49 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37014/1 diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index ca99487..74bb5a8 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -23,7 +23,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <spi-generic.h> #include <elog.h> #include <halt.h> @@ -260,62 +259,71 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); /* Emulate B2 register as the FADT / Linux expects it */ @@ -341,13 +349,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/37014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f576b586622cfff73dea39af0fbb0cfbab04b4 Gerrit-Change-Number: 37014 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/baytrail: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37013 ) Change subject: soc/intel/baytrail: Use common SMM save state ops ...................................................................... soc/intel/baytrail: Use common SMM save state ops Change-Id: Ia74a9956a22d550b5d864b38632add3d4d48b83d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/smihandler.c 1 file changed, 50 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37013/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 16e2d95..e19f9c6 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <elog.h> #include <halt.h> @@ -177,57 +176,65 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + u32 ret, param; + u8 sub_command; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg);} static void finalize(void) { @@ -301,8 +308,8 @@ static void southbridge_smi_apmc(void) { + const struct smm_save_state_ops *ops = get_save_state_ops(); uint8_t reg8; - em64t100_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -336,13 +343,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/37013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia74a9956a22d550b5d864b38632add3d4d48b83d Gerrit-Change-Number: 37013 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: sb/intel/haswell: Use common smm save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37012 ) Change subject: sb/intel/haswell: Use common smm save state ops ...................................................................... sb/intel/haswell: Use common smm save state ops Change-Id: I6db0a63a0c55ee1c8e67948fd4f4024f886597e6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/lynxpoint/smihandler.c 1 file changed, 49 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/37012/1 diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 61f86fb..a863fc8 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -22,7 +22,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> @@ -214,62 +213,71 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -317,13 +325,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; case 0xca: usb_xhci_route_all(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6db0a63a0c55ee1c8e67948fd4f4024f886597e6 Gerrit-Change-Number: 37012 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/common: Use common save_state ops to fetch apmc args
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37011 ) Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ...................................................................... sb/intel/common: Use common save_state ops to fetch apmc args Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 89 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f292b6f..a9942f3 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> @@ -38,6 +37,11 @@ return gnvs; } +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} + int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -162,18 +166,6 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 6af8805..8959613 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -18,7 +18,6 @@ #define INTEL_COMMON_PMUTIL_H #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -142,10 +141,10 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); +void set_gnvs(void *gnvs_ptr); uint8_t get_gnvs_smif(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +int smi_apmc_find_state_save_node(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 46fe28a..80f4380 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <inttypes.h> #include <types.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -22,7 +23,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> @@ -214,76 +214,108 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uintptr_t reg_rbx; + void *param; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_rbx = (uintptr_t)io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = (void *)(uint32_t)reg; /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_rbx); - io_smi->rax = ret; + ret = smmstore_exec(sub_command, param); + ops->set_reg(node, RAX, ret); +} + +static void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +{ + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); + uint64_t rbx; + uintptr_t gnvs_ptr; + if (ops->get_reg(node, RBX, &rbx)) + return; + + gnvs_ptr = rbx; + + set_gnvs((void *)gnvs_ptr); + *smm_done = 1; + + printk(BIOS_DEBUG, "SMI#: Setting GNVS to " PRIxPTR"\n", gnvs_ptr); } static int mainboard_finalized = 0; diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 1aacbca..b215cc6 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -36,17 +36,15 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs(void *gnvs_ptr) { - gnvs = *(global_nvs_t **)0x500; - *smm_done = 1; + gnvs = gnvs_ptr; } int southbridge_io_trap_handler(int smif) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 96a9e2a..2c56fe6 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -28,9 +28,12 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; + +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} int southbridge_io_trap_handler(int smif) { @@ -49,14 +52,6 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - uint8_t get_gnvs_smif(void) { return gnvs->smif; diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6ed5edd..eb193fa 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -26,18 +26,12 @@ #include "nvs.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; +static global_nvs_t *gnvs; -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} int southbridge_io_trap_handler(int smif) { @@ -56,14 +50,6 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - uint8_t get_gnvs_smif(void) { return gnvs->smif; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..ac45c15 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Gerrit-Change-Number: 37011 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 7

Change in coreboot[master]: sb/intel/common/smihandler: Use a common IO TRAP handler
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37010 ) Change subject: sb/intel/common/smihandler: Use a common IO TRAP handler ...................................................................... sb/intel/common/smihandler: Use a common IO TRAP handler This adds the get_gnvs_smif callback to get smif from the sb dependent gnvs struct. Change-Id: I85ff060012f68087edce6946b05181ee6b84a135 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c 6 files changed, 64 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37010/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index ceac598..f292b6f 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -151,58 +151,9 @@ } } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_smm_xhci_sleep(u8 slp_type) diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index cea5c82..6af8805 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -144,7 +144,7 @@ void southbridge_gate_memory_reset(void); void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); -void southbridge_smi_monitor(void); +uint8_t get_gnvs_smif(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7f376fd..46fe28a 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -30,6 +30,7 @@ #include <smmstore.h> #include "pmutil.h" +#include "rcba.h" static int smm_initialized = 0; @@ -455,6 +456,60 @@ printk(BIOS_DEBUG, "Periodic SMI.\n"); } +static void southbridge_smi_monitor(void) +{ +#define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; + u32 data, mask = 0; + int i; + + trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register + RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR + + trap_cycle = RCBA32(0x1e10); + for (i=16; i<20; i++) { + if (trap_cycle & (1 << i)) + mask |= (0xff << ((i - 16) << 2)); + } + + + /* IOTRAP(3) SMI function call */ + if (IOTRAP(3)) { + io_trap_handler(get_gnvs_smif()); + return; + } + + /* IOTRAP(2) currently unused + * IOTRAP(1) currently unused */ + + /* IOTRAP(0) SMIC */ + if (IOTRAP(0)) { + if (!(trap_cycle & (1 << 24))) { // It's a write + printk(BIOS_DEBUG, "SMI1 command\n"); + data = RCBA32(0x1e18); + data &= mask; + // if (smi1) + // southbridge_smi_command(data); + // return; + } + // Fall through to debug + } + + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + + if (!(trap_cycle & (1 << 24))) { + /* Write Cycle */ + data = RCBA32(0x1e18); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + } +#undef IOTRAP +} + + typedef void (*smi_handler_t)(void); static smi_handler_t southbridge_smi[32] = { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 16ceb13..1aacbca 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -66,49 +66,9 @@ return 0; } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i = 16; i < 20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 2)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC: currently unused */ - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i = 0; i < 4; i++) - if (IOTRAP(i)) - printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_finalize_all(void) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8090a09..96a9e2a 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -57,58 +57,9 @@ *smm_done = 1; } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 3)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_finalize_all(void) diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 667a853..6ed5edd 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -64,58 +64,9 @@ *smm_done = 1; } -void southbridge_smi_monitor(void) +uint8_t get_gnvs_smif(void) { -#define IOTRAP(x) (trap_sts & (1 << x)) - u32 trap_sts, trap_cycle; - u32 data, mask = 0; - int i; - - trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register - RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR - - trap_cycle = RCBA32(0x1e10); - for (i=16; i<20; i++) { - if (trap_cycle & (1 << i)) - mask |= (0xff << ((i - 16) << 3)); - } - - - /* IOTRAP(3) SMI function call */ - if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif - return; - } - - /* IOTRAP(2) currently unused - * IOTRAP(1) currently unused */ - - /* IOTRAP(0) SMIC */ - if (IOTRAP(0)) { - if (!(trap_cycle & (1 << 24))) { // It's a write - printk(BIOS_DEBUG, "SMI1 command\n"); - data = RCBA32(0x1e18); - data &= mask; - // if (smi1) - // southbridge_smi_command(data); - // return; - } - // Fall through to debug - } - - printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); - printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); - printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); - - if (!(trap_cycle & (1 << 24))) { - /* Write Cycle */ - data = RCBA32(0x1e18); - printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); - } -#undef IOTRAP + return gnvs->smif; } void southbridge_finalize_all(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ff060012f68087edce6946b05181ee6b84a135 Gerrit-Change-Number: 37010 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019