coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in ...coreboot[master]: soc/intel/common/block/pcr: Remove unneded 'esle'
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33336 Change subject: soc/intel/common/block/pcr: Remove unneded 'esle' ...................................................................... soc/intel/common/block/pcr: Remove unneded 'esle' 'else' is not needed after a 'break' or 'return'. Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33336/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 4a35a03..f3971c2 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -394,10 +394,9 @@ break; } return 0; - } else { - printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", - *response); - return -1; } + printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", + *response); + return -1; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Gerrit-Change-Number: 33336 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: src/Kconfig: Move DRAM section to 'Devices' menu
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32882 Change subject: src/Kconfig: Move DRAM section to 'Devices' menu ...................................................................... src/Kconfig: Move DRAM section to 'Devices' menu This moves DRAM to 'Devices' menu and allow to change default DIMM_MAX value if needed. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig M src/device/Kconfig 2 files changed, 24 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32882/1 diff --git a/src/Kconfig b/src/Kconfig index 2c9dc4a..d30aa99 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1158,31 +1158,6 @@ implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. -config GENERIC_SPD_BIN - bool - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config SPD_READ_BY_WORD - bool - config BOOTBLOCK_CUSTOM # To be selected by arch, SoC or mainboard if it does not want use the normal # src/lib/bootblock.c#main() C entry point. diff --git a/src/device/Kconfig b/src/device/Kconfig index 0539062..d4cacec 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -681,5 +681,29 @@ be useful for debugging or on platforms where a driver for the real I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int "Total number of memory DIMM slots" + default 4 + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config SPD_READ_BY_WORD + bool endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Gerrit-Change-Number: 32882 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: mb/supermicro/x11: fix cmos layout and add a default config
by Michael Niewöhner (Code Review) 13 Nov '22

13 Nov '22

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35526 ) Change subject: mb/supermicro/x11: fix cmos layout and add a default config ...................................................................... mb/supermicro/x11: fix cmos layout and add a default config This fixes the error that power_on_after_fail could not be found, adds the missing nmi option and adds a default config. Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig A src/mainboard/supermicro/x11-lga1151-series/cmos.default M src/mainboard/supermicro/x11-lga1151-series/cmos.layout 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35526/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 3aaf1d3..68a3c94 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -4,6 +4,7 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.default b/src/mainboard/supermicro/x11-lga1151-series/cmos.default new file mode 100644 index 0000000..45a860b --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout index 201ca33..e1c6aed 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout @@ -30,6 +30,10 @@ 395 4 e 6 debug_level 448 128 r 0 vbnv +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + # coreboot config options: check sums 984 16 h 0 check_sum -- To view, visit https://review.coreboot.org/c/coreboot/+/35526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4 Gerrit-Change-Number: 35526 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

6 25

Change in coreboot[master]: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
by Arthur Heymans (Code Review) 26 Oct '22

26 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37321 ) Change subject: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB ...................................................................... cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB Pre-sandy bridge hardware is likely affected by the sinkhole vulnerability. Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37321/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index efb5fa9..335463d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -139,9 +139,9 @@ config SMM_LAPIC_REMAP_MITIGATION bool - default y if NORTHBRIDGE_INTEL_I945 - default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \ + || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \ + || NORTHBRIDGE_INTEL_E7505 default n config SERIALIZED_SMM_INITIALIZATION -- To view, visit https://review.coreboot.org/c/coreboot/+/37321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Gerrit-Change-Number: 37321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: Kconfig: Allow x86 to compress pre-ram stages if not run XIP
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36613 ) Change subject: Kconfig: Allow x86 to compress pre-ram stages if not run XIP ...................................................................... Kconfig: Allow x86 to compress pre-ram stages if not run XIP Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36613/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..df86246 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -160,7 +160,7 @@ config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" - depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) + depends on HAVE_ROMSTAGE || HAVE_VERSTAGE # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash @@ -1217,7 +1217,7 @@ default y if !UNCOMPRESSED_RAMSTAGE config COMPRESS_PRERAM_STAGES - depends on !ARCH_X86 + depends on NO_XIP_EARLY_STAGES default y config INCLUDE_CONFIG_FILE diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..db4f054 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -119,6 +119,7 @@ ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S +bootblock-y += memmove.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) -- To view, visit https://review.coreboot.org/c/coreboot/+/36613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Gerrit-Change-Number: 36613 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 21

Change in ...coreboot[master]: mb/lenovo/*/romstage: Use common hybrid_graphics_init
by Peter Lemenkov (Code Review) 01 Jun '22

01 Jun '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33807 Change subject: mb/lenovo/*/romstage: Use common hybrid_graphics_init ...................................................................... mb/lenovo/*/romstage: Use common hybrid_graphics_init Change-Id: I28c3c5c94ce6c6b3fb44c2540a6fa7953a28b761 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h M src/drivers/lenovo/hybrid_graphics/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c 7 files changed, 30 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33807/1 diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h index b238440..2f7cce6 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h @@ -17,5 +17,6 @@ #define _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); +void hybrid_graphics_init(void); #endif /* _DRIVERS_LENOVO_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 35cb384..e4b27bb 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -24,6 +24,9 @@ #include "hybrid_graphics.h" #include "chip.h" +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> + /* * Returns the hybrid graphics presence and user's card preferences. */ @@ -94,3 +97,29 @@ " FIXME: dGPU power handling not implemented\n"); } } + +void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index ebf5aed..2f7ceb4 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 49de58d..2eed168 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 1f4b90d..98ff418 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 5c23b8e..c23b896 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -25,32 +25,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 67cf97c..1b76def 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -25,32 +25,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c3c5c94ce6c6b3fb44c2540a6fa7953a28b761 Gerrit-Change-Number: 33807 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: configs: add Lenovo G505S sample configuration (use with dGPU patches)
by mikeb mikeb (Code Review) 01 Jun '22

01 Jun '22

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32352 to review the following change. Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches) ...................................................................... configs: add Lenovo G505S sample configuration (use with dGPU patches) This sample .config could not be merged before the dGPU patches at CB:31929 (see https://review.coreboot.org/c/coreboot/+/31929 for more information). I'm sharing it with you here partially for the archival purposes. After you have installed the dGPU patches above, you can use this .config as the base configuration for your G505S by saving it to ./coreboot/.config - however, you may want to change some of its' configs! For example: it specifies CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" CONFIG_VGA_BIOS_DGPU_ID="1002,6665" which is compatible with R5-M230 discrete GPU, but if your G505S has HD-8570M discrete GPU instead - you will need to change these configs to ",6663" etc. Or, if your G505S does not have a discrete GPU at all, please disable CONFIG_MULTIPLE_VGA_ADAPTERS=y and those DGPU configs will be disabled. Also, if you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I've disabled this WiFi adapter at my .config to save some space: If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7 --- A configs/config.lenovo_g505s_use_with_dgpu_patches 1 file changed, 746 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32352/1 diff --git a/configs/config.lenovo_g505s_use_with_dgpu_patches b/configs/config.lenovo_g505s_use_with_dgpu_patches new file mode 100644 index 0000000..5ff218f --- /dev/null +++ b/configs/config.lenovo_g505s_use_with_dgpu_patches @@ -0,0 +1,746 @@ +# +# ./coreboot/.config for Lenovo G505S - 17 April 2019 +# +### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/g505s" +CONFIG_MAINBOARD_PART_NUMBER="LENOVO G505S" +CONFIG_MAX_CPUS=4 +CONFIG_CBFS_SIZE=0x400000 +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_VGA_BIOS_ID="1002,990b" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="pci1002,990b.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +# CONFIG_HUDSON_XHCI_FWM is not set +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_POST_DEVICE=y +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_VBOOT is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="LENOVO G505S" +CONFIG_BOARD_LENOVO_G505S=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_BASEBOARD_T520 is not set +# CONFIG_BOARD_LENOVO_BASEBOARD_T530 is not set +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_BOARD_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c" +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x100000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CPU_AMD_AGESA=y +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=32768 +CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_COMPAL_ENE932=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_CBMEM_TOP_BACKUP=y +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_HAS_MULTIPLE_VGA_ADAPTERS=y +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y +CONFIG_MULTIPLE_VGA_ADAPTERS=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +CONFIG_BOOTSPLASH=y +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_VGA_BIOS_DGPU=y +CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" +CONFIG_VGA_BIOS_DGPU_ID="1002,6665" +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +CONFIG_DRIVERS_AMD_PI=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +# CONFIG_POSTCAR_CONSOLE is not set +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y + -- To view, visit https://review.coreboot.org/c/coreboot/+/32352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7 Gerrit-Change-Number: 32352 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 51

Change in ...coreboot[master]: configs: add ASUS AM1I-A sample configuration
by Mike Banon (Code Review) 01 Jun '22

01 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33800 Change subject: configs: add ASUS AM1I-A sample configuration ...................................................................... configs: add ASUS AM1I-A sample configuration You can use this .config as the base configuration for your AM1I-A by saving it to ./coreboot/.config - however, you may want to change some of its' configs! If you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I have disabled Intel WiFi adapter at my .config to save some space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4 --- A configs/config.asus_am1i-a 1 file changed, 789 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33800/1 diff --git a/configs/config.asus_am1i-a b/configs/config.asus_am1i-a new file mode 100644 index 0000000..0660c44 --- /dev/null +++ b/configs/config.asus_am1i-a @@ -0,0 +1,789 @@ +######### +### +### ./coreboot/.config for ASUS AM1I-A - 26 Jun 2019 +### +######### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/am1i-a" +CONFIG_MAINBOARD_PART_NUMBER="AM1I-A" +CONFIG_MAX_CPUS=4 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_IRQ_SLOT_COUNT=9 +CONFIG_VGA_BIOS_ID="1002,9830" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_AZ_PIN=0xaa +CONFIG_VGA_BIOS_FILE="pci1002,9830.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_BOARD_ASUS_AM1I_A=y +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_H61M_CS is not set +# CONFIG_BOARD_ASUS_KCMA_D8 is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KGPE_D16 is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +# CONFIG_BOARD_ASUS_P5QC is not set +# CONFIG_BOARD_ASUS_P5Q_PRO is not set +# CONFIG_BOARD_ASUS_P5QL_PRO is not set +# CONFIG_BOARD_ASUS_P5QPL_AM is not set +# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set +# CONFIG_HUDSON_IMC_FWM is not set +# CONFIG_HUDSON_XHCI_FWM is not set +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=4 +CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="AM1I-A" +CONFIG_CPU_ADDR_BITS=40 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 +# CONFIG_SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QUALCOMM_COMMON is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x100000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CPU_AMD_AGESA=y +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=32768 +CONFIG_CPU_AMD_AGESA_FAMILY16_KB=y +CONFIG_FORCE_AM1_SOCKET_SUPPORT=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c" +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_ASPEED_AST2400 is not set +# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set +CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y +CONFIG_SUPERIO_ITE_ENV_CTRL=y +CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y +CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y +CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y +CONFIG_SUPERIO_ITE_IT8623E=y + +# +# Embedded Controllers +# +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +CONFIG_AGESA_EXTRA_TIMESTAMPS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_RISCV_M is not set +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_CBMEM_TOP_BACKUP=y +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +CONFIG_BOOTSPLASH=y +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +CONFIG_DRIVERS_AMD_PI=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_USER_TPM1 is not set +# CONFIG_USER_TPM2 is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +# CONFIG_POSTCAR_CONSOLE is not set +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_CBMEM=y +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO=y +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_POSTCAR=y +CONFIG_HAVE_RAMSTAGE=y + -- To view, visit https://review.coreboot.org/c/coreboot/+/33800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4 Gerrit-Change-Number: 33800 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 38

Change in ...coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review) 01 Jun '22

01 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33509 Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches ...................................................................... csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches Conveniently and securely gets, checks SHA256 and installs some of my patches from this page - https://review.coreboot.org/q/status:open+banon - and also gets a collection of useful floppy-based operating systems. Sometimes it takes quite a long time to get a patch merged, while the people might need it today! - and this script could be really helpful. It asks a [Y/N] question for every addition, and since there are some "universal" patches as well as great floppies, you may still want to run this script - even if your board is not Lenovo G505S or not AMD. Please share your feedback/suggestions and tell about other useful patches, preferably the "universal" ones - i.e. SeaBIOS. Currently included: 1) "board-specific": G505S dGPU support, G505S config and AtomBIOS ROMs 2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb ; tint build system ; and also a floppies collection : KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird. Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49 --- A csb_patcher.sh 1 file changed, 876 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33509/1 diff --git a/csb_patcher.sh b/csb_patcher.sh new file mode 100755 index 0000000..b325f71 --- /dev/null +++ b/csb_patcher.sh @@ -0,0 +1,876 @@ +#!/bin/sh +# +# csb_patcher.sh: coreboot and SeaBIOS patcher script. +# +# Conveniently and securely gets, checks SHA256 and installs some of my +# patches from this page - https://review.coreboot.org/q/status:open+banon +# and also gets a collection of useful floppy-based operating systems. +# Please send your feedback to Mike Banon <mikebdp2(a)gmail.com> +# + +# Keys +enter=$( printf '\015' ) +ctrl_c=$( printf '\003' ) +ctrl_x=$( printf '\030' ) +ctrl_z=$( printf '\032' ) + +# Formatting +bold="\e[1m" +bred="\e[1;31m" +bgreen="\e[1;32m" +byellow="\e[1;33m" +bend="\e[0m" + +# Asks a question '$1' and waits for Y/N user input, printing a decision - with '$2' message if Y. +yesno () { + printf "$1 [Y/N] " + yesno_old_stty_cfg=$( stty -g ) + stty raw -echo + while true ; do + yesno_answer=$( head -c 1 ) + case "$yesno_answer" in + *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*) + stty "$yesno_old_stty_cfg" + printf "${bred}TERMINATED${bend}\n" + exit 1 + ;; + *"y"*|"Y"*) + stty "$yesno_old_stty_cfg" + printf "${bgreen}YES${bend}$2\n" + return 0 + ;; + *"n"*|"N"*) + stty "$yesno_old_stty_cfg" + printf "${byellow}NO${bend}\n" + return 1 + ;; + esac + done +} + +# Waits until a user presses Enter. +encontinue () { + printf "\npress [ENTER] to continue... " + encontinue_old_stty_cfg=$( stty -g ) + stty raw -echo + while true ; do + encontinue_answer=$( head -c 1 ) + case "$encontinue_answer" in + *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*) + stty "$encontinue_old_stty_cfg" + printf "${bred}TERMINATED${bend}\n" + exit 1 + ;; + *"$enter"*) + stty "$encontinue_old_stty_cfg" + printf "\n" + return 0 + ;; + esac + done +} + +# Checks if a command '$1' exists. +command_exists() { + if [ ! -x "$( command -v $1 )" ] ; then + printf "\n${bred}ERROR${bend}: command ${bold}$1${bend} is not found !\n" + encontinue + return 1 + else + return 0 + fi +} + +# Checks if a file '$1' exists. +file_exists () { + if [ ! -f "$1" ] ; then + printf "\n${byellow}WARNING${bend}: file ${bold}$1${bend} is not found !\n" + encontinue + return 1 + else + return 0 + fi +} + +# Force removes a file '$2' and then copies a file '$1' to '$2'. +copier () { + if file_exists "$1" ; then + rm -f "$2" + cp "$1" "$2" + return 0 + else + return 1 + fi +} + +# Force removes a file '$2' and then moves a file '$1' to '$2'. +mover () { + if file_exists "$1" ; then + rm -f "$2" + mv "$1" "$2" + return 0 + else + return 1 + fi +} + +# Checks if line '$1' contains the text '$2'. +checker () { + case "$1" in + *"$2"*) + return 0 + ;; + *) + return 1 + ;; + esac +} + +# Prints the lines of a file '$2' which contain the text '$1'. +grepper () { + if file_exists "$2" ; then + while IFS= read -r grepper_line + do + case "$grepper_line" in + *"$1"*) + printf '%s\n' "$grepper_line" + ;; + esac + done < "$2" + return 0 + else + return 1 + fi +} + +# Checks if a file '$2' contains the text '$1'. +grepcheck () { + if file_exists "$2" ; then + while IFS= read -r grepcheck_line + do + case "$grepcheck_line" in + *"$1"*) + return 0 + ;; + esac + done < "$2" + return 1 + else + return 1 + fi +} + +# Replaces the lines containing the text '$2' of a file '$1' with a line '$3'. +sedder () { + if file_exists "$1" ; then + csb_sedder_tmp="./.csb_sedder" + rm -f "$csb_sedder_tmp" + while IFS= read -r sedder_line + do + case "$sedder_line" in + *"$2"*) + if [ ! -z "$3" ] ; then + printf '%s\n' "$3" >> "$csb_sedder_tmp" + fi + ;; + *) + printf '%s\n' "$sedder_line" >> "$csb_sedder_tmp" + ;; + esac + done < "$1" + mover "$csb_sedder_tmp" "$1" + return 0 + else + return 1 + fi +} + +# Downloads a file '$1' from a link '$2' using the options '$3' and checks if this was successful. +wgetter () { + rm -f "$1" + if [ -z "$3" ] ; then + wget "$2" + else + wget "$3" "$2" + fi + if [ -f "$1" ] ; then + wgetter_file_size=$(($( wc -c < "$1" ))) + if [ "$wgetter_file_size" -eq "0" ] ; then + rm -f "$1" + fi + fi + if [ ! -f "$1" ] ; then + printf "\n${byellow}WARNING${bend}: can't download a ${bold}$1${bend} file !" + printf "\n Please check your Internet connection and try again.\n" + encontinue + return 1 + else + return 0 + fi +} + +# Unzips the archive '$1', optional '$2' for -j path inside the archive, and then force removes it. +unzipper () { + if file_exists "$1" ; then + if [ -z "$2" ] ; then + unzip "$1" + else + unzip -j "$1" "$2" + fi + rm -f "$1" + return 0 + else + return 1 + fi +} + +# Expands a file '$1' with zeroes using a dd to '$2' size - e.g. to a standard floppy size 1474560. +expander () { + if file_exists "$1" && [ ! -z "$2" ] ; then + expander_file_size=$(($( wc -c < "$1" ))) + if [ "$expander_file_size" -lt "$2" ] ; then + dd if=/dev/zero of=$1 bs=1 count=1 seek="$(( $2 - 1 ))" conv=notrunc iflag=nocache + fi + return 0 + else + return 1 + fi +} + +# Compares sha256sum of '$1.img' floppy image with '$2' and creates a hidden '.$1' file if matches. +floppy_verifier () { + rm -f "./.$1" + cd ".." + if [ ! -z "$2" ] ; then + if file_exists "./floppies/$1.img" ; then + floppy_verifier_sha256sum_correct="$2 ./floppies/$1.img" + floppy_verifier_sha256sum_my=$( sha256sum "./floppies/$1.img" ) + printf "\n=== sha256sum should be:\n${bold}$floppy_verifier_sha256sum_correct${bend}\n" + if [ "$floppy_verifier_sha256sum_my" = "$floppy_verifier_sha256sum_correct" ] ; then + printf "^^^ this is correct, ./floppies/${bold}$1.img${bend} is verified and could be added.\n\n" + cd "./floppies/" + touch "./.$1" + return 0 + else + printf "${bold}^^^ ! MISMATCH for ./floppies/$1.img ! Check sha256sum manually: sha256sum ./floppies/$1.img${bend}\n" + encontinue + cd "./floppies/" + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n" + printf "\n Please re-download a set of floppies.\n" + encontinue + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is a rolling release, its' SHA256 checksum" + printf "\n is changing constantly and not provided by $1 project, so not checked.\n" + encontinue + cd "./floppies/" + touch "./.$1" + return 0 + fi +} + +# Downloads a collection of floppies, for the purpose of adding them later to a coreboot ROM image. +floppy_mass_downloader () { + printf "\n" + if [ ! -d "./floppies/" ]; then + mkdir "./floppies/" + fi + cd "./floppies/" + # KOLIBRI + if command_exists "7za" ; then + if wgetter "./latest-img.7z" "https://builds.kolibrios.org/eng/latest-img.7z" ; then + rm -f "./kolibri.img" + 7za x "./latest-img.7z" + rm -f "./latest-img.7z" + floppy_verifier "kolibri" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION + fi + else + printf "\n${byellow}WARNING${bend}: cannot get ./floppies/${bold}kolibri.img${bend} without ${bold}7za${bend}\n" + encontinue + fi + # FREEDOS + if wgetter "./FD12FLOPPY.zip" "https://www.freedos.org/download/download/FD12FLOPPY.zip" ; then + unzipper "./FD12FLOPPY.zip" "FLOPPY.img" + mover "./FLOPPY.img" "./freedos.img" + floppy_verifier "freedos" "de2fb84dc2f132324549e89d58c6383497ec1af538c5b0ecde389fb748b9d537" + fi + # MICHALOS + printf "\n${byellow}WARNING${bend}: getting ./floppies/${bold}michalos.img${bend} could take a couple of minutes...\n\n" + if wgetter "./MichalOS 2.0 Source.zip" "https://sourceforge.net/p/michalos/tickets/_discuss/thread/69ab1508c3/39cd/…" "--content-disposition" ; then + unzipper "./MichalOS 2.0 Source.zip" "disk_images/michalos.img" + floppy_verifier "michalos" "139e9d08881f646156971a0a061972ddca77057b8acf4164e36366271ab3658c" + fi + # SNOWDROP + if wgetter "./snowdrop.img" "http://sebastianmihai.com/downloads/snowdrop/snowdrop.img" ; then + floppy_verifier "snowdrop" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION + fi + # FIWIX + if wgetter "./fiwix.img" "https://www.fiwix.org/fiwix-1.0.1-i386-initrd.img" "--output-document=fiwix.img" ; then + floppy_verifier "fiwix" "dbec2994ec619c9954327ab0b983ab24cd362406a2e515c35c79c79bd6417cfd" + fi + # MEMTEST + if wgetter "./memtest86+-5.01.floppy.zip" "https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip" ; then + unzipper "./memtest86+-5.01.floppy.zip" "floppy/memtestp.bin" + expander "./memtestp.bin" "1474560" + mover "./memtestp.bin" "./memtest.img" + floppy_verifier "memtest" "364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1" + fi + # TATOS + if wgetter "./tatos.img" "https://github.com/tatimmer/tatOS/raw/master/tatOS.img" "--output-document=tatos.img" ; then + expander "./tatos.img" "1474560" + floppy_verifier "tatos" "2c66f884498a4fe7b469bc213aebfccd84a09fd7ace1b3b4b3e747e2392c35d1" + fi + # PLOP + if wgetter "./plpbt-5.0.15.zip" "https://download.plop.at/files/bootmngr/plpbt-5.0.15.zip" ; then + unzipper "./plpbt-5.0.15.zip" "plpbt-5.0.15/plpbt.img" + mover "./plpbt.img" "./plop.img" + floppy_verifier "plop" "f170759966ec4efe60c8531158344a234d7543c8de81e54c8c1bb9d2d69eaf27" + fi + # FLOPPYBIRD + if wgetter "./floppybird.img" "https://github.com/mikebdp2/floparchive/raw/master/floppies_extra/floppybir…" ; then + floppy_verifier "floppybird" "5db1b469e25e9eda7b8c0f666d6b655bab083c85618a9453ee72f1201cca840f" + fi + # Some floppies have the weird permissions after their extraction + floppy_mass_downloader_floppies=$( find . -name "*.img" ) + if [ ! -z "$floppy_mass_downloader_floppies" ] ; then + chmod 755 "./"*".img" + fi + # Return back to ./coreboot/ + cd ".." + return 0 +} + +# Adds a './pci1002,$1.rom' to coreboot '$3' ROM using '$2' cbfstool, printing '$4'/'$5'/'$6' info. +atombios_adder () { + if file_exists "$2" && file_exists "$3" ; then + if [ -f "./pci1002,$1.rom" ] ; then + atombios_adder_cbfs=$( "$2" "$3" print ) + if checker "$atombios_adder_cbfs" "pci1002,$1.rom" ; then + printf "\n${bgreen}NOTE${bend}: ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} is already at your $3.\n" + else + if yesno "\nAdd a ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then + "$2" "$3" add -f "./pci1002,$1.rom" -n "pci1002,$1.rom" -t optionrom + else + printf "\n${bold}You can add it later by running:${bend}" + printf "\n${bold} $2 $3 add -f ./pci1002,$1.rom -n pci1002,$1.rom -t optionrom${bend}\n\n" + fi + fi + return 0 + else + printf "\n${byellow}WARNING${bend}: cannot find ./${bold}pci1002,$1.rom${bend} ," + printf "\n please re-apply ${bold}AMD atombios${bend} patch.\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# Adds a '$1.img' floppy image to coreboot '$3' ROM using '$2' cbfstool, printing '$4' size info. +floppy_adder () { + if file_exists "$2" && file_exists "$3" ; then + if [ -f "./floppies/$1.img" ] ; then + if [ -f "./floppies/.$1" ] ; then + floppy_adder_cbfs=$( "$2" "$3" print ) + if checker "$floppy_adder_cbfs" "floppyimg/$1.lzma" ; then + printf "\n${bgreen}NOTE${bend}: ./floppies/${bold}$1.img${bend} is already at your $3.\n" + else + if checker "$1" "plop" ; then + printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is proprietary: all its' source code is closed !" + printf "\n Add it only if you really need it and trust the author of $1 project.\n" + encontinue + fi + if yesno "\nAdd a ./floppies/${bold}$1.img${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then + "$2" "$3" add -f "./floppies/$1.img" -n "floppyimg/$1.lzma" -t raw -c lzma + else + printf "\n${bold}You can add it later by running:${bend}" + printf "\n${bold} $2 $3 add -f ./floppies/$1.img -n floppyimg/$1.lzma -t raw -c lzma${bend}\n\n" + fi + fi + return 0 + else + printf "\n${byellow}WARNING${bend}: there was a SHA256 mismatch for ./floppies/${bold}$1.img${bend} -" + printf "\n check sha256sum manually: sha256sum ./floppies/${bold}$1.img${bend}\n" + encontinue + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n" + printf "\n Please re-download a set of floppies.\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# Adds a set of AtomBIOS/floppies ('$1') to coreboot '$3' ROM copied to '$4', using '$2' cbfstool. +cbfs_mass_adder () { + if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then + printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory," + printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n" + fi + if file_exists "$2" && file_exists "$3" ; then + if checker "$1" "atom" || checker "$1" "flop" ; then + copier "$3" "$4" + printf "\n${bold}=== $4 - initial memory map${bend}\n\n" + "$2" "$4" print + printf "\n" + if checker "$1" "atom" ; then +### +### https://review.coreboot.org/c/coreboot/+/31944 +### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 +### + csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD " + atombios_adder "990b" "$2" "$4" "62K" "Lenovo G505S with A10-5750M" "iGPU HD-8650G" + atombios_adder "6663" "$2" "$4" "33K" "Lenovo G505S with A10-5750M" "dGPU HD-8570M" + atombios_adder "6665" "$2" "$4" "32K" "Lenovo G505S with A10-5750M" "dGPU R5-M230" + atombios_adder "9830" "$2" "$4" "59K" "ASUS AM1I-A with Athlon-5370" "iGPU HD-8400 / R3-Series" + atombios_adder "990c" "$2" "$4" "62K" "ASUS A88XM-E with A10-6700" "iGPU HD-8670D" + fi + if checker "$1" "flop" ; then + if [ ! -d "./floppies/" ] ; then + printf "\n" + floppy_mass_downloader + fi + # Default boot order: the last floppy added - is the first floppy to boot! + floppy_adder "floppybird" "$2" "$4" "2K" + floppy_adder "plop" "$2" "$4" "74K" + floppy_adder "tatos" "$2" "$4" "60K" + floppy_adder "memtest" "$2" "$4" "44K" + floppy_adder "fiwix" "$2" "$4" "458K" + floppy_adder "snowdrop" "$2" "$4" "126K" + floppy_adder "michalos" "$2" "$4" "256K" + floppy_adder "freedos" "$2" "$4" "698K" + floppy_adder "kolibri" "$2" "$4" "1264K" + fi + printf "\n${bold}=== $4 - final memory map${bend}\n\n" + "$2" "$4" print + printf "\nYou can use ./build/${bold}coreflop.rom${bend} now !\n\n" + return 0 + else + return 1 + fi + else + return 1 + fi +} + +# Finds the files of '$1' extension, saves the result to '$2' log and prints a message with '$3'. +csb_finder () { + csb_finder_files=$( find . -name "*.$1" ) + if [ ! -z "$csb_finder_files" ] ; then + printf "%25s\n" "*.$1 - YES" >> "$2" + printf "\n${byellow}WARNING${bend}: found ${bold}*.$1${bend} files at these locations :\n" + printf "$csb_finder_files" + printf "\n That means - Some patches $3\n" + encontinue + return 0 + else + printf "%24s\n" "*.$1 - NO" >> "$2" + return 1 + fi +} + +# Prints a csb_patcher_log '$1' with a custom highlighting. +csb_printer () { + if ! file_exists "$1" ; then + return 1 + fi + while IFS= read -r csb_printer_line + do + case "$csb_printer_line" in + *"orig - YES"*) + printf "${csb_printer_line%???}${byellow}YES" # YELLOW + ;; + *"rej - YES"*) + printf "${csb_printer_line%???}${bred}YES" # RED + ;; + *"YES"*) + printf "${csb_printer_line%???}${bgreen}YES" # GREEN + ;; + *"orig - NO"*|*"rej - NO"*) + printf "${csb_printer_line%??}${bgreen}NO" # GREEN + ;; + *"NO"*) + printf "${csb_printer_line%??}${byellow}NO" # YELLOW + ;; + *"FAILURE_1"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_1" # RED + ;; + *"FAILURE_2"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_2" # RED + ;; + *"FAILURE_3"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_3" # RED + ;; + *"\\\\"*) + printf "${bold}${csb_printer_line%?????}\\\\\!//" # ALIEN HAIR + ;; + *) + printf "${bold}$csb_printer_line" + ;; + esac + printf "${bend}\n" + done < "$1" + return 0 +} + +# Configure some popular options of a config file '$1'. +csb_configurer () { + if file_exists "$1" ; then + csb_configurer_tmp="./.csb_configurer" + rm -f "$csb_configurer_tmp" + grepper "CONFIG_BOARD_" "$1" > "$csb_configurer_tmp" + if grepcheck "_LENOVO_G505S=y" "$csb_configurer_tmp" ; then + printf "\n\n${bgreen}[CONFIG]${bend} Questions about your Lenovo G505S\n\n" + sedder "$1" "### CSB_CONFIGURER OPTIONS" "" + printf "### CSB_CONFIGURER OPTIONS\n" >> "$1" + sedder "$1" "# CONFIG_DRIVERS_INTEL_WIFI is not set" "" + if ! yesno "Do you have an Intel WiFi adapter?" "" ; then + printf "# CONFIG_DRIVERS_INTEL_WIFI is not set\n" >> "$1" + fi + sedder "$1" "CONFIG_MULTIPLE_VGA_ADAPTERS=y" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU=y" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"" "" + if yesno "Do you have a Discrete GPU?" "" ; then + printf "CONFIG_MULTIPLE_VGA_ADAPTERS=y\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU=y\n" >> "$1" + if yesno "No for HD-8570M, Yes for R5-M230" "" ; then + printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"\n" >> "$1" + else + printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"\n" >> "$1" + fi + fi + + sedder "$1" "# NATIVE" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=0" "" + + sedder "$1" "# RAID" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=1" "" + sedder "$1" "CONFIG_RAID_ROM_ID=\"1022,7802\"" "" + sedder "$1" "CONFIG_RAID_ROM_FILE=\"src/southbridge/amd/agesa/hudson/raid.bin\"" "" + sedder "$1" "CONFIG_RAID_MISC_ROM_FILE=\"src/southbridge/amd/agesa/hudson/misc.bin\"" "" + sedder "$1" "CONFIG_RAID_MISC_ROM_POSITION=0xFFF00000" "" + + sedder "$1" "# AHCI" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=2" "" + sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7801\"" "" + sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" "" + + sedder "$1" "# LEGACY IDE" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=3" "" + + sedder "$1" "# IDE to AHCI" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=4" "" + + sedder "$1" "# AHCI7804" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=5" "" + sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7804\"" "" + + sedder "$1" "# IDE to AHCI7804" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=6" "" + sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" "" + + if yesno "Do you have a SSD? (enable AHCI if Y)" "" ; then + printf "# AHCI\n" >> "$1" + printf "CONFIG_HUDSON_SATA_MODE=2\n" >> "$1" + printf "CONFIG_AHCI_ROM_ID=\"1022,7801\"\n" >> "$1" + printf "# CONFIG_HUDSON_AHCI_ROM is not set\n" >> "$1" + else + printf "# NATIVE\n" >> "$1" + printf "CONFIG_HUDSON_SATA_MODE=0\n" >> "$1" + fi + rm -f "$csb_configurer_tmp" + return 0 + else + printf "\n\n${byellow}WARNING${bend}: sorry, I don't know how to configure a board of ${bold}$1${bend}\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# +# Conveniently and securely gets, checks SHA256 and installs a patch. +# Arguments are the patch properties: +# $1 - new diff name, could be also a part of extracted scripts' filename +# $2 - change ID number, part of download link to review.coreboot.org +# $3 - change revision number, part of download link to review.coreboot.org +# $4 - diff filename inside the downloaded archive, will be renamed to $1 +# $5 - diff known good SHA256 checksum, will be used for SHA256 verification +# $6 - filepath where to save a csb_patcher_log which will be printed later +# $7 - info about the target of a patch, if not specified ("") it is common +# +csb_patcher () { + if ! wgetter "./patch?zip" "https://review.coreboot.org/changes/$2/revisions/$3/patch?zip" ; then + printf "${bold}^^^ ! Can't download a $7$1 patch ! Check your Internet.${bend}\n" + printf "%31s\n" "$7$1 - FAILURE_1" >> "$6" + csb_printer "$6" + exit 1 + fi + unzipper "./patch?zip" + mover "./$4.diff" "./$1.diff" + csb_patcher_sha256sum_correct="$5 ./$1.diff" + csb_patcher_sha256sum_my=$( sha256sum "./$1.diff" ) + printf "\n=== sha256sum should be:\n${bold}$csb_patcher_sha256sum_correct${bend}\n" + if [ "$csb_patcher_sha256sum_my" = "$csb_patcher_sha256sum_correct" ] ; then + printf "^^^ this is correct, " + csb_patcher_patch_title=$( grepper "Subject" "./$1.diff" ) + csb_patcher_patch_title=${csb_patcher_patch_title#?????????????????} + if [ "$1" = "dgpu" ] ; then + printf "will extract a ${bold}$7$1${bend} patch now...\n" + rm -f "./sha256sums_$1_correct.txt" + rm -f "./"*"_$1_patches.sh" + patch -p1 < "./$1.diff" + chmod +x "./"*"_$1_patches.sh" + "./get_$1_patches.sh" + if ! "./check_$1_patches.sh" ; then + printf "%31s\n" "$7$1 - FAILURE_3" >> "$6" + csb_printer "$6" + exit 1 + fi + else + printf "${bold}$7$1${bend} patch could be applied now...\n" + fi + if [ "$1" = "dgpu" ] || [ "$1" = "atombios" ] || \ + [ "$1" = "tint" ] || [ "$1" = "seabios" ] ; then + printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n" + if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then + printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory," + printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n" + fi + if [ -f "./.$1" ] ; then + printf "\n${byellow}WARNING${bend}: found a '.$1' hidden file at the current directory," + printf "\n maybe you have applied this patch already.\n\n" + fi + if yesno "Apply a ${bold}$7$1${bend} patch now?" "" ; then + if [ "$1" = "dgpu" ] ; then + "./apply_$1_patches.sh" + else + if [ "$1" = "atombios" ] ; then + rm -f "./sha256sums_$1_correct.txt" + rm -f "./"*"_$1_roms.sh" + rm -f "./pci1002\,"*".rom" + rm -f "./pci1002\,"*".rom.txt" + fi + if [ "$1" = "tint" ] ; then + rm -f "./payloads/external/tint/tint.sh" + rm -f "./payloads/external/tint/"*"_core.sh" + rm -f "./payloads/external/tint/tint-0.04-nmu1_libpayload.patch" + fi + if [ "$1" = "seabios" ] ; then + rm -f "./payloads/external/SeaBIOS/"*".patch" + fi + patch -p1 < "./$1.diff" + if [ "$1" = "atombios" ] ; then + chmod +x "./"*"_$1_roms.sh" + "./extract_$1_roms.sh" + printf "\n" + if ! "./check_$1_roms.sh" ; then + printf "%31s\n" "$7$1 - FAILURE_3" >> "$6" + csb_printer "$6" + exit 1 + fi + fi + if [ "$1" = "tint" ] ; then + chmod +x "./payloads/external/tint/"*"_core.sh" + fi + fi + touch ".$1" + printf "%25s\n" "$7$1 - YES" >> "$6" + if [ "$1" = "atombios" ] ; then + encontinue + fi + else + printf "%24s\n" "$7$1 - NO" >> "$6" + printf "\n${bold}You can apply it later by running:${bend}" + if [ "$1" = "dgpu" ] ; then + printf "\n${bold} ./apply_$1_patches.sh${bend}\n" + else + printf "\n${bold} patch -p1 < ./$1.diff${bend}\n" + fi + encontinue + fi + fi + if checker "$1" "config" ; then + rm -f "./configs/$1_"* + patch -p1 < "./$1.diff" + printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n" + ls "./configs" > "./.csb_configs" + csb_patcher_config_name=$( grepper "$1" "./.csb_configs" ) + rm -f "./.csb_configs" + printf "\n${bold}$csb_patcher_config_name could now be found at ./configs/${bend}" + printf "\n${bold}To use it, it should be copied to '.config' of your ./coreboot directory.${bend}\n\n" + if [ -f "./.config" ] ; then + printf "\n${byellow}WARNING${bend}: copying it to ./.config will overwrite your current '.config'\n\n" + fi + if yesno "Copy it to ./.config now?" "" ; then + copier "./configs/$csb_patcher_config_name" "./.config" + printf "\n" + printf "%25s\n" "$7$1 - YES" >> "$6" + if yesno "Configure this ./.config now?" "" ; then + csb_configurer "./.config" + else + printf "\n${bold}You can configure it later by running:${bend}" + printf "\n${bold} ./csb_patcher.sh config${bend}\n\n" + fi + else + printf "%24s\n" "$7$1 - NO" >> "$6" + printf "\n${bold}You can copy it later by running:${bend}" + printf "\n${bold} cp ./configs/$csb_patcher_config_name ./.config${bend}\n" + fi + printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n" + encontinue + fi + printf "\n\n" + return 0 + else + printf "${bold}^^^ ! MISMATCH for a $7$1 patch ! Check sha256sum manually: sha256sum ./$1.diff${bend}\n" + printf "%31s\n" "$7$1 - FAILURE_2" >> "$6" + csb_printer "$6" + exit 1 + fi +} + +# +# Conveniently and securely gets, checks SHA256 and applies my collection of unofficial patches. +# $1 - filepath where to save a csb_patcher_log which will be printed later +# +csb_mass_patcher () { +### +### https://review.coreboot.org/c/coreboot/+/31929 +### G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches +### + csb_patcher "dgpu" "31929" "13" "ed0c44f" "eb461931a1f34a8263405138eb1bf8d32a1f460026449c9ec1a9b9e7d8383f1c" "$1" "G505S " +### +### https://review.coreboot.org/c/coreboot/+/31944 +### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 +### + csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD " +### +### https://review.coreboot.org/c/coreboot/+/23856 +### tint: introduce the new tint build system with checksum verification +### + csb_patcher "tint" "23856" "15" "14630b6" "7b9719f675d83750c7d4fb21b3abcbf1758ac6d1db20a9e8ef0db22f15761317" "$1" "" +### +### https://review.coreboot.org/c/coreboot/+/32351 +### SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb +### + csb_patcher "seabios" "32351" "5" "4a9c3cd" "58348b0514446856d07078af443ac8a24cd3be8178290e7361a48a86d213a43b" "$1" "" +### +### https://review.coreboot.org/c/coreboot/+/32352 +### configs: add Lenovo G505S sample configuration (use with dGPU patches) +### +csb_patcher "config.lenovo_g505s" "32352" "12" "348d8ce" "5b3b663b3afe3fe5729be2632201f3665e75ed3848996901322d3528ed6dd897" "$1" "" + + return 0 +} + +# Prints a usage info for this ./csb_patcher.sh script. +csb_usage () { + printf "${bold}===============${bend} ${bgreen}USAGE${bend} ${bold}================${bend}\n\n" + printf "${bold}./csb_patcher.sh${bend}\n" + printf " patch your coreboot source code\n\n" + printf "${bold}./csb_patcher.sh${bend} ${byellow}help${bend} ${bold}|${bend} ${byellow}usage${bend}\n" + printf " print this usage info\n\n" + printf "${bold}==================== Before building :${bend}\n\n" + printf "${bold}./csb_patcher.sh ${byellow}config${bend}\n" + printf " configure some popular options\n\n" + printf "${bold}==================== After building :${bend}\n\n" + printf "${bold}./csb_patcher.sh ${byellow}atom${bend}\n" + printf " add the AtomBIOS to coreboot.rom\n\n" + printf "${bold}./csb_patcher.sh ${byellow}flop${bend}\n" + printf " add the floppies to coreboot.rom\n\n" + printf "${bold}./csb_patcher.sh ${byellow}atomflop${bend}\n" + printf " both AtomBIOS VGA ROMs and floppies\n\n" + printf "${bold}./csb_patcher.sh${bend} ${byellow}print${bend}\n" + printf " print a ./.csb_patcher log\n\n" + return 0 +} + +# +# MAIN PART OF A CSB_PATCHER SCRIPT +# + +if [ -z "$1" ] ; then + csb_patcher_log="./.csb_patcher" + rm -f "$csb_patcher_log" + if ! command_exists "wget" || \ + ! command_exists "unzip" || \ + ! command_exists "sha256sum" || \ + ! command_exists "patch" ; then + exit 1 + fi + printf '\n\n' >> "$csb_patcher_log" + printf ' \\\\!//\n' >> "$csb_patcher_log" + printf ' (o o)\n' >> "$csb_patcher_log" + printf ' oOOo-(_)-oOOo\n' >> "$csb_patcher_log" + printf 'Hi! I am coreboot and SeaBIOS patcher\n' >> "$csb_patcher_log" + printf 'Please send your feedback to\n' >> "$csb_patcher_log" + printf ' Mike Banon <mikebdp2(a)gmail.com>\n' >> "$csb_patcher_log" + csb_printer "$csb_patcher_log" + encontinue + printf '\n=== CSB_PATCHER LOG. Patches applied?\n' >> "$csb_patcher_log" + + csb_mass_patcher "$csb_patcher_log" + + if yesno "Download a ${bold}floppies${bend} collection?" "" ; then + floppy_mass_downloader + printf "%25s\n" "floppies - YES" >> "$csb_patcher_log" + else + printf "\n" + printf "%24s\n" "floppies - NO" >> "$csb_patcher_log" + fi + + printf '==================== Bad files found?\n' >> "$csb_patcher_log" + csb_finder "orig" "$csb_patcher_log" "applied correctly although at slightly different lines, can ignore it." + csb_finder "rej" "$csb_patcher_log" "perhaps failed to apply, could result in a broken build! ${bred}Please report${bend}" + + printf '\n' >> "$csb_patcher_log" + csb_printer "$csb_patcher_log" + csb_usage +else + case "$1" in + *"print"*) + csb_patcher_log="./.csb_patcher" + csb_printer "$csb_patcher_log" + ;; + *"config"*) + csb_configurer "./.config" + ;; + *"atom"*|*"flop"*) + if ! command_exists "wget" || \ + ! command_exists "unzip" || \ + ! command_exists "sha256sum" ; then + exit 1 + fi + cbfs_mass_adder "$1" "./build/cbfstool" "./build/coreboot.rom" "./build/coreflop.rom" + ;; + *"help"*|*"usage"*) + printf "\n" + csb_usage + ;; + *) + printf "\n${bred}ERROR${bend}: unknown argument ${bold}$1${bend} !\n\n" + csb_usage + exit 1 + ;; + esac +fi + +exit 0 + -- To view, visit https://review.coreboot.org/c/coreboot/+/33509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49 Gerrit-Change-Number: 33509 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 100

Change in coreboot[master]: soc/amd: Use uinptr_t over void *
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36562 ) Change subject: soc/amd: Use uinptr_t over void * ...................................................................... soc/amd: Use uinptr_t over void * This reduces the amount casts needed and makes it easier to catch type errors. Change-Id: I24792f45a8e6d70daabd43203df88310681af875 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/include/arch/bert_storage.h M src/security/memory/memory_clear.c M src/soc/amd/picasso/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c 6 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/36562/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 130f97a..828b0e7 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -32,7 +32,7 @@ * manage the space. */ static int bert_region_broken; -static void *bert_region_base; +static uintptr_t bert_region_base; static size_t bert_region_size; static size_t bert_region_used; @@ -49,10 +49,10 @@ return bert_region_broken ? 0 : !!bert_region_used; } -void bert_errors_region(void **start, size_t *size) +void bert_errors_region(uintptr_t *start, size_t *size) { if (bert_region_broken) { - *start = NULL; + *start = 0; *size = 0; return; } @@ -538,11 +538,11 @@ /* The region must be in memory marked as reserved. If not implemented, * skip generating the information in the region. */ -__weak void bert_reserved_region(void **start, size_t *size) +__weak void bert_reserved_region(uintptr_t *start, size_t *size) { printk(BIOS_ERR, "Error: %s not implemented. BERT region generation disabled\n", __func__); - *start = NULL; + *start = 0; *size = 0; } @@ -562,7 +562,7 @@ return; } - memset(bert_region_base, 0, bert_region_size); + memset((void *)bert_region_base, 0, bert_region_size); } RAMSTAGE_CBMEM_INIT_HOOK(bert_storage_setup) diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 644f24e..f277a67 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -53,12 +53,12 @@ */ /* Get implementation-specific reserved area for generating BERT info */ -void bert_reserved_region(void **start, size_t *size); +void bert_reserved_region(uintptr_t *start, size_t *size); /* Get the region where BERT error structures have been constructed for * generating the ACPI table */ -void bert_errors_region(void **start, size_t *size); +void bert_errors_region(uintptr_t *start, size_t *size); /* Get amount of available storage left for error info */ size_t bert_storage_remaining(void); diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 45bee91..7394f81 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -88,14 +88,14 @@ BM_MEM_RAM); /* Add reserved entries */ - void *baseptr = NULL; + uintptr_t baseptr = 0; size_t size = 0; /* Only skip CBMEM, as RELOCATABLE_RAMSTAGE is a requirement, no need * to separately protect stack or heap */ cbmem_get_region(&baseptr, &size); - memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE); + memranges_insert(&mem, baseptr, size, BM_MEM_TABLE); if (CONFIG(PLATFORM_USES_FSP1_0)) { /* Protect CBMEM pointer */ diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index c56ac5e..b1465b2 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -49,12 +49,12 @@ #define BERT_REGION_MAX_SIZE 0 #endif -void bert_reserved_region(void **start, size_t *size) +void bert_reserved_region(uintptr_t *start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = (void *)cbmem_top(); + *start = cbmem_top(); else - *start = NULL; + *start = 0; *size = BERT_REGION_MAX_SIZE; } diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 8304ba3..88eafde 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -49,12 +49,12 @@ #define BERT_REGION_MAX_SIZE 0 #endif -void bert_reserved_region(void **start, size_t *size) +void bert_reserved_region(uintptr_t *start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = (void *)cbmem_top(); + *start = cbmem_top(); else - *start = NULL; + *start = 0; *size = BERT_REGION_MAX_SIZE; } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d08722e..f873747 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -254,7 +254,7 @@ * a table with a 0-length region: * BERT: [Firmware Bug]: table invalid. */ - void *rgn; + uintptr_t rgn; size_t size; bert_errors_region(&rgn, &size); if (!rgn) { @@ -262,7 +262,7 @@ } else { current = ALIGN(current, 8); bert = (acpi_bert_t *)current; - acpi_write_bert(bert, (uintptr_t)rgn, size); + acpi_write_bert(bert, rgn, size); acpi_add_table(rsdp, (void *)current); current += bert->header.length; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24792f45a8e6d70daabd43203df88310681af875 Gerrit-Change-Number: 36562 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019