coreboot-gerrit November 2019

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Change in coreboot[master]: lib/imd: Use uintptr_t over void *
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36561 ) Change subject: lib/imd: Use uintptr_t over void * ...................................................................... lib/imd: Use uintptr_t over void * This reduces the number of casts. Change-Id: I3c41963202e5912da7c96ed8236e80e8bc27a4ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cbmem.h M src/include/imd.h M src/lib/fit_payload.c M src/lib/imd.c M src/lib/imd_cbmem.c 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36561/1 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4767c80..c5d8d58 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -110,7 +110,7 @@ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); /* Return the cbmem memory used */ -void cbmem_get_region(void **baseptr, size_t *size); +void cbmem_get_region(uintptr_t *baseptr, size_t *size); void cbmem_list(void); void cbmem_add_records_to_cbtable(struct lb_header *header); diff --git a/src/include/imd.h b/src/include/imd.h index cd2d297..09db1d9 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -101,7 +101,7 @@ int imd_lockdown(struct imd *imd); /* Fill in base address and size of region used by imd. */ -int imd_region_used(struct imd *imd, void **base, size_t *size); +int imd_region_used(struct imd *imd, uintptr_t *base, size_t *size); /* Add an entry to the imd. If id already exists NULL is returned. */ const struct imd_entry *imd_entry_add(const struct imd *imd, uint32_t id, diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 1b6c986..f719352 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -127,7 +127,7 @@ { u32 addr_cells = 1, size_cells = 1; u64 reg_addrs[2], reg_sizes[2]; - void *baseptr = NULL; + uintptr_t baseptr = 0; size_t size = 0; static const char *firmware_path[] = {"firmware", NULL}; @@ -163,7 +163,7 @@ return; } - reg_addrs[1] = (uintptr_t)baseptr; + reg_addrs[1] = baseptr; reg_sizes[1] = size; dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2, addr_cells, diff --git a/src/lib/imd.c b/src/lib/imd.c index bedcfa8..b24a6f5 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -524,11 +524,11 @@ return 0; } -int imd_region_used(struct imd *imd, void **base, size_t *size) +int imd_region_used(struct imd *imd, uintptr_t *base, size_t *size) { struct imd_root *r; struct imd_entry *e; - void *low_addr; + uintptr_t low_addr; size_t sz_used; if (!imd->lg.limit) @@ -542,10 +542,10 @@ /* Use last entry to obtain lowest address. */ e = root_last_entry(r); - low_addr = relative_pointer(r, e->start_offset); + low_addr = (uintptr_t)r + e->start_offset; /* Total size used is the last entry's base up to the limit. */ - sz_used = imd->lg.limit - (uintptr_t)low_addr; + sz_used = imd->lg.limit - low_addr; *base = low_addr; *size = sz_used; diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index be135c2..3d5f653 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -295,14 +295,14 @@ void cbmem_add_bootmem(void) { - void *baseptr = NULL; + uintptr_t baseptr = 0; size_t size = 0; cbmem_get_region(&baseptr, &size); - bootmem_add_range((uintptr_t)baseptr, size, BM_MEM_TABLE); + bootmem_add_range(baseptr, size, BM_MEM_TABLE); } -void cbmem_get_region(void **baseptr, size_t *size) +void cbmem_get_region(uintptr_t *baseptr, size_t *size) { imd_region_used(cbmem_get_imd(), baseptr, size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c41963202e5912da7c96ed8236e80e8bc27a4ed Gerrit-Change-Number: 36561 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: lib/cbmem: Change the return type of cbmem_top to uinptr_t
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36559 ) Change subject: lib/cbmem: Change the return type of cbmem_top to uinptr_t ...................................................................... lib/cbmem: Change the return type of cbmem_top to uinptr_t This allows to remove a lot of casts. Change-Id: I13c592b81f088b84703ca2f69b08890284c69f26 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cbmem.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/include/imd.h M src/lib/ext_stage_cache.c M src/lib/imd.c M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/fsp_rangeley/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/via/vx900/memmap.c M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/imgtec/pistachio/cbmem.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_baytrail/northcluster.c M src/soc/intel/fsp_broadwell_de/memmap.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/skylake/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 66 files changed, 146 insertions(+), 150 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/36559/1 diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 16c35b5..caaa3d9 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -16,16 +16,16 @@ #if CONFIG(CBMEM_TOP_BACKUP) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - static void *cbmem_top_backup; - void *top_backup; + static uintptr_t cbmem_top_backup; + uintptr_t top_backup; if (ENV_RAMSTAGE && cbmem_top_backup != NULL) return cbmem_top_backup; /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - top_backup = (void *)restore_top_of_low_cacheable(); + top_backup = restore_top_of_low_cacheable(); if (ENV_RAMSTAGE) cbmem_top_backup = top_backup; diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 3946b67..f7326c7 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -86,9 +86,9 @@ return cc6_size; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t topmem = rdmsr(TOP_MEM).lo; - return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); + return topmem - get_uma_memory_size(topmem) - get_cc6_memory_size(); } diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index a626ec6..116d82d 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return (uintptr_t)_dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..988eaf6 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -57,7 +57,7 @@ * writeback possible. */ - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); @@ -90,7 +90,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB, diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 2039c9c..2ea4e1b 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -29,7 +29,7 @@ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 59a60cf..21dc431 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -151,7 +151,7 @@ } /* Migrate CAR data */ - printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + printk(BIOS_DEBUG, "0x%"PRIxPTR": cbmem_top\n", cbmem_top()); if (!s3wake) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index e2937d7..e4901b4 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -61,8 +61,8 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%p: cbmem_top\n", + if (range_entry_end(&tolum) != cbmem_top()) { + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != 0x%"PRIxPTR": cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4005fa2..4767c80 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -73,7 +73,7 @@ * below 4GiB for 32bit coreboot builds. On 64bit coreboot builds there's no * upper limit. This should not be called before memory is initialized. */ -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/include/imd.h b/src/include/imd.h index 6575312..cd2d297 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -59,7 +59,7 @@ * to be called at least once before any other imd related functions * can be used. */ -void imd_handle_init(struct imd *imd, void *upper_limit); +void imd_handle_init(struct imd *imd, uintptr_t upper_limit); /* * Initialize a handle with a shallow recovery. This function doesn't diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 354342d..52c0d6f 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -36,7 +36,7 @@ imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + (uintptr_t)base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); @@ -52,7 +52,7 @@ imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + imd_handle_init(imd, size + (uintptr_t)base); if (imd_recover(imd)) printk(BIOS_DEBUG, "Unable to recover external stage cache.\n"); } diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9..bedcfa8 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -132,9 +132,9 @@ e->id = id; } -static void imdr_init(struct imdr *ir, void *upper_limit) +static void imdr_init(struct imdr *ir, uintptr_t upper_limit) { - uintptr_t limit = (uintptr_t)upper_limit; + uintptr_t limit = upper_limit; /* Upper limit is aligned down to 4KiB */ ir->limit = ALIGN_DOWN(limit, LIMIT_ALIGN); ir->r = NULL; @@ -396,10 +396,10 @@ } /* Initialize imd handle. */ -void imd_handle_init(struct imd *imd, void *upper_limit) +void imd_handle_init(struct imd *imd, uintptr_t upper_limit) { imdr_init(&imd->lg, upper_limit); - imdr_init(&imd->sm, NULL); + imdr_init(&imd->sm, 0); } void imd_handle_init_partial_recovery(struct imd *imd) @@ -411,7 +411,7 @@ if (imd->lg.limit == 0) return; - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); /* Initialize root pointer for the large regions. */ imdr = &imd->lg; @@ -468,7 +468,7 @@ return 0; fail: - imd_handle_init(imd, (void *)imdr->limit); + imd_handle_init(imd, imdr->limit); return -1; } @@ -495,7 +495,7 @@ /* Tear down any changes on failure. */ if (imdr_recover(&imd->sm) != 0) { - imd_handle_init(imd, (void *)imd->lg.limit); + imd_handle_init(imd, imd->lg.limit); return -1; } diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index c50254d..0675777 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -10,7 +10,7 @@ #include <ramdetect.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 542e08d..bdae66d 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -15,7 +15,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 8209379..c80cf2e 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -52,15 +52,15 @@ return tomk; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t top = 0; top = fw_cfg_tolud(); if (!top) - top = (uintptr_t)qemu_get_memory_size() * 1024; + top = qemu_get_memory_size() * 1024; - return (void *)top; + return top; } /* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 3df6b80..4391cdb 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -15,10 +15,9 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ - void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (1ULL << 32) - 1048576; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index c6a20fa..372004a 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -21,7 +21,7 @@ #include <program_loading.h> #include "e7505.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -30,7 +30,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27; - return (void *)tolm; + return tolm; } void northbridge_write_smram(u8 smram); @@ -58,7 +58,7 @@ postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c index da9ed71..bdd6466 100644 --- a/src/northbridge/intel/fsp_rangeley/memmap.c +++ b/src/northbridge/intel/fsp_rangeley/memmap.c @@ -36,7 +36,7 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); + return smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 7479a78..d588088 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -117,10 +117,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) @@ -136,7 +135,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e652090..df24282 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -137,7 +137,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - (cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 007a67d..f0e874b 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -34,9 +34,9 @@ return tom & ~((1 << 20) - 1); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 75a6c7e..112eee3 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -23,7 +23,7 @@ #include <program_loading.h> #include "i440bx.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -63,7 +63,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return tom; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -71,7 +71,7 @@ uintptr_t top_of_ram; /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 8207d06..d2423ff 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -71,10 +71,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dde1b11..10fcccb 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -105,7 +105,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = ((uint32_t)cbmem_top() >> 10); + cbmem_topk = cbmem_top() >> 10; delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem; diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index 1c17b0d..1116b60 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -42,9 +42,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index b4fef6b..c689c6e 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -132,11 +132,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; - + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) @@ -152,7 +150,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index fc71bc3..c6fd7b7 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -103,7 +103,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = (uint32_t)cbmem_top() >> 10; + cbmem_topk = cbmem_top() >> 10; delta_cbmem = tomk - cbmem_topk; tomk -= delta_cbmem; diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 67de344..65720ed 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -31,9 +31,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } static uintptr_t northbridge_get_tseg_base(void) @@ -56,7 +56,7 @@ { uintptr_t top_of_ram; - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 41e4912..8ac63af 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -128,10 +128,9 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); } void smm_region(uintptr_t *start, size_t *size) @@ -147,7 +146,7 @@ /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 39f24d3..49476ae 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -89,7 +89,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - (cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index d11dc65..8a3a2b7 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -120,7 +120,7 @@ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t tolm; uintptr_t fb_size; @@ -131,5 +131,5 @@ if (tolm > 0xfc0 || tolm <= 0x3ff || fb_size == 0x0) return NULL; - return (void *)((tolm - fb_size) << 20); + return (tolm - fb_size) << 20; } diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 09af7e4..c56ac5e 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -52,13 +52,13 @@ void bert_reserved_region(void **start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); + *start = (void *)cbmem_top(); else - start = NULL; + *start = NULL; *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -66,14 +66,14 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); + return ALIGN_DOWN(restore_top_of_low_cacheable() + - CONFIG_SMM_TSEG_SIZE + - BERT_REGION_MAX_SIZE, 8*MiB); } static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 08807f3..901622d 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -263,7 +263,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 257ae67..9ccb11b 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -76,7 +76,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 09af7e4..8304ba3 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -52,13 +52,13 @@ void bert_reserved_region(void **start, size_t *size) { if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); + *start = (void *)cbmem_top(); else - start = NULL; + *start = NULL; *size = BERT_REGION_MAX_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { msr_t tom = rdmsr(TOP_MEM); @@ -73,7 +73,7 @@ static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; + return cbmem_top() + BERT_REGION_MAX_SIZE; } static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..d08722e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -415,7 +415,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 2228c1a..936907f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -162,7 +162,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index bb6fa18..a9fd213 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -20,7 +20,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* Make sure not to overlap with reserved ATF scratchpad */ return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7c..c5fffa6 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -18,7 +18,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { return _dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 7b60270..a7f2ff6 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -26,10 +26,10 @@ #include "chip.h" -void *cbmem_top(void) +uintptr_t cbmem_top(void) { const config_t *config; - void *tolum = (void *)sa_get_tseg_base(); + uintptr_t tolum = sa_get_tseg_base(); if (!CONFIG(SOC_INTEL_GLK)) return tolum; @@ -58,7 +58,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index d9f6160..3a1bfd9 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -29,9 +29,9 @@ return CONFIG_SMM_TSEG_SIZE; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) smm_region_start(); + return smm_region_start(); } void smm_region(uintptr_t *start, size_t *size) @@ -48,7 +48,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d502aed..dab9234 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -33,7 +33,7 @@ *size = smm_region_size(); } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uintptr_t smm_base; size_t smm_size; @@ -67,5 +67,5 @@ */ smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f4a9d0e..483e7be 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -41,9 +41,9 @@ return tom; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 96218f4..df446de 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -41,7 +41,7 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + top_of_ram = ALIGN_DOWN(cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 80aa97d..6d4aa9a 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -253,13 +253,13 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -271,7 +271,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e03942f..8b99d17 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -154,7 +154,7 @@ uintptr_t top_of_ram; int index = *resource_count; - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); /* 0 - > 0xa0000 */ base_k = 0; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 9f788dd..aca1d97 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -60,7 +60,10 @@ power_of_2(iqat_region_size + tseg_region_size); } -void *cbmem_top(void) { return (void *)top_of_32bit_ram(); } +uintptr_t cbmem_top(void) +{ + return top_of_32bit_ram(); +} static inline uintptr_t smm_region_start(void) { @@ -87,7 +90,7 @@ * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 7fec7f9..4aee8a1 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -40,9 +40,9 @@ * @return pointer to the first byte of reserved memory */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); + return (uintptr_t)find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 797039a..232263c 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -125,7 +125,7 @@ uint32_t fsp_mem_base = 0; GetHighMemorySize(&highmem_size); - fsp_mem_base=(uint32_t)cbmem_top(); + fsp_mem_base = cbmem_top(); bmbound = iosf_bunit_read(BUNIT_BMBOUND); bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c index cbd3cf7..2e6f1f6 100644 --- a/src/soc/intel/fsp_broadwell_de/memmap.c +++ b/src/soc/intel/fsp_broadwell_de/memmap.c @@ -23,9 +23,9 @@ #include <soc/pci_devs.h> #include <device/pci_ops.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); + return (uintptr_t)find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR); } /* diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 00f45cf..2afa849 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -232,13 +232,13 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -250,7 +250,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index b8b8506..c0f326e 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -18,7 +18,7 @@ #include <cbmem.h> #include <soc/reg_access.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { uint32_t top_of_memory; @@ -32,7 +32,7 @@ top_of_memory -= 0x10000; /* Return the top of memory */ - return (void *)top_of_memory; + return top_of_memory; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -41,7 +41,7 @@ uintptr_t top_of_low_usable_memory; /* Locate the top of RAM */ - top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_low_usable_memory = cbmem_top(); top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); /* Cache postcar and ramstage */ diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c index 0507efc..c10f002 100644 --- a/src/soc/intel/quark/northcluster.c +++ b/src/soc/intel/quark/northcluster.c @@ -55,7 +55,7 @@ /* 0x100000 -> cbmem_top - cacheable and usable */ base_k += size_k; - size_k = (unsigned long)cbmem_top() - base_k; + size_k = cbmem_top() - base_k; ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); /* cbmem_top -> 0xc0000000 - reserved */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index c6ccd71..688c69b 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -254,13 +254,13 @@ * | | * +-------------------------+ */ -void *cbmem_top(void) +uintptr_t cbmem_top(void) { struct ebda_config ebda_cfg; retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return ebda_cfg.tolum_base; } void fill_postcar_frame(struct postcar_frame *pcf) @@ -273,7 +273,7 @@ * Instruct postcar to cache 16 megs under cbmem top which is * a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = cbmem_top(); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index 8906565..7d0aad6 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -21,7 +21,7 @@ #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB) -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 4b52a51..d11816a 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -17,7 +17,7 @@ #include <soc/display.h> #include <soc/sdram.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index 63ae497..21f8819 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -16,7 +16,7 @@ #include <cbmem.h> #include <soc/addressmap.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { static uintptr_t addr; @@ -32,5 +32,5 @@ addr = end_mib << 20; } - return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 05325cc..dc2c721 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -32,7 +32,7 @@ * for loading ipq blobs before DRAM is initialized). */ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 9674db6..54bdba2 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -23,7 +23,7 @@ cbmem_backing_store_ready = 1; } -void *cbmem_top(void) +uintptr_t cbmem_top(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -33,7 +33,7 @@ * initialized). */ if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) - return NULL; + return 0; - return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index e065409..b9f70a4 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)3 * GiB); + return 3 * GiB; } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 597e369..833c9d2 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return 4 * GiB; } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 3b9ad4a..1cacbf4 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -15,7 +15,7 @@ #include <cbmem.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)((uintptr_t)4 * GiB); + return 4 * GiB; } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 401f8b2..105e178 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -19,8 +19,8 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, + return min((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 1874495..dc02577 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <soc/cpu.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index e1999e8..de75663 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -17,7 +17,7 @@ #include <soc/cpu.h> #include <stddef.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)(get_fb_base_kb() * KiB); + return get_fb_base_kb() * KiB; } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index 1c68de8..facc714 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -19,8 +19,7 @@ #include <stdlib.h> #include <symbols.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB, - FU540_MAXDRAM); + return min((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 542e08d..bdae66d 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -15,7 +15,7 @@ #include <symbols.h> #include <ramdetect.h> -void *cbmem_top(void) +uintptr_t cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return (uintptr_t)_dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c592b81f088b84703ca2f69b08890284c69f26 Gerrit-Change-Number: 36559 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: emulation/riscv: Don't probe for total DRAM
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36445 ) Change subject: emulation/riscv: Don't probe for total DRAM ...................................................................... emulation/riscv: Don't probe for total DRAM Trying accessing memory that is not there causes an exception. Change-Id: Ic4d9fbb727f41436798783a357b3cfb7b64d3edb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/mainboard.c M src/soc/ucb/riscv/cbmem.c 3 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36445/1 diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..c3136c1 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -55,8 +55,8 @@ default 1 config DRAM_SIZE_MB - int - default 32768 + int "size of DRAM. Run qemu with the argument -m ***M" + default 1024 config OPENSBI_PLATFORM string diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index 88898087..eda43c9 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -27,7 +27,7 @@ die("No dev0; die\n"); } - dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); + dram_mb_detected = CONFIG_DRAM_SIZE_MB - CONFIG_ROM_SIZE; ram_resource(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB); cbmem_recovery(0); diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 542e08d..9872760 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -13,9 +13,8 @@ #include <cbmem.h> #include <symbols.h> -#include <ramdetect.h> void *cbmem_top(void) { - return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); + return _dram + CONFIG_DRAM_SIZE_MB * MiB - CONFIG_ROM_SIZE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4d9fbb727f41436798783a357b3cfb7b64d3edb Gerrit-Change-Number: 36445 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/*/*: Don't guard serial setup
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36603 ) Change subject: mb/*/*: Don't guard serial setup ...................................................................... mb/*/*: Don't guard serial setup Even without using the console it might be useful to set up the console regardless, for instance with VBOOT or normal/fallback setups. This will be more meaningful once C_ENVIRONMENT_BOOTBLOCK is implemented. Change-Id: Ieca2ec1e376cdb26d76222126307fe016572d9d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/ocp/wedge100s/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36603/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 258eac7..b0dd962 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -58,8 +58,7 @@ void mainboard_config_superio(void) { - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 6c139ed..e07007c 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -58,8 +58,7 @@ void mainboard_config_superio(void) { - if (CONFIG(CONSOLE_SERIAL)) - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } void mainboard_get_spd(spd_raw_data *spd, bool id_only) diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index 108d7a1..c0d2ca0 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -42,8 +42,7 @@ pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1); - if (CONFIG(CONSOLE_SERIAL)) - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/36603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca2ec1e376cdb26d76222126307fe016572d9d7 Gerrit-Change-Number: 36603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: *.asl: Don't define Devices by absolute path
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36600 ) Change subject: *.asl: Don't define Devices by absolute path ...................................................................... *.asl: Don't define Devices by absolute path Be consistent with the rest tree and set the scope first when defining devices. In general make the resulting code more readable as it avoid '^' symbols. Change-Id: I0b8dd33fac7cb1524d920b77e95c08b839157e8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/h61m-cs/dsdt.asl M src/mainboard/asus/p8z77-m_pro/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/msi/ms7707/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl M util/autoport/main.go 7 files changed, 42 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36600/1 diff --git a/src/mainboard/asus/h61m-cs/dsdt.asl b/src/mainboard/asus/h61m-cs/dsdt.asl index 0e1cc3a..a1a70c0 100644 --- a/src/mainboard/asus/h61m-cs/dsdt.asl +++ b/src/mainboard/asus/h61m-cs/dsdt.asl @@ -32,9 +32,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 1c7a620..2c14e8f 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -34,10 +34,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index 7ee12a0..e54b01b 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -37,10 +37,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 82358aa..fd37f9e 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -37,10 +37,11 @@ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl index d3e3602..6df1394 100644 --- a/src/mainboard/msi/ms7707/dsdt.asl +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -32,10 +32,11 @@ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/common/acpi/sleepstates.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 6ed19ee..8649a95 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -24,10 +24,11 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> #include <cpu/intel/common/acpi/cpu.asl> - Device (\_SB.PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + Scope (\_SB) { + Device (PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } } } diff --git a/util/autoport/main.go b/util/autoport/main.go index 03523a2..51d10cf 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -876,17 +876,20 @@ } dsdt.WriteString(` - Device (\_SB.PCI0) + Scope (\_SB) { + Device (PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) } - fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + fmt.Fprintf(dsdt, "\t\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } + ` } + } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/36600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8dd33fac7cb1524d920b77e95c08b839157e8f Gerrit-Change-Number: 36600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35884 ) Change subject: soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place ...................................................................... soc/intel/Kconfig: Move MMCONF_BASE_ADDRESS out of a common place include/device/pci_mmio_cfg.h now has a compile time error if MMCONF_BASE_ADDRESS is not defined. This requires soc/intel target to explicitly set this in the SOC dir, instead of potentially using a possibly wrong common default. Change-Id: Idcfea1718cc36ae16b491604786c26c6ed320f06 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/skylake/Kconfig 5 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35884/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a1d3c07..24a4b7a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -128,6 +128,10 @@ TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config PCR_BASE_ADDRESS hex default 0xd0000000 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c1fda95..aeef75c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -109,6 +109,10 @@ select FSP_T_XIP if FSP_CAR select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573..d7619a0 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,10 +3,6 @@ help Intel Processor common System Agent support -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config SA_PCIEX_LENGTH hex default 0x10000000 if (PCIEX_LENGTH_256MB) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae..d12e4e3 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -91,6 +91,10 @@ int default 16 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 901e5f9..a9b8aaa 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -120,6 +120,10 @@ hex default 0x200000 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config DCACHE_RAM_BASE hex default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcfea1718cc36ae16b491604786c26c6ed320f06 Gerrit-Change-Number: 35884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

9 19

Change in coreboot[master]: soc/intel/common/block/sa: Add compiletime error on undefined SA_PCIE...
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35887 ) Change subject: soc/intel/common/block/sa: Add compiletime error on undefined SA_PCIE_LENGTH ...................................................................... soc/intel/common/block/sa: Add compiletime error on undefined SA_PCIE_LENGTH Change-Id: Ib9facecc4caa869e65f938a55508741dd48b09b0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35887/1 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index d7619a0..81a7f9d 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -8,7 +8,6 @@ default 0x10000000 if (PCIEX_LENGTH_256MB) default 0x8000000 if (PCIEX_LENGTH_128MB) default 0x4000000 if (PCIEX_LENGTH_64MB) - default 0x10000000 help This option allows you to select length of PCIEX region. diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 8c89c07..5411238 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -26,6 +26,10 @@ #include "systemagent_def.h" +#if CONFIG_SA_PCIEX_LENGTH == 0 +#error "SA_PCIEX_LENGTH undefined!" +#endif + void bootblock_systemagent_early_init(void) { uint32_t reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/35887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9facecc4caa869e65f938a55508741dd48b09b0 Gerrit-Change-Number: 35887 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: arch/x86/car.ld: Use REGION macro
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36696 ) Change subject: arch/x86/car.ld: Use REGION macro ...................................................................... arch/x86/car.ld: Use REGION macro The advantages of using the REGION macro: - less boilerplate for defining start and end symbols - overlap between regions checking - automatic alignment Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 4 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/36696/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 74fc74b..c601d2e 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -18,9 +18,7 @@ #if CONFIG(PAGING_IN_CACHE_AS_RAM) /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ - _pagetables = . ; - . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; - _epagetables = . ; + REGION(pagetables, ., 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4096) #endif /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ @@ -37,9 +35,7 @@ * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) - _car_stack = .; - . += CONFIG_DCACHE_BSP_STACK_SIZE; - _ecar_stack = .; + REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 16) #endif /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that @@ -47,22 +43,17 @@ * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if CONFIG(PAGING_IN_CACHE_AS_RAM) - . = ALIGN(32); /* Page directory pointer table resides here. There are 4 8-byte entries * totalling 32 bytes that need to be 32-byte aligned. The reason the * pdpt are not colocated with the rest of the page tables is to reduce * fragmentation of the CAR space that persists across stages. */ - _pdpt = .; - . += 32; - _epdpt = .; + REGION(pdpt, ., 32, 32) #endif TIMESTAMP(., 0x200) - _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ - . += 80; - _ecar_ehci_dbg_info = .; + REGION(car_ehci_dbg_info, ., 80, ARCH_POINTER_ALIGN_SIZE) /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -114,9 +105,6 @@ } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -#if CONFIG(PAGING_IN_CACHE_AS_RAM) -_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); -#endif #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee Gerrit-Change-Number: 36696 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: src/soc/intel/fsp-car: Align stack before jumping to C code
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37279 ) Change subject: src/soc/intel/fsp-car: Align stack before jumping to C code ...................................................................... src/soc/intel/fsp-car: Align stack before jumping to C code GCC has had a 16 byte stack requirement since quite some time now... Change-Id: I0f5b62b5fef3ca7ec6d9010723527a356eb566ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37279/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index d7ef834..4174f36 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -99,6 +99,10 @@ xorl %eax, %eax rep stosl + /* Need to align stack to 16 bytes at call instruction. Account for + the two pushes below. */ + andl $0xfffffff0, %esp + sub $8, %esp /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/37279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5b62b5fef3ca7ec6d9010723527a356eb566ed Gerrit-Change-Number: 37279 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/fsp-car: Clear the whole usable CAR region
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37277 ) Change subject: soc/intel/fsp-car: Clear the whole usable CAR region ...................................................................... soc/intel/fsp-car: Clear the whole usable CAR region Other symbols in car.ld likely expect to be zero initialized. Change-Id: I44a0d3947eb6dd67dfd2d7f03e5c0766b043f61b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37277/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a..ec43311 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -89,13 +89,14 @@ /* Setup bootblock stack */ mov %edx, %esp - /* clear .bss section as it is not shared */ + /* coreboot assumes CAR region will be zero */ cld - xor %eax, %eax - movl $(_ebss), %ecx - movl $(_bss), %edi - sub %edi, %ecx + movl %ecx, %edi + neg %ecx + /* Clear up to Temp Ram top. */ + add %edx, %ecx shrl $2, %ecx + xorl %eax, %eax rep stosl /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44a0d3947eb6dd67dfd2d7f03e5c0766b043f61b Gerrit-Change-Number: 37277 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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