coreboot-gerrit November 2019

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Change in coreboot[master]: drivers/intel/fsp1.1: Use the coreboot symbols for the stack
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37276 ) Change subject: drivers/intel/fsp1.1: Use the coreboot symbols for the stack ...................................................................... drivers/intel/fsp1.1: Use the coreboot symbols for the stack We want to know where the stack is, to make sure that it does not override other CAR symbols. Change-Id: I9edf615bff11aa38fc307b4e2e2c97f1757a05a1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37276/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fea7acb..fb39884 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -143,8 +143,8 @@ cmp $0, %eax jne halt2 - /* Setup bootloader stack */ - movl %edx, %esp + /* Setup BSP stack */ + movl _ecar_stack, %esp /* * ebp: FSP_INFO_HEADER address -- To view, visit https://review.coreboot.org/c/coreboot/+/37276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edf615bff11aa38fc307b4e2e2c97f1757a05a1 Gerrit-Change-Number: 37276 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel: Remove unused CPU_ADDR_BITS Kconfig option
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33169 Change subject: cpu/intel: Remove unused CPU_ADDR_BITS Kconfig option ...................................................................... cpu/intel: Remove unused CPU_ADDR_BITS Kconfig option Change-Id: Ib5529ceeec9481e05c56f20af0d201f3d20ea3f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_106cx/Kconfig M src/lib/cbfs.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/packardbell/ms2290/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/skylake/Kconfig 6 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/33169/1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..91b5189 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -14,10 +14,4 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON -if CPU_INTEL_MODEL_106CX - -config CPU_ADDR_BITS - int - default 32 - endif diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..d4433df 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -273,7 +273,6 @@ memset(&load[fsize], 0, stage.memlen - fsize); prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); - out: prog_set_area(pstage, load, stage.memlen); prog_set_entry(pstage, entry, NULL); diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 69e2038..ad22cc4 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -47,10 +47,6 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - # Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA # controllers) don't work as expected config ME_CLEANER_ARGS diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index c6a1e12..20b520d 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -49,8 +49,4 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 217d1ea..91476c1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -158,10 +158,6 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. -config CPU_ADDR_BITS - int - default 39 - config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 100 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6..b67ddd7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -116,10 +116,6 @@ hex default 0x200000 -config CPU_ADDR_BITS - int - default 36 - config DCACHE_RAM_BASE hex default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/33169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5529ceeec9481e05c56f20af0d201f3d20ea3f9 Gerrit-Change-Number: 33169 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED]sb/intel/common: Deal with different save states
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36590 ) Change subject: [UNTESTED]sb/intel/common: Deal with different save states ...................................................................... [UNTESTED]sb/intel/common: Deal with different save states Some CPUs have different save states and have to be dealt with accordingly. updating the gnvs pointer is now done in a common place and fixes this on i82801xx targets. Change-Id: I63f77432cf4a2ef484ad320bfc321e9a923a19ab Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 47 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36590/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index ceac598..c4f1efb 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -211,16 +211,9 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs_ptr(uintptr_t offset) { - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + gnvs = (global_nvs_t *)offset; } void southbridge_finalize_all(void) diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index cea5c82..a5cd921 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -142,10 +142,10 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); +void set_gnvs_ptr(uintptr_t ptr); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +int smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 5582051..e85031d 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -215,13 +215,17 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +int smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { + if (get_save_state_type() == LEGACY) + if (((*(uintptr_t *)save_state_reg(node, SS_EAX)) & 0xff) != cmd) + continue; + state = smm_get_save_state(node); /* Check for Synchronous IO (bit0 == 1) */ @@ -240,10 +244,11 @@ if ((state->rax & 0xff) != cmd) continue; - return state; + return node; } - return NULL; + printk(BIOS_WARNING, "APMC node not found!\n"); + return -1; } #if CONFIG(ELOG_GSMI) @@ -251,18 +256,17 @@ { u32 *ret, *param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int apm_node = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (apm_node < 0) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; + ret = (u32*)save_state_reg(apm_node, SS_EAX); sub_command = (u8)(*ret >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + param = (u32*)save_state_reg(apm_node, SS_EBX); /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); @@ -272,21 +276,33 @@ static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uintptr_t reg_rbx; + int apm_node = smi_apmc_find_state_save(APM_CNT_SMMSTORE); + void *reg_rbx; - if (!io_smi) + if (apm_node < 0) return; /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + sub_command = (*(uintptr_t *)save_state_reg(apm_node, SS_EAX) >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_rbx = (uintptr_t)io_smi->rbx; + reg_rbx = save_state_reg(apm_node, SS_EBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_rbx); - io_smi->rax = ret; + ret = smmstore_exec(sub_command, reg_rbx); + *(uintptr_t *)save_state_reg(apm_node, SS_EAX) = ret; +} + +static void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +{ + int apm_node = smi_apmc_find_state_save(apm_cnt); + uintptr_t gnvs; + if (apm_node > 0) { + /* EBX in the state save contains the GNVS pointer */ + gnvs = *(uintptr_t *)save_state_reg(apm_node, SS_EBX); + set_gnvs_ptr(gnvs); + *smm_done = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } } static int mainboard_finalized = 0; diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 16ceb13..c697cf5 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -41,12 +41,11 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs_ptr(uintptr_t offset) { - gnvs = *(global_nvs_t **)0x500; - *smm_done = 1; + gnvs = (global_nvs_t *)offset; } int southbridge_io_trap_handler(int smif) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 8090a09..2edba39 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -28,9 +28,7 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; int southbridge_io_trap_handler(int smif) { @@ -49,12 +47,9 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs_ptr(uintptr_t offset) { - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; + gnvs = (global_nvs_t *)offset; } void southbridge_smi_monitor(void) diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 667a853..69a9e7a 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -35,9 +35,7 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; int southbridge_io_trap_handler(int smif) { @@ -56,12 +54,9 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs_ptr(uintptr_t offset) { - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; + gnvs = (global_nvs_t *)offset; } void southbridge_smi_monitor(void) diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..961d207 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -171,16 +171,9 @@ #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs_ptr(uintptr_t offset) { - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + gnvs = (global_nvs_t *)offset; } void southbridge_finalize_all(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/36590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f77432cf4a2ef484ad320bfc321e9a923a19ab Gerrit-Change-Number: 36590 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]Makefile.inc: Simplify generating the default fmap
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33275 Change subject: [WIP]Makefile.inc: Simplify generating the default fmap ...................................................................... [WIP]Makefile.inc: Simplify generating the default fmap Apparently you don't always need to specify base/size as fmap tool fills in the gaps, so make use of that to remove some ugly Makefile arithmetics. Change-Id: Ib138249140fc87307c3dc76692f343587117c7e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M util/cbfstool/default-x86.fmd 2 files changed, 7 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33275/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..13cb6ed 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -865,10 +865,9 @@ # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled -FMAP_CONSOLE_BASE := 0 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) -FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) +FMAP_CONSOLE_ENTRY := CONSOLE $(FMAP_CONSOLE_SIZE) else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := @@ -879,12 +878,9 @@ # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE)), 0x10000) FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) -FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) +FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE $(FMAP_MRC_CACHE_SIZE) else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := 0 FMAP_MRC_CACHE_SIZE := 0 FMAP_MRC_CACHE_ENTRY := endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -894,12 +890,9 @@ # # position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_SMMSTORE),y) -FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000) FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE) -FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE) +FMAP_SMMSTORE_ENTRY := SMMSTORE $(FMAP_SMMSTORE_SIZE) else # ifeq ($(CONFIG_SMMSTORE),y) -FMAP_SMMSTORE_BASE := 0 FMAP_SMMSTORE_SIZE := 0 FMAP_SMMSTORE_ENTRY := endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -909,16 +902,14 @@ # # # position, size -FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \ - $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE)) FMAP_FMAP_SIZE := 0x200 # # X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) -FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +FMAP_CBFS_SIZE := $(shell echo $($(FMAP_BIOS_SIZE) - $(FMAP_FMAP_SIZE) \ + - $(FMAP_CONSOLE_SIZE) - $(FMAP_MRC_CACHE_SIZE) - $(FMAP_SMMSTORE_SIZE))) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd # entire flash diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f0143e9..1d1fec9 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -12,7 +12,7 @@ ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## - FMAP@##FMAP_BASE## ##FMAP_SIZE## - COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + FMAP ##FMAP_SIZE## + COREBOOT(CBFS) ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib138249140fc87307c3dc76692f343587117c7e0 Gerrit-Change-Number: 33275 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33276 Change subject: [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes ...................................................................... [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes fmaptool can deal with it and it makes the file more readable. Not defining WR_RO and COREBOOT(CBFS) insures the bootblock is at the bottom of the flash. Change-Id: I4ed789acc8716942212fc5ab97fd722c8ea8c20d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x220/vboot-rwa.fmd 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/33276/1 diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..be06484 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -5,25 +5,25 @@ SI_ME@0x3000 0x4ed000 } SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed789acc8716942212fc5ab97fd722c8ea8c20d Gerrit-Change-Number: 33276 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus n...
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35879 ) Change subject: [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number ...................................................................... [WIP]coreboot_table: Add a record to hold the PCIE BASE + Total bus number This can be useful for PCI MMCONF access in payloads. Change-Id: I1c31fc439896715fb69a627672499ffb4112ee51 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35879/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6816670..3182e9e 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -90,6 +90,7 @@ LB_TAG_MMC_INFO = 0x0035, LB_TAG_TCPA_LOG = 0x0036, LB_TAG_FMAP = 0x0037, + LB_TAG_PCIE_BASE = 0x0038, LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, @@ -429,6 +430,13 @@ struct mac_address mac_addrs[0]; }; +struct lb_pcie_info { + uint32_t tag; + uint32_t size; + uint64_t base; + uint32_t bus_number; +}; + #define MAX_SERIALNO_LENGTH 32 /* The following structures are for the cmos definitions table */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d3576e6..6294762 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -452,6 +452,17 @@ */ void __weak lb_spi_flash(struct lb_header *header) { /* NOOP */ } +static void lb_pcie_base(struct lb_header *header) +{ + struct lb_pcie_base *rec; + rec = (struct lb_pcie_base *)lb_new_record(header); + rec->tab = LB_TAG_PCIE_BASE; + rec->size = sizeof(*rec); + rec->base = CONFIG_MMCONF_BASE_ADDRESS; + /* Coreboot only populates this value on AMD and VIA for now... */ + rec->bus_number = CONFIG_MMCONF_BUS_NUMBER; +} + static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { @@ -587,6 +598,9 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); + /* Add PCIE Base */ + lb_pcie_base(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c31fc439896715fb69a627672499ffb4112ee51 Gerrit-Change-Number: 35879 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/{baytrail,braswell}: Use a Kconfig symbol for max PCI BUS number
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35874 ) Change subject: intel/{baytrail,braswell}: Use a Kconfig symbol for max PCI BUS number ...................................................................... intel/{baytrail,braswell}: Use a Kconfig symbol for max PCI BUS number Change-Id: Ia7364b454feeca0c5f8db5fa72400cc8b078bd28 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c 4 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35874/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c833c53..bf0e221 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -51,6 +51,10 @@ hex default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + config MAX_CPUS int default 4 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c322cce..add5ec2 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -165,7 +165,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + MCFG_BASE_ADDRESS, 0, 0, + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d6438f..edb64ac 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -69,6 +69,10 @@ hex default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + config MAX_CPUS int default 4 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index dbd2950..c738869 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -140,7 +140,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + MCFG_BASE_ADDRESS, 0, 0, + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7364b454feeca0c5f8db5fa72400cc8b078bd28 Gerrit-Change-Number: 35874 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/acpi: Use the correct last PCI BUS
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35873 ) Change subject: soc/intel/broadwell/acpi: Use the correct last PCI BUS ...................................................................... soc/intel/broadwell/acpi: Use the correct last PCI BUS Use the correct last PCI BUS number. The MMCONF_BASE is 0xf000000 so 256 busses is most certainly wrong. The bootblock programs it to 64 busses, so the assumption is that the mrc.bin does not modify that. Change-Id: Id8a8d10e069f2ab6dd5c87d2df462d00c6fad11e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35873/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5856ef1..13fdd55 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -85,6 +85,10 @@ hex default 0xf0000000 +config MMCONF_BUS_NUMBER + int + default 64 + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 7acde68..b5b7f0b 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -219,7 +219,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + MCFG_BASE_ADDRESS, 0, 0, + CONFIG_MMCONF_BUS_NUMBER - 1); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8a8d10e069f2ab6dd5c87d2df462d00c6fad11e Gerrit-Change-Number: 35873 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Fix the ACPI PCIE MMCONF range
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35870 ) Change subject: nb/intel/nehalem: Fix the ACPI PCIE MMCONF range ...................................................................... nb/intel/nehalem: Fix the ACPI PCIE MMCONF range The QPI functions are at PCI bus 0xff. Change-Id: I064585e97b0a04decfcee0742f3258175d7930b9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/acpi/nehalem.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35870/1 diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index df8aad7..eff39b0 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -28,7 +28,7 @@ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -- To view, visit https://review.coreboot.org/c/coreboot/+/35870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064585e97b0a04decfcee0742f3258175d7930b9 Gerrit-Change-Number: 35870 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/icelake: Use SSDT generator to generate PCI _PRT table
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36437 ) Change subject: [WIP]soc/intel/icelake: Use SSDT generator to generate PCI _PRT table ...................................................................... [WIP]soc/intel/icelake: Use SSDT generator to generate PCI _PRT table This creates a _PRT ACPI table using the common southbridge code based on the default routes the FSP sets up. TODO: soc/irq.h can be cleaned up and adapted with this code in mind. Change-Id: I44687e9d18a8fd2c926022fdae1240339df1c978 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/Makefile.inc D src/soc/intel/icelake/acpi/pci_irqs.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/chip.c A src/soc/intel/icelake/pirq.c 6 files changed, 99 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36437/1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 4ae043a..47963db 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -50,6 +50,9 @@ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN + select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN_STATIC_PIC_MAP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 80dcdc1..5242188 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += sd.c +ramstage-y += pirq.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl deleted file mode 100644 index 79c9927..0000000 --- a/src/soc/intel/icelake/acpi/pci_irqs.asl +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017-2018 Intel Corp. - * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/irq.h> - -Name (PICP, Package () { - /* PCI Bridge */ - /* cAVS, SMBus, GbE, Nothpeak */ - Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo and SCS */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 9-16 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - /* SerialIo */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - /* Integrated Sensor Hub */ - Package(){0x0013FFFF, 0, 0, ISH_IRQ }, - /* Thermal */ - Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, - /* Host Bridge */ - /* Root Port D1F0 */ - Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, - Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, - Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, - Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, -}) - -Name (PICN, Package () { - /* D31: cAVS, SMBus, GbE, Nothpeak */ - Package () { 0x001FFFFF, 0, 0, 11 }, - Package () { 0x001FFFFF, 1, 0, 10 }, - Package () { 0x001FFFFF, 2, 0, 11 }, - Package () { 0x001FFFFF, 3, 0, 11 }, - /* D30: Can't use PIC*/ - /* D29: PCI Express Port 9-16 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - /* D26: Can't use PIC*/ - /* D25: Can't use PIC*/ - /* D23: SATA controller */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - /* D18: Can't use PIC*/ - /* P.E.G. Root Port D1F0 */ - Package () { 0x0001FFFF, 0, 0, 11 }, - Package () { 0x0001FFFF, 1, 0, 10 }, - Package () { 0x0001FFFF, 2, 0, 11 }, - Package () { 0x0001FFFF, 3, 0, 11 }, - /* SA IGFX Device */ - Package () { 0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, - /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ffd2fcc..e4e974a 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -20,9 +20,6 @@ #include <soc/itss.h> #include <soc/pcr_ids.h> -/* PCI IRQ assignment */ -#include "pci_irqs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl> diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2bb908c..438ae1c 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -27,6 +27,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) @@ -149,6 +150,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, #endif + .acpi_fill_ssdt_generator = intel_acpi_gen_def_acpi_pirq, }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/icelake/pirq.c b/src/soc/intel/icelake/pirq.c new file mode 100644 index 0000000..d81edcc --- /dev/null +++ b/src/soc/intel/icelake/pirq.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/device.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> +#include <soc/irq.h> + +/* Generate a _PRT table based on what FSP programs as default IRQ Routes. + TODO: FSP has the option to override the defaults. Provide a + way to deal with that too. */ +enum pirq intel_common_map_pirq(const struct device *dev, + const enum pci_pin pci_pin) +{ + u8 slot = PCI_SLOT(dev->path.pci.devfn); + + if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) { + printk(BIOS_ERR, + "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n", + slot, pci_pin); + return PIRQ_NONE; + } + + switch (slot) { + case 0x13: + if (pci_pin == PCI_INT_A) + return ISH_IRQ - 16 + PIRQ_A; + break; + case 0x19: + switch (pci_pin) { + case PCI_INT_A: + return LPSS_I2C4_IRQ - 16 + PIRQ_A; + case PCI_INT_B: + return LPSS_I2C5_IRQ - 16 + PIRQ_A; + case PCI_INT_C: + return LPSS_UART2_IRQ - 16 + PIRQ_A; + default: + break; + } + break; + case 0x1e: + switch (pci_pin) { + case PCI_INT_A: + return LPSS_UART0_IRQ - 16 + PIRQ_A; + case PCI_INT_B: + return LPSS_UART1_IRQ - 16 + PIRQ_A; + case PCI_INT_C: + return LPSS_SPI0_IRQ - 16 + PIRQ_A; + case PCI_INT_D: + return LPSS_SPI1_IRQ - 16 + PIRQ_A; + default: + break; + } + break; + case 0x1f: + switch (pci_pin) { + case PCI_INT_A: + return cAVS_INTA_IRQ - 16 + PIRQ_A; + case PCI_INT_B: + return SMBUS_INTB_IRQ - 16 + PIRQ_A; + case PCI_INT_C: + return GbE_INTC_IRQ - 16 + PIRQ_A; + case PCI_INT_D: + return TRACE_HUB_INTD_IRQ - 16 + PIRQ_A; + default: + break; + } + break; + } + + /* Other PCI devices map pin A -> IRQA, B -> IRQB, ... */ + return (enum pirq)pci_pin; + +} + +int intel_common_map_pic(enum pirq pirq) +{ + if (pirq == PIRQ_B) + return 10; + else + return 11; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44687e9d18a8fd2c926022fdae1240339df1c978 Gerrit-Change-Number: 36437 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019