coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 05 Nov '19

05 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 12: (1 comment) > Patch Set 12: > > > Patch Set 12: > > > > > Patch Set 12: > > > > > > > > HI Arthur/Philipp, > > > > > > > > > > Will you please consider your -2 with this new sets of split CL in place and we have icl base clean up cl also merged ? This will help us to land TGL SOC copy code ? > > > > > > > > This still has received no real review. It references many docs that I cannot find so how do you expect proper review to happen? > > > > > > I have access to the documents and would be willing to review. However, > > > I want to be fully honest: a review of copy-first patches will take weeks > > > if not months. It pushes a lot of work that should be done by the authors > > > to the reviewers and will create a bottle-neck. I estimate at least five > > > times more work for reviewers this way. Doesn't seem fair, and due to the > > > overhead of copy-first patch-later, it might even be less work for me if > > > I write the patches by myself. > > > > Again, document said to have TGL specific changes which are yet to land. this copy patches are placeholder from previous soc to help review only TGL specific changes as per logic. > > Again, again, again, it eases the review of differences, yes; but it also > increases the effort to confirm that everything else really stayed the same > by one or two orders of magnitude. Shouldn't the same we can confirm based on TGL specific CL's for an example: GPIO driver for TGL. If its an incremental change over original ICL gpio code then why should I write again a fresh code? thats the argument i have. Given that we don't have trust on SOC vendors that they know what they are doing with new soc. in terms of IP. We are just asking help to make the code land and its matter to have 8-10 CL to make entire ICL to TGL transition. And i have shared the document number so u can verify whatever coming new makes sense or not. > > So what you are really trying to ease, IMHO, is the conscience of whoever > is supposed to rubber-stamp this. trying to ease the review time of old platform and helping to have smooth review only on new SOC code given that ICL been reviewed properly (Arthur has spent significant to review almost all soc files from ICL to review achieving that) https://review.coreboot.org/c/coreboot/+/36087/12/src/soc/intel/tigerlake/s… File src/soc/intel/tigerlake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/36087/12/src/soc/intel/tigerlake/s… PS12, Line 1: /* > Is this file not copied 1 on 1 many times in the tree? Make it common? yes, this file is a candidate for common code i had started sometime now https://review.coreboot.org/c/coreboot/+/26138 -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Nov 2019 12:57:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Nico Huber (Code Review) 05 Nov '19

05 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 12: > Patch Set 12: > > > Patch Set 12: > > > > > > HI Arthur/Philipp, > > > > > > > > Will you please consider your -2 with this new sets of split CL in place and we have icl base clean up cl also merged ? This will help us to land TGL SOC copy code ? > > > > > > This still has received no real review. It references many docs that I cannot find so how do you expect proper review to happen? > > > > I have access to the documents and would be willing to review. However, > > I want to be fully honest: a review of copy-first patches will take weeks > > if not months. It pushes a lot of work that should be done by the authors > > to the reviewers and will create a bottle-neck. I estimate at least five > > times more work for reviewers this way. Doesn't seem fair, and due to the > > overhead of copy-first patch-later, it might even be less work for me if > > I write the patches by myself. > > Again, document said to have TGL specific changes which are yet to land. this copy patches are placeholder from previous soc to help review only TGL specific changes as per logic. Again, again, again, it eases the review of differences, yes; but it also increases the effort to confirm that everything else really stayed the same by one or two orders of magnitude. So what you are really trying to ease, IMHO, is the conscience of whoever is supposed to rubber-stamp this. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Nov 2019 12:50:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 05 Nov '19

05 Nov '19

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Nico Huber (Code Review) 05 Nov '19

05 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 12: > > HI Arthur/Philipp, > > > > Will you please consider your -2 with this new sets of split CL in place and we have icl base clean up cl also merged ? This will help us to land TGL SOC copy code ? > > This still has received no real review. It references many docs that I cannot find so how do you expect proper review to happen? I have access to the documents and would be willing to review. However, I want to be fully honest: a review of copy-first patches will take weeks if not months. It pushes a lot of work that should be done by the authors to the reviewers and will create a bottle-neck. I estimate at least five times more work for reviewers this way. Doesn't seem fair, and due to the overhead of copy-first patch-later, it might even be less work for me if I write the patches by myself. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Nov 2019 12:36:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver
by Michael Niewöhner (Code Review) 05 Nov '19

05 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36620 ) Change subject: drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver ...................................................................... Uploaded patch set 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/36620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I914df51a7414eb72416f816ff8375a13d5716925 Gerrit-Change-Number: 36620 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 10:43:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver
by Michael Niewöhner (Code Review) 05 Nov '19

05 Nov '19

Hello Patrick Rudolph, Vanny E, Arthur Heymans, build bot (Jenkins), Nico Huber, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36620 to look at the new patch set (#8). Change subject: drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver ...................................................................... drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver The common cbmem_top_chipset implementation uses the FSP bootloader HOB, thus move it to the fsp driver which is a more appropriate place. Change-Id: I914df51a7414eb72416f816ff8375a13d5716925 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/drivers/intel/fsp2_0/Makefile.inc R src/drivers/intel/fsp2_0/cbmem.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 1 insertion(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/36620/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/36620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I914df51a7414eb72416f816ff8375a13d5716925 Gerrit-Change-Number: 36620 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/quark: make use of common cbmem_top_chipset
by Michael Niewöhner (Code Review) 05 Nov '19

05 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36621 ) Change subject: soc/intel/quark: make use of common cbmem_top_chipset ...................................................................... Uploaded patch set 6. -- To view, visit https://review.coreboot.org/c/coreboot/+/36621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445c471b654abfa922b20215e52a2794529be120 Gerrit-Change-Number: 36621 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 10:43:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/quark: make use of common cbmem_top_chipset
by Michael Niewöhner (Code Review) 05 Nov '19

05 Nov '19

Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36621 to look at the new patch set (#6). Change subject: soc/intel/quark: make use of common cbmem_top_chipset ...................................................................... soc/intel/quark: make use of common cbmem_top_chipset This replaces quark's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: I445c471b654abfa922b20215e52a2794529be120 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/quark/Kconfig M src/soc/intel/quark/memmap.c 2 files changed, 2 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/36621/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/36621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I445c471b654abfa922b20215e52a2794529be120 Gerrit-Change-Number: 36621 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIP
by Nico Huber (Code Review) 05 Nov '19

05 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36170 ) Change subject: drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIP ...................................................................... Patch Set 5: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/36170/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36170/5//COMMIT_MSG@9 PS5, Line 9: FSP > Technically it's a property of the cpu's capability -- not FSP proper. How so? -- To view, visit https://review.coreboot.org/c/coreboot/+/36170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80 Gerrit-Change-Number: 36170 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 09:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Hide CONFIG_FSP_CAR
by Nico Huber (Code Review) 05 Nov '19

05 Nov '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36169 ) Change subject: drivers/intel/fsp2_0: Hide CONFIG_FSP_CAR ...................................................................... drivers/intel/fsp2_0: Hide CONFIG_FSP_CAR CONFIG_FSP_CAR should not be a user visible option, but depends on the choice presented in the soc Kconfig. This also removes the dependencies on ADD_FSP_BINARIES. You need to included those for other stages too so there is no need to make this requirement explicit for FSP-T. Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 765d643..b434a51 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -123,8 +123,7 @@ The path and filename of the Intel FSP-S binary for this platform. config FSP_CAR - bool "Use FSP TempRamInit & TempRamExit APIs" - depends on ADD_FSP_BINARIES + bool default n help Use FSP APIs to initialize & Tear Down the Cache-As-Ram -- To view, visit https://review.coreboot.org/c/coreboot/+/36169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a Gerrit-Change-Number: 36169 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: merged

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coreboot-gerrit November 2019