coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Arthur Heymans (Code Review) 05 Nov '19

05 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: Code-Review+1 (1 comment) > Patch Set 4: Code-Review-1 > > (1 comment) > > Is this really necessary, FSP-T is optional right? coreboot is an open source project, blobs that replace open source code have no place here. The reason for its removal is exactly that it is optional. https://review.coreboot.org/c/coreboot/+/36622/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36622/4//COMMIT_MSG@10 PS4, Line 10: working I'd even call it superior. You don't need to have a hardcoded location for microcode. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 14:41:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/pc80: Remove UDELAY_TIMER2
by Kyösti Mälkki (Code Review) 05 Nov '19

05 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36534 ) Change subject: drivers/pc80: Remove UDELAY_TIMER2 ...................................................................... drivers/pc80: Remove UDELAY_TIMER2 Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/pc/Kconfig M src/drivers/pc80/pc/i8254.c 2 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/36534/1 diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index 06e6568..6813857 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -18,9 +18,4 @@ this option, then you can say N here to speed up boot time. Otherwise say Y. -# This option is used in code but never selected. -config UDELAY_TIMER2 - bool - default n - endif diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 654f84a..5090f0c 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -32,24 +32,6 @@ outb(0x12, TIMER1_PORT); } -#if CONFIG(UDELAY_TIMER2) -static void load_timer2(unsigned int ticks) -{ - /* Set up the timer gate, turn off the speaker */ - outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); - outb(TIMER2_SEL | WORD_ACCESS | MODE0 | BINARY_COUNT, TIMER_MODE_PORT); - outb(ticks & 0xFF, TIMER2_PORT); - outb(ticks >> 8, TIMER2_PORT); -} - -void udelay(int usecs) -{ - load_timer2((usecs * TICKS_PER_MS) / 1000); - while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) - ; -} -#endif - #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ /* ------ Calibrate the TSC ------- -- To view, visit https://review.coreboot.org/c/coreboot/+/36534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a Gerrit-Change-Number: 36534 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: drivers/pc80: Remove UDELAY_IO
by Kyösti Mälkki (Code Review) 05 Nov '19

05 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36533 ) Change subject: drivers/pc80: Remove UDELAY_IO ...................................................................... drivers/pc80: Remove UDELAY_IO Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/pc/Kconfig M src/drivers/pc80/pc/Makefile.inc D src/drivers/pc80/pc/udelay_io.c 3 files changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36533/1 diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index bba45f6..06e6568 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -18,10 +18,6 @@ this option, then you can say N here to speed up boot time. Otherwise say Y. -config UDELAY_IO - bool - default n - # This option is used in code but never selected. config UDELAY_TIMER2 bool diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index bd56cd4..67c40a1 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -2,8 +2,6 @@ ramstage-y += isa-dma.c ramstage-y += i8259.c -ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c -romstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/drivers/pc80/pc/udelay_io.c b/src/drivers/pc80/pc/udelay_io.c deleted file mode 100644 index 4fe1cae..0000000 --- a/src/drivers/pc80/pc/udelay_io.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <delay.h> - -void init_timer(void) -{ -} - -void udelay(unsigned int usecs) -{ - int i; - - for (i = 0; i < usecs; i++) - inb(0x80); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464 Gerrit-Change-Number: 36533 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: intel/i440bx: Switch to UDELAY_TSC
by Kyösti Mälkki (Code Review) 05 Nov '19

05 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36525 ) Change subject: intel/i440bx: Switch to UDELAY_TSC ...................................................................... intel/i440bx: Switch to UDELAY_TSC Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/slot_1/Kconfig M src/northbridge/intel/i440bx/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36525/1 diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a..10001bd 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,8 @@ select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM - select NO_MONOTONIC_TIMER + select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 45cdd9c..df1e365 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select UDELAY_IO config SDRAMPWR_4DIMM bool -- To view, visit https://review.coreboot.org/c/coreboot/+/36525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Gerrit-Change-Number: 36525 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by David Guckian (Code Review) 05 Nov '19

05 Nov '19

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: Code-Review-1 (1 comment) Is this really necessary, FSP-T is optional right? https://review.coreboot.org/c/coreboot/+/36622/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36622/4//COMMIT_MSG@9 PS4, Line 9: FSP-T is only working in very few cases You have data to back this up? Is this the only justification for removing FSP-T from fsp2_0 driver? -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 14:36:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Nico Huber (Code Review) 05 Nov '19

05 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 12: > > > > > > HI Arthur/Philipp, > > > > > > > > > > > > Will you please consider your -2 with this new sets of split CL in place and we have icl base clean up cl also merged ? This will help us to land TGL SOC copy code ? > > > > > > > > > > This still has received no real review. It references many docs that I cannot find so how do you expect proper review to happen? > > > > > > > > I have access to the documents and would be willing to review. However, > > > > I want to be fully honest: a review of copy-first patches will take weeks > > > > if not months. It pushes a lot of work that should be done by the authors > > > > to the reviewers and will create a bottle-neck. I estimate at least five > > > > times more work for reviewers this way. Doesn't seem fair, and due to the > > > > overhead of copy-first patch-later, it might even be less work for me if > > > > I write the patches by myself. > > > > > > Again, document said to have TGL specific changes which are yet to land. this copy patches are placeholder from previous soc to help review only TGL specific changes as per logic. > > > > Again, again, again, it eases the review of differences, yes; but it also > > increases the effort to confirm that everything else really stayed the same > > by one or two orders of magnitude. > > Shouldn't the same we can confirm based on TGL specific CL's for an example: GPIO driver for TGL. If its an incremental change over original ICL gpio code then why should I write again a fresh code? thats the argument i have. I don't say you should. But I don't see how this information, that it was an incremental change, is valuable in our Git history. > Given that we don't have trust on SOC vendors that they know what they are doing with new soc. in terms of IP. We are just asking help to make the code land and its matter to have 8-10 CL to make entire ICL to TGL transition. That 8-10 sounds bad to me. Few, big commits are 10 times harder to review than many, small commits. > And i have shared the document number so u can verify whatever coming new makes sense or not. I think we should also verify that everything that we assume is unchanged in hardware really didn't change. Otherwise, we'll create hard to track bugs for the future. Let's stick to your GPIO example. In the current patch set, `gpio.c`. How is one supposed to review this file? * To see if this is the final state of the file, I'd have to look ahead on the patch branch. Time wasted. * It is not the final state, so I'd have to figure out for every line of the file if that line is in its final state. Incredibly much time wasted. * If I have to comment on one line but surrounding lines are patched later, on which change shall I comment? => messy review, more time wasted. Another example `graphics.c`. This file is flawed, but not changed later it seems. If we don't go through the pain of reviewing it as part of the messy review, the errors will stick. Now, in a year or so, somebody might run into a bug there, they might check the Git history for clues about the code: * How is one supposed to know if the code was already checked to be Tiger Lake compatible? * If somebody assumes that it was checked but it wasn't, more time gets wasted. -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Nov 2019 14:34:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/mp_init: Wait longer with serial enabled
by Patrick Rudolph (Code Review) 05 Nov '19

05 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34570 ) Change subject: cpu/x86/mp_init: Wait longer with serial enabled ...................................................................... cpu/x86/mp_init: Wait longer with serial enabled In case of slow serial wait longer for MP init to pickup jobs. This fixes a crash observed on KBL with 8core CPU as the task is stored on the BSP stack, which is reused for something else if the APs are to slow. Tested on SuperMicro X11SSH-TF. Change-Id: Id47df02a9238e66f2b628b9d6805858724bf30a9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34570/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9528149..8ff214e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -892,6 +892,19 @@ } mfence(); + if (CONFIG(CONSOLE_SERIAL)) { + /* The serial console is slow and has a spinlock. + * It can take a while for all APs to pickup the work, + * especially with modern multicore CPUs. + * + * Wait longer than requested, otherwise we will return early + * and the stack containing the AP work will be reused for + * something else, causing the APs to crash. + * + * 100msec seems to be sufficent on 8core platform. + */ + expire_us = 100 * USECS_PER_MSEC; + } /* Wait for all the APs to signal back that call has been accepted. */ if (expire_us > 0) stopwatch_init_usecs_expire(&sw, expire_us); -- To view, visit https://review.coreboot.org/c/coreboot/+/34570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id47df02a9238e66f2b628b9d6805858724bf30a9 Gerrit-Change-Number: 34570 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 26

Change in coreboot[master]: bootblock: Add TS_START_BOOTBLOCK and TS_END_BOOTBLOCK
by Kyösti Mälkki (Code Review) 05 Nov '19

05 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36594 ) Change subject: bootblock: Add TS_START_BOOTBLOCK and TS_END_BOOTBLOCK ...................................................................... bootblock: Add TS_START_BOOTBLOCK and TS_END_BOOTBLOCK Change-Id: I5617e5d9b7238ad7a894934910a3eae742d2d22d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/bootblock.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36594/1 diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 19841c6..4f5d887 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -41,6 +41,8 @@ static void bootblock_main_with_timestamp(uint64_t base_timestamp, struct timestamp_entry *timestamps, size_t num_timestamps) { + uint64_t ts_start = timestamp_get(); + /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(timestamp) > 0) { @@ -51,6 +53,8 @@ timestamps[i].entry_stamp); } + timestamp_add(TS_START_BOOTBLOCK, ts_start); + bootblock_soc_early_init(); bootblock_mainboard_early_init(); @@ -65,6 +69,8 @@ bootblock_soc_init(); bootblock_mainboard_init(); + timestamp_add_now(TS_END_BOOTBLOCK); + run_romstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5617e5d9b7238ad7a894934910a3eae742d2d22d Gerrit-Change-Number: 36594 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/ti/am335x: Extend monotonic timer to early stages
by Kyösti Mälkki (Code Review) 05 Nov '19

05 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36593 ) Change subject: cpu/ti/am335x: Extend monotonic timer to early stages ...................................................................... cpu/ti/am335x: Extend monotonic timer to early stages Change-Id: Ifb3f624930c9ef663fae30cd5ddcb1d3d46f06b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/ti/am335x/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36593/1 diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 24a79dd..404848a 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -3,9 +3,11 @@ bootblock-y += dmtimer.c bootblock-y += gpio.c bootblock-y += pinmux.c +bootblock-y += monotonic_timer.c romstage-y += nand.c romstage-y += cbmem.c +romstage-y += monotonic_timer.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb3f624930c9ef663fae30cd5ddcb1d3d46f06b1 Gerrit-Change-Number: 36593 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 05 Nov '19

05 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/36087/12/src/soc/intel/tigerlake/K… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/36087/12/src/soc/intel/tigerlake/K… PS12, Line 81: depends on FSP_USES_CB_STACK > why? https://review.coreboot.org/c/coreboot/+/36628 thx -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 Nov 2019 13:02:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019