coreboot-gerrit November 2019

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Patrick Georgi (Code Review) 05 Nov '19

05 Nov '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: > Patch Set 4: Code-Review-2 > > I think this needs to be discussed much more heavily and decided upon at the project level. Put on the agenda for tomorrow's leadership meeting: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 15:19:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Martin Roth (Code Review) 05 Nov '19

05 Nov '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: Code-Review-2 I think this needs to be discussed much more heavily and decided upon at the project level. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 15:13:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Tigerlake device IDs
by Patrick Georgi (Code Review) 05 Nov '19

05 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36225 ) Change subject: soc/intel/common: Include Tigerlake device IDs ...................................................................... soc/intel/common: Include Tigerlake device IDs Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 20 files changed, 112 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3cab86bd..4d21f5b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2767,6 +2767,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -2903,6 +2904,23 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15 0x34b6 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16 0x34b7 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1 0xa0b8 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2 0xa0b9 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3 0xa0ba +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4 0xa0bb +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5 0xa0bc +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6 0xa0bd +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7 0xa0be +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8 0xa0bf +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9 0xa0b0 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10 0xa0b1 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11 0xa0b2 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12 0xa0b3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13 0xa0b4 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14 0xa0b5 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15 0xa0b6 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16 0xa0b7 + #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1 0xa338 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2 0xa339 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3 0xa33a @@ -2972,6 +2990,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 #define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_SATA 0xa0d3 +#define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 +#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 +#define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2985,6 +3007,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 +#define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3035,6 +3058,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb #define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 #define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 +#define PCI_DEVICE_ID_INTEL_TGP_I2C0 0xa0e8 +#define PCI_DEVICE_ID_INTEL_TGP_I2C1 0xa0e9 +#define PCI_DEVICE_ID_INTEL_TGP_I2C2 0xa0ea +#define PCI_DEVICE_ID_INTEL_TGP_I2C3 0xa0eb +#define PCI_DEVICE_ID_INTEL_TGP_I2C4 0xa0c5 +#define PCI_DEVICE_ID_INTEL_TGP_I2C5 0xa0c6 +#define PCI_DEVICE_ID_INTEL_TGP_I2C6 0xa0d8 +#define PCI_DEVICE_ID_INTEL_TGP_I2C7 0xa0d9 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3066,6 +3097,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 #define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 #define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 +#define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 +#define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 +#define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3096,6 +3130,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab #define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 +#define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 +#define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa +#define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd +#define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe +#define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de +#define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3187,6 +3229,10 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3237,6 +3283,8 @@ #define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3247,6 +3295,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3260,6 +3309,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed +#define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3273,6 +3323,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 +#define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3281,6 +3332,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef +#define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3295,6 +3347,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 +#define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3310,6 +3363,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 +#define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3319,6 +3373,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee +#define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2c5061f..df571ba 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -84,6 +84,7 @@ { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_P0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, + { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 0bd5c72..5eb3761 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -754,6 +754,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_CSE0, PCI_DEVICE_ID_INTEL_ICL_CSE0, PCI_DEVICE_ID_INTEL_CMP_CSE0, + PCI_DEVICE_ID_INTEL_TGL_CSE0, 0, }; diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 277b6c5..947c002 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -34,6 +34,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, + PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 8e79eab..4efa60f 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -207,6 +207,10 @@ PCI_DEVICE_ID_INTEL_CML_GT1_H_2, PCI_DEVICE_ID_INTEL_CML_GT2_H_1, PCI_DEVICE_ID_INTEL_CML_GT2_H_2, + PCI_DEVICE_ID_INTEL_TGL_GT1, + PCI_DEVICE_ID_INTEL_TGL_GT2_UY, + PCI_DEVICE_ID_INTEL_TGL_GT2, + PCI_DEVICE_ID_INTEL_TGL_GT2_Y, 0, }; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index be8319c..4a87e1a 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -82,6 +82,7 @@ PCI_DEVICE_ID_INTEL_ICL_AUDIO, PCI_DEVICE_ID_INTEL_CMP_AUDIO, PCI_DEVICE_ID_INTEL_BSW_AUDIO, + PCI_DEVICE_ID_INTEL_TGL_AUDIO, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index fb7aea2..1749bf5 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -235,6 +235,14 @@ PCI_DEVICE_ID_INTEL_CMP_I2C3, PCI_DEVICE_ID_INTEL_CMP_I2C4, PCI_DEVICE_ID_INTEL_CMP_I2C5, + PCI_DEVICE_ID_INTEL_TGP_I2C0, + PCI_DEVICE_ID_INTEL_TGP_I2C1, + PCI_DEVICE_ID_INTEL_TGP_I2C2, + PCI_DEVICE_ID_INTEL_TGP_I2C3, + PCI_DEVICE_ID_INTEL_TGP_I2C4, + PCI_DEVICE_ID_INTEL_TGP_I2C5, + PCI_DEVICE_ID_INTEL_TGP_I2C6, + PCI_DEVICE_ID_INTEL_TGP_I2C7, 0, }; diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 5ef7641..e547538 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -51,6 +51,7 @@ #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_TIGERLAKE_A0 0x806c0 /* * MP Init callback function to Find CPU Topology. This function is common diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index eb7de08..c2b51be 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -190,6 +190,7 @@ PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, + PCI_DEVICE_ID_INTEL_TGL_ESPI, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 14e1fd9..981ad07 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -179,6 +179,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, + PCI_DEVICE_ID_INTEL_TGL_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index c8ca4f4..406a227 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -250,6 +250,22 @@ PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 2b148f2..1d2aa61 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -133,6 +133,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_PMC, PCI_DEVICE_ID_INTEL_ICP_PMC, PCI_DEVICE_ID_INTEL_CMP_PMC, + PCI_DEVICE_ID_INTEL_TGP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 0c278f3..13ac32e 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -96,6 +96,10 @@ PCI_DEVICE_ID_INTEL_CMP_SATA, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_SATA, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 77b05c1..56f54d7 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -95,6 +95,7 @@ PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, + PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 365da2f..3c77cc4 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -81,6 +81,14 @@ PCI_DEVICE_ID_INTEL_CMP_SPI1, PCI_DEVICE_ID_INTEL_CMP_SPI2, PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_TGP_SPI0, + PCI_DEVICE_ID_INTEL_TGP_GSPI0, + PCI_DEVICE_ID_INTEL_TGP_GSPI1, + PCI_DEVICE_ID_INTEL_TGP_GSPI2, + PCI_DEVICE_ID_INTEL_TGP_GSPI3, + PCI_DEVICE_ID_INTEL_TGP_GSPI4, + PCI_DEVICE_ID_INTEL_TGP_GSPI5, + PCI_DEVICE_ID_INTEL_TGP_GSPI6, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 720b736..47ba28f 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -51,6 +51,7 @@ PCI_DEVICE_ID_INTEL_GLK_SRAM, PCI_DEVICE_ID_INTEL_ICL_SRAM, PCI_DEVICE_ID_INTEL_CMP_SRAM, + PCI_DEVICE_ID_INTEL_TGL_SRAM, 0, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e03942f..7ad565d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -362,6 +362,8 @@ PCI_DEVICE_ID_INTEL_CML_S_10_2, PCI_DEVICE_ID_INTEL_CML_H, PCI_DEVICE_ID_INTEL_CML_H_8_2, + PCI_DEVICE_ID_INTEL_TGL_ID_U, + PCI_DEVICE_ID_INTEL_TGL_ID_Y, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 364835d..718eaca 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -275,6 +275,9 @@ PCI_DEVICE_ID_INTEL_CMP_UART0, PCI_DEVICE_ID_INTEL_CMP_UART1, PCI_DEVICE_ID_INTEL_CMP_UART2, + PCI_DEVICE_ID_INTEL_TGP_UART0, + PCI_DEVICE_ID_INTEL_TGP_UART1, + PCI_DEVICE_ID_INTEL_TGP_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index d42a1ec..92f3b15 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -43,6 +43,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_XDCI, PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, PCI_DEVICE_ID_INTEL_CMP_LP_XDCI, + PCI_DEVICE_ID_INTEL_TGP_LP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 293fd36..5930e23 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ PCI_DEVICE_ID_INTEL_CNP_H_XHCI, PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, + PCI_DEVICE_ID_INTEL_TGP_LP_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/36225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19047354718bdf510dffee4659d885f1313a751b Gerrit-Change-Number: 36225 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Nico Huber (Code Review) 05 Nov '19

05 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/36622/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36622/4//COMMIT_MSG@9 PS4, Line 9: FSP-T is only working in very few cases > You have data to back this up? […] I think the big problem here is the way it is integrated. Both on coreboot and FSP sides. People often give up before they have figured out the correct Kconfig settings to make it work. Does that count as a case where it is (not) working? So if Intel wants to maintain this feature as an upstream option, it would be much appreciated if the FSP binaries could be fixed or the integration guides updates (one thing that comes to mind is that the integration guides say you *are* allowed to pass a NULL-pointer for microcode updates, but if you do, FSP often crashes). It's pretty ridiculous, as most of the CPUs (or maybe all?) already apply the update via FIT. Also, with the complex rules of updating, especially in cases like SGX enablement, it's even harder to track if everything goes according to plan when FSP does updates too. So please fix all the binaries, nobody needs microcode updates performed by error-prone FSP! If really necessary, because Intel can't fix their own programs, we could also fix the microcode-update pointer on the coreboot side, see how it is done for FIT, for instance. No need for a Kconfig mess! That this pops up every few months is a clear sign that Intel doesn't take the integration serious. So why should the coreboot community? -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 15:04:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Guckian Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vendorcode/eltan/security: align mboot with coreboot tpm
by Wim Vervoorn (Code Review) 05 Nov '19

05 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36483 ) Change subject: vendorcode/eltan/security: align mboot with coreboot tpm ...................................................................... vendorcode/eltan/security: align mboot with coreboot tpm Align the eltan mboot support with coreboot tpm support to limit the amount of custom code. We now only support SHA256 pcrs, only single a single digest handled in a call. The pcr invalidation has been changed. BUG=N/A TEST=tested on fbg1701 Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/romstage.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/mboot/mboot.h M src/vendorcode/eltan/security/mboot/mboot_func.c 4 files changed, 47 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/36483/1 diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index c10e866..b6ea03f 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -78,7 +78,7 @@ CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD; -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int mb_crtm(void) { int status = TPM_E_IOERROR; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -91,9 +91,9 @@ tcgEventHdr.eventSize = sizeof(crtm_version); printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, &tcgEventHdr, - (uint8_t *)crtm_version, 0); + (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); } diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index bae377a..3799b8a 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -120,92 +120,37 @@ * Calculates the hash over the data and extends it in active PCR banks and * then logs them in the event log. * - * @param[in] activePcr bitmap of active PCR banks in TPM. - * @param[in] flags flags associated with hash data. Currently - * unused. + * @param[in] flags flags associated with hash data. Currently unused. * @param[in] hashData data to be hashed. * @param[in] hashDataLen length of the data to be hashed. * @param[in] newEventHdr event header in TCG_PCR_EVENT2 format. * @param[in] eventLog description of the event. - * @param[in] invalid invalidate the pcr * * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. */ -int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, - TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid) +int mboot_hash_extend_log(uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog) { - int status; TPMT_HA *digest = NULL; - int digest_num = 0; - printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, - (size_t)hashDataLen); + printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, (size_t)hashDataLen); - if (invalid) { - digest = &(newEventHdr->digest.digests[digest_num]); - digest->hashAlg = TPM_ALG_ERROR; - digest_num++; + /* Generate SHA256 */ + digest = &(newEventHdr->digest.digests[0]); + if (flags & MBOOT_HASH_PROVIDED) { + /* The hash is provided as data */ + memcpy(digest->digest.sha256, (void *)hashData, hashDataLen); } else { - /* - * Generate SHA1 hash if SHA1 PCR bank is active in TPM - * currently - */ - if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA1) { - digest = &(newEventHdr->digest.digests[digest_num]); - if (flags & MBOOT_HASH_PROVIDED) { - /* The hash is provided as data */ - memcpy(digest->digest.sha1, (void *)hashData, - VB2_SHA1_DIGEST_SIZE); - } else { - if (cb_sha_little_endian(VB2_HASH_SHA1, hashData, - hashDataLen, digest->digest.sha1)) - return TPM_E_IOERROR; - } - - digest->hashAlg = TPM_ALG_SHA1; - digest_num++; - - printk(BIOS_DEBUG, "%s: SHA1 Hash Digest:\n", __func__); - mboot_print_buffer(digest->digest.sha1, - VB2_SHA1_DIGEST_SIZE); - } - - /* - * Generate SHA256 hash if SHA256 PCR bank is active in TPM - * currently - */ - if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA256) { - digest = &(newEventHdr->digest.digests[digest_num]); - if (flags & MBOOT_HASH_PROVIDED) { - /* The hash is provided as data */ - memcpy(digest->digest.sha256, - (void *)hashData, hashDataLen); - } else { - - if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, - hashDataLen, digest->digest.sha256)) - return TPM_E_IOERROR; - } - digest->hashAlg = TPM_ALG_SHA256; - digest_num++; - - printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", - __func__); - mboot_print_buffer(digest->digest.sha256, - VB2_SHA256_DIGEST_SIZE); - } + if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, hashDataLen, + digest->digest.sha256)) + return TPM_E_IOERROR; } - newEventHdr->digest.count = digest_num; + printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", __func__); + mboot_print_buffer(digest->digest.sha256, VB2_SHA256_DIGEST_SIZE); - status = tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), - NULL); - if (status != TPM_SUCCESS) - printk(BIOS_DEBUG, "%s: returned 0x%x\n", __func__, status); - - return status; + return (tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), NULL)); } /* @@ -215,13 +160,11 @@ */ void invalidate_pcrs(void) { - int status, pcr; - TCG_PCR_EVENT2_HDR tcgEventHdr; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; - uint8_t invalidate; + int pcr; + int status; - ActivePcrs = tpm2_get_active_pcrs(); - invalidate = 1; + TCG_PCR_EVENT2_HDR tcgEventHdr; + uint8_t invalidate = 1; for (pcr = 0; pcr < 8; pcr++) { printk(BIOS_DEBUG, "%s: Invalidating PCR %d\n", __func__, pcr); @@ -230,10 +173,9 @@ tcgEventHdr.eventType = EV_NO_ACTION; tcgEventHdr.eventSize = (uint32_t) sizeof(invalidate); - status = mboot_hash_extend_log(ActivePcrs, 0, - (uint8_t *)&invalidate, tcgEventHdr.eventSize, - &tcgEventHdr, (uint8_t *)"Invalidate PCR", invalidate); - + status = mboot_hash_extend_log(0, (uint8_t *)&invalidate, + tcgEventHdr.eventSize, &tcgEventHdr, + (uint8_t *)"Invalidate PCR"); if (status != TPM_SUCCESS) printk(BIOS_DEBUG, "%s: invalidating pcr %d returned" " 0x%x\n", __func__, pcr, status); @@ -288,7 +230,6 @@ /* * measures and logs the specified cbfs file. * - * @param[in] activePcr bitmap of active PCR banks in TPM. * @param[in] name name of the cbfs file to measure * @param[in] type data type of the cbfs file. * @param[in] pcr pcr to extend. @@ -298,9 +239,8 @@ * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. */ -int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - const char *name, uint32_t type, uint32_t pcr, - TCG_EVENTTYPE eventType, const char *event_msg) +int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg) { int status; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -311,21 +251,18 @@ base = cbfs_boot_map_with_leak(name, type, &size); if (base == NULL) { - printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, - name); + printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, name); return VB2_ERROR_READ_FILE_OPEN; } - printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", - __func__, name); + printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", __func__, name); memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); tcgEventHdr.pcrIndex = pcr; tcgEventHdr.eventType = eventType; if (event_msg) tcgEventHdr.eventSize = (uint32_t) strlen(event_msg); - status = mboot_hash_extend_log(activePcr, 0, base, size, &tcgEventHdr, - (uint8_t *)event_msg, 0); + status = mboot_hash_extend_log(0, base, size, &tcgEventHdr, (uint8_t *)event_msg); return status; } @@ -440,18 +377,15 @@ int __attribute__((weak))mb_measure_log_start(void) { int status; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; uint32_t i; - ActivePcrs = tpm2_get_active_pcrs(); - - if (ActivePcrs == 0x0) { - printk(BIOS_DEBUG, "%s: No Active PCR Bank in TPM.\n", + if ((tpm2_get_active_pcrs() & EFI_TCG2_BOOT_HASH_ALG_SHA256) == 0x0) { + printk(BIOS_DEBUG, "%s: SHA256 PCR Bank not active in TPM.\n", __func__); return TPM_E_IOERROR; } - status = mb_crtm(ActivePcrs); + status = mb_crtm(); if (status != TPM_SUCCESS) { printk(BIOS_DEBUG, "%s: Fail! CRTM Version can't be measured." " ABORTING!!!\n", __func__); @@ -462,7 +396,7 @@ /* Log the items defined by the mainboard */ for (i = 0; i < ARRAY_SIZE(mb_log_list); i++) { status = mb_measure_log_worker( - ActivePcrs, mb_log_list[i].cbfs_name, + mb_log_list[i].cbfs_name, mb_log_list[i].cbfs_type, mb_log_list[i].pcr, mb_log_list[i].eventType, mb_log_list[i].event_msg); @@ -494,12 +428,10 @@ * The function can be overridden at the mainboard level my simply creating a * function with the same name there. * - * @param[in] activePcr bitmap of the support - * * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. **/ -int __attribute__((weak))mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int __attribute__((weak))mb_crtm(void) { int status; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -515,9 +447,8 @@ printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, - tcgEventHdr.eventSize, &tcgEventHdr, (uint8_t *)crtm_version, - 0); + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, + &tcgEventHdr, (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); @@ -540,8 +471,8 @@ msgPtr = NULL; tcgEventHdr.eventSize = 0; - status = mboot_hash_extend_log(activePcr, MBOOT_HASH_PROVIDED, hash, - sizeof(hash), &tcgEventHdr, msgPtr, 0); + status = mboot_hash_extend_log(MBOOT_HASH_PROVIDED, hash, sizeof(hash), &tcgEventHdr, + msgPtr); if (status) printk(BIOS_DEBUG, "Add ME hash returned 0x%x\n", status); diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 96375ab..43aca66 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -89,16 +89,14 @@ */ #define MBOOT_HASH_PROVIDED (0x00000001) - int is_zero_buffer(void *buffer, unsigned int size); -int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, - TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid); +int mboot_hash_extend_log( uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog); void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize); -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr); +int mb_crtm(void); typedef struct { const char *cbfs_name; @@ -108,9 +106,8 @@ const char *event_msg; } mboot_measure_item_t; -int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - const char *name, uint32_t type, uint32_t pcr, - TCG_EVENTTYPE eventType, const char *event_msg); +int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg); int mb_measure_log_start(void); void invalidate_pcrs(void); @@ -122,7 +119,7 @@ int mb_measure(int wake_from_s3); int mb_entry(int wake_from_s3); -int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs); +int log_efi_specid_event(void); int log_event_tcg_20_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); int log_event_tcg_12_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); diff --git a/src/vendorcode/eltan/security/mboot/mboot_func.c b/src/vendorcode/eltan/security/mboot/mboot_func.c index ec66d34..6792204 100644 --- a/src/vendorcode/eltan/security/mboot/mboot_func.c +++ b/src/vendorcode/eltan/security/mboot/mboot_func.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,7 @@ #include <mboot.h> -int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs) { +int log_efi_specid_event(void) { return TPM_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Gerrit-Change-Number: 36483 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: commonlib: Use __builtin_offsetof with supported compilers
by Alex James (Code Review) 05 Nov '19

05 Nov '19

Alex James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36249 ) Change subject: commonlib: Use __builtin_offsetof with supported compilers ...................................................................... commonlib: Use __builtin_offsetof with supported compilers Use __builtin_offsetof (which is treated as a constant expression) with Clang & GCC. This also allows check_member to work with Clang. Signed-off-by: Alex James <theracermaster(a)gmail.com> Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e --- M src/commonlib/include/commonlib/helpers.h 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/36249/1 diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index 4429ea4..b5e08b4 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -107,17 +107,15 @@ #define MHz (1000 * KHz) #define GHz (1000 * MHz) -#ifndef offsetof +#ifdef __ROMCC__ #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#else +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#if !defined(__clang__) #define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ "`struct " #structure "` offset for `" #member "` is not " #offset) -#else -#define check_member(structure, member, offset) -#endif /** * container_of - cast a member of a structure out to the containing structure -- To view, visit https://review.coreboot.org/c/coreboot/+/36249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e Gerrit-Change-Number: 36249 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is un...
by Arthur Heymans (Code Review) 05 Nov '19

05 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35883 ) Change subject: pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefined ...................................................................... pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefined if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if CONFIG_MMCONF_BASE_ADDRESS is not defined. Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/device/pci_mmio_cfg.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35883/1 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 5567ed8..e3c5fe4 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -90,6 +90,10 @@ #if CONFIG(MMCONF_SUPPORT) +#if CONFIG_MMCONF_BASE_ADDRESS == 0 +#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" +#endif + /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or * MMIO variant. -- To view, visit https://review.coreboot.org/c/coreboot/+/35883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Gerrit-Change-Number: 35883 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/Kconfig: Drop unused DEBUG_ACPI
by HAOUAS Elyes (Code Review) 05 Nov '19

05 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36498 ) Change subject: src/Kconfig: Drop unused DEBUG_ACPI ...................................................................... src/Kconfig: Drop unused DEBUG_ACPI Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36498/1 diff --git a/src/Kconfig b/src/Kconfig index 2b41ff2..defe4e4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -828,17 +828,6 @@ # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. -config DEBUG_ACPI - prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 - bool - default n - help - This option enables additional ACPI related debug messages. - - Note: This option will slightly increase the size of the coreboot image. - - If unsure, say N. - config DEBUG_CONSOLE_INIT bool "Debug console initialisation code" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb Gerrit-Change-Number: 36498 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: security/vboot: Build vboot library with same .a that depthcharge uses
by Joel Kitching (Code Review) 05 Nov '19

05 Nov '19

Joel Kitching has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36341 ) Change subject: security/vboot: Build vboot library with same .a that depthcharge uses ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/c/coreboot/+/36341/14/src/security/vboot/Makefi… File src/security/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/36341/14/src/security/vboot/Makefi… PS14, Line 113: VB_ > You bet Seems like the latest patchset is still VB -- are you still going to change this? -- To view, visit https://review.coreboot.org/c/coreboot/+/36341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I905b781c3596965ec7ef45a2a7eafe15fdd4d9cc Gerrit-Change-Number: 36341 Gerrit-PatchSet: 17 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 05 Nov 2019 14:51:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Disable i8042 support
by Patrick Rudolph (Code Review) 05 Nov '19

05 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36078 ) Change subject: mb/supermicro/x11-lga1151-series: Disable i8042 support ...................................................................... mb/supermicro/x11-lga1151-series: Disable i8042 support Even though the vendor firmware enables the i8042 I/O port, it doesn't feed valid data to those, but instead uses USB HID devices. Disable the KBC port in SuperI/O and report no KCS port using FADT. Fixes: * Fixes error message in Linux that i8042 keyboard couldn't be enabled. Tested on Supermicro X11SSH-TF: The virtual remote managment console still works. Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb 2 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36078/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 541b23d..069e65a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -12,6 +12,7 @@ select SUPERIO_ASPEED_AST2400 select GENERATE_SMBIOS_TABLES select IPMI_KCS + select NO_FADT_8042 if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 09aa8b5..d08cc36 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -78,12 +78,7 @@ io 0x66 = 0xa30 irq 0x70 = 0xb end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 0xc - end + device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO device pnp 2e.b on # SUART3 io 0x60 = 0x3e8 -- To view, visit https://review.coreboot.org/c/coreboot/+/36078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d Gerrit-Change-Number: 36078 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019