coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7180: Add UART support
by Roja Rani Yarubandi (Code Review) 07 Nov '19

07 Nov '19

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/35500/11/src/soc/qualcomm/sc7180/u… File src/soc/qualcomm/sc7180/uart.c: https://review.coreboot.org/c/coreboot/+/35500/11/src/soc/qualcomm/sc7180/u… PS11, Line 78: XBL > Would be nice if we could update that for clarity Sure, I will update in next patch -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 13 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 07 Nov 2019 10:36:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Copy acpi directory from icelake
by Subrata Banik (Code Review) 07 Nov '19

07 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36553 ) Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ...................................................................... Patch Set 4: (5 comments) https://review.coreboot.org/c/coreboot/+/36553/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36553/4//COMMIT_MSG@12 PS4, Line 12: . > Sure i will https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 226: : Name (EP_B, 0) /* to store EP BAR */ : Name (MH_B, 0) /* to store MCH BAR */ : Name (PC_B, 0) /* to store PCIe BAR */ : Name (PC_L, 0) /* to store PCIe BAR Length */ : Name (DM_B, 0) /* to store DMI BAR > > to avoid multiple read if any ? […] let me take that AR to fix this soon from tgl https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 236: If (LEqual (MH_B, 0)) { : ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) : } > use new syntax. Same applies to all files in this CL btw. yes, planning to clean from TGL onwards https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 323: Store (\_SB.PCI0.GMHB (), MBR0) > Are those functions necessary? Just do 'MBR0 = \_SB.PCI0.MCHC. […] will do with TGL changes https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/scs.asl: https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 26: ^PCRA > use absolute references? will do with TGL onwards -- To view, visit https://review.coreboot.org/c/coreboot/+/36553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Gerrit-Change-Number: 36553 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Nov 2019 10:08:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by build bot (Jenkins) (Code Review) 07 Nov '19

07 Nov '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/36087/16/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/ramstage.h: https://review.coreboot.org/c/coreboot/+/36087/16/src/soc/intel/tigerlake/i… PS16, Line 24: void mainboard_silicon_init_params(FSP_S_CONFIG *params); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Nov 2019 10:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 07 Nov '19

07 Nov '19

Subrata Banik has uploaded a new patch set (#16) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... soc/intel/tigerlake: Do initial SoC commit till ramstage Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/tigerlake/Kconfig A src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/acpi.c A src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/chip.h A src/soc/intel/tigerlake/cpu.c A src/soc/intel/tigerlake/elog.c A src/soc/intel/tigerlake/espi.c A src/soc/intel/tigerlake/finalize.c A src/soc/intel/tigerlake/fsp_params.c A src/soc/intel/tigerlake/gpio.c A src/soc/intel/tigerlake/graphics.c A src/soc/intel/tigerlake/gspi.c A src/soc/intel/tigerlake/i2c.c A src/soc/intel/tigerlake/include/soc/cpu.h A src/soc/intel/tigerlake/include/soc/gpe.h A src/soc/intel/tigerlake/include/soc/gpio.h A src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/irq.h A src/soc/intel/tigerlake/include/soc/itss.h A src/soc/intel/tigerlake/include/soc/msr.h A src/soc/intel/tigerlake/include/soc/nvs.h A src/soc/intel/tigerlake/include/soc/pmc.h A src/soc/intel/tigerlake/include/soc/ramstage.h A src/soc/intel/tigerlake/include/soc/serialio.h A src/soc/intel/tigerlake/include/soc/smm.h A src/soc/intel/tigerlake/include/soc/usb.h A src/soc/intel/tigerlake/lockdown.c A src/soc/intel/tigerlake/p2sb.c A src/soc/intel/tigerlake/pmc.c A src/soc/intel/tigerlake/pmutil.c A src/soc/intel/tigerlake/reset.c A src/soc/intel/tigerlake/sd.c A src/soc/intel/tigerlake/smihandler.c A src/soc/intel/tigerlake/smmrelocate.c A src/soc/intel/tigerlake/spi.c A src/soc/intel/tigerlake/systemagent.c A src/soc/intel/tigerlake/uart.c 39 files changed, 4,761 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36087/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Subrata Banik (Code Review) 07 Nov '19

07 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 15: (53 comments) https://review.coreboot.org/c/coreboot/+/36087/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36087/8//COMMIT_MSG@9 PS8, Line 9: Clone entirely from Icelake > > […] Done https://review.coreboot.org/c/coreboot/+/36087/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36087/15//COMMIT_MSG@22 PS15, Line 22: > Yes Furquan, this list is valid but its till yesterday, so what i will do after ICL https://review. […] Done https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K… File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K… PS10, Line 73: FSP_USES_CB_STACK > Done Done https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/K… PS10, Line 215: ENABLE_DISPLAY_OVER_EXT_PCIE_GFX > oh yes, this has added to enable dGPU over PCIE usecase on icelake RVP which might be applicable for […] Done https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M… File src/soc/intel/tigerlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/M… PS10, Line 1: feq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) > > one question. is that all means all stages like […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 21: #include <ec/google/chromeec/ec.h> > This should not be here. Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 32: #include <vendorcode/google/chromeos/gnvs.h> > Can you work on making GNVS common and move this out of here? needed for google_ec_running_ro https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 188: } > missing newline Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 203: gnvs->pcnt = dev_count_cpu(); > useless code, there's no user of PCNT will analysis with kernel team https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 207: gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); > useless code, there's no user of CBMC. isn't it used by chromeos ? https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 209: if (CONFIG(CHROMEOS)) { : /* Initialize Verified Boot data */ : chromeos_init_chromeos_acpi(&(gnvs->chromeos)); : if (CONFIG(EC_GOOGLE_CHROMEEC)) { : gnvs->chromeos.vbt2 = google_ec_running_ro() ? : ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; : } else : gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; : } > This does not belong here. will evaluate with TGL code ? https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 226: gnvs->u2we = config->usb2_wake_enable_bitmap; > seems only be used on skylake will check with kernel team ? https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/cnvi.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 1: /* > this file doesn't exist inside icl soc directory. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 25: > Please use tabs. Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 53: : #if 0 : Method(_PRW, 0) : { : : } : #endif > ? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/espi.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 23: Device (FWH) : { : Name (_HID, EISAID ("INT0800")) : Name (_DDN, "Firmware Hub") : Name (_CRS, ResourceTemplate () : { : Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) : }) : } > Should this always be created? It might be a good idea to look at the boot straps before doing so? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 81: IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO : IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO : IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status : IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved : IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved : IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved : IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post : IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved : IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI : IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, : 0x1, 0xff) > Should this not depend on what is actually programmed in registers? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 95: Device (RTC) : { : Name (_HID, EISAID ("PNP0B00")) : Name (_DDN, "Real Time Clock") : Name (_CRS, ResourceTemplate () : { : IO (Decode16, 0x70, 0x70, 1, 8) : }) : } : : Device (TIMR) : { : Name (_HID, EISAID ("PNP0100")) : Name (_DDN, "8254 Timer") : Name (_CRS, ResourceTemplate () : { : IO (Decode16, 0x40, 0x40, 0x01, 0x04) : IO (Decode16, 0x50, 0x50, 0x10, 0x04) : IRQNoFlags () {0} : }) : } > CL to move into common […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/globalnvs.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 30: GNVS > https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 59: /* Set flag to enable USB charging in S3 */ : Method (S3UE) : { : Store (One, \S3U0) : } : : /* Set flag to disable USB charging in S3 */ : Method (S3UD) : { : Store (Zero, \S3U0) : } : : /* Set flag to enable USB charging in S5 */ : Method (S5UE) : { : Store (One, \S5U0) : } : : /* Set flag to disable USB charging in S5 */ : Method (S5UD) : { : Store (Zero, \S5U0) : } > not required, already deleted in ICL Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 42: Store (^^PCRB (PID_GPIOCOM0), BAS0) : Store (GPIO_BASE_SIZE, LEN0) > reasonable to do this but should we target any particular soc for moving towards ASL 2. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/pci_irqs.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 100: 11 > > > didn't get ur thought ? […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 22: : OperationRegion (APMP, SystemIO, 0xb2, 2) : Field (APMP, ByteAcc, NoLock, Preserve) : { : APMC, 8, // APM command : APMS, 8 // APM status : } > https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/sleepstates.asl: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ac… PS8, Line 17: : Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) : Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) : Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) > This has been the same for all Intel targets since a long time. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/bo… File src/soc/intel/tigerlake/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/bo… PS8, Line 30: : bootblock_systemagent_early_init(); : bootblock_pch_early_init(); : bootblock_cpu_init(); : pch_early_iorange_init(); : if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) : uart_bootblock_init(); > some work started in the same like we called that common code 2. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/bo… File src/soc/intel/tigerlake/bootblock/cpu.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/bo… PS8, Line 24: BOOT_DEVICE_SPI_FLASH > https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/bo… File src/soc/intel/tigerlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/bo… PS8, Line 61: static uint8_t get_dev_revision(pci_devfn_t dev) > CL: https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ch… File src/soc/intel/tigerlake/chip.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ch… PS8, Line 72: switch (dev->path.pci.devfn) { > which datasheet(s) was/were consultated to create this array? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cp… File src/soc/intel/tigerlake/cpu.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cp… PS8, Line 72: msr = rdmsr(IA32_MISC_ENABLE); > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cp… PS8, Line 130: /* Set PM1 timer IO port and enable*/ > Done https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cp… PS8, Line 239: smm_lock(); > why is it done here? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fi… File src/soc/intel/tigerlake/finalize.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fi… PS8, Line 45: pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); > why is it done in finalize? after FSP-S programming is done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fi… PS8, Line 51: if (config->pch_isclk) > what is handled here? this depends on CAMERA controller https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fi… PS8, Line 73: * point and hence removed from the root bus. pcidev_path_on_root thus > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fi… PS8, Line 85: if (config->s0ix_enable) { > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… File src/soc/intel/tigerlake/finalize.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… PS10, Line 118: : BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); > this is good feedback to handle this in . […] will address this later in TGL changes ? https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/f… PS10, Line 42: __weak > > let me start this non weak practice from TGL so we do force ppl to get used to it. SG? […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gr… File src/soc/intel/tigerlake/graphics.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gr… PS8, Line 73: * GFX PEIM module inside FSP binary is taking care of graphics > isn;t below code does the same check ? […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gr… PS8, Line 78: * In case of non-FSP solution, SoC need to select VGA_ROM_RUN > well. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gs… File src/soc/intel/tigerlake/gspi.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gs… PS8, Line 24: return PCH_DEVFN_GSPI0; > which datasheet(s) was/were consultated to create this array? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/i2… File src/soc/intel/tigerlake/i2c.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/i2… PS8, Line 23: case PCH_DEVFN_I2C0: > which datasheet(s) was/were consultated to create this array? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/gpe.h: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/in… PS8, Line 20: #define GPE0_DW0_00 0 > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/i… PS10, Line 19: #include <soc/gpio_defs.h> : #include <intelblocks/gpio.h> : : #define CROS_GPIO_DEVICE_NAME "INT3455:00" > i believe this file is kind of wrapper for other mainboard and common code files to get gpio related […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/in… PS8, Line 47: #define GPP_G0_IRQ 0x18 > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/usb.h: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/in… PS8, Line 22: /* Per Port HS Transmitter Emphasis */ > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/p2… File src/soc/intel/tigerlake/p2sb.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/p2… PS8, Line 29: * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband > which datasheet(s) was/were consultated to create this? Done https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/r… File src/soc/intel/tigerlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/36087/10/src/soc/intel/tigerlake/r… PS10, Line 26: __weak > true. […] Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sm… File src/soc/intel/tigerlake/smihandler.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sm… PS8, Line 82: pch_disable_heci(); > which datasheet(s) was/were consultated? Why it it done in SMM? due to postboot SAI implementation since CNP PCH https://review.coreboot.org/c/coreboot/+/36087/12/src/soc/intel/tigerlake/s… File src/soc/intel/tigerlake/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/36087/12/src/soc/intel/tigerlake/s… PS12, Line 191: tseg_base > @Arthur, need your view here ? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sp… File src/soc/intel/tigerlake/spi.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sp… PS8, Line 23: case PCH_DEVFN_SPI: > which datasheet(s) was/were consultated to create this array? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sy… File src/soc/intel/tigerlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sy… PS8, Line 31: { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, > which datasheet(s) was/were consultated to create this array? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ua… File src/soc/intel/tigerlake/uart.c: https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ua… PS8, Line 31: PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ > which datasheet(s) was/were consultated to create this array? Done https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/ua… PS8, Line 61: return pcidev_path_on_root(PCH_DEVFN_UART0); > which datasheet(s) was/were consultated to create this array? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 15 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Nov 2019 10:01:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/em64t_save_state: Fix smbase/smm_revision
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36658 ) Change subject: cpu/intel/em64t_save_state: Fix smbase/smm_revision ...................................................................... cpu/intel/em64t_save_state: Fix smbase/smm_revision Fix the offsets of smbase and smm_revision in the em64t_smm_state_save_area_t struct. This follows the Intle 64 and IA-32 manual and is tested to be the correct offset on a Intel core2 CPU. Change-Id: I4055d61f8920967cede6e219f2658c54631c5dd1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/intel/em64t_save_state.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/36658/1 diff --git a/src/include/cpu/intel/em64t_save_state.h b/src/include/cpu/intel/em64t_save_state.h index 1dd01a6..4e1f7a8 100644 --- a/src/include/cpu/intel/em64t_save_state.h +++ b/src/include/cpu/intel/em64t_save_state.h @@ -47,8 +47,8 @@ u8 reserved4[84]; - u32 smm_revision; u32 smbase; + u32 smm_revision; u16 io_restart; u16 autohalt_restart; -- To view, visit https://review.coreboot.org/c/coreboot/+/36658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4055d61f8920967cede6e219f2658c54631c5dd1 Gerrit-Change-Number: 36658 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: cpu/intel/car/p3: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30776 ) Change subject: cpu/intel/car/p3: Update microcode in CAR setup ...................................................................... Abandoned It is observed to work fine until CPU init in ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/30776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Gerrit-Change-Number: 30776 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775 Change subject: cpu/intel/car/core2: Update microcode in CAR setup ...................................................................... cpu/intel/car/core2: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S 1 file changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..4fb8c66 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -111,6 +111,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -131,15 +142,17 @@ invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif +cache_xip: post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to set final MTRRs for speeding up XIP. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -165,8 +178,16 @@ /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Gerrit-Change-Number: 30775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/car/p3: Update microcode in CAR setup
by Kyösti Mälkki (Code Review) 07 Nov '19

07 Nov '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30776 ) Change subject: cpu/intel/car/p3: Update microcode in CAR setup ...................................................................... Patch Set 4: abandon as unnecessary? -- To view, visit https://review.coreboot.org/c/coreboot/+/30776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f31f7f30d6ce970d3616c12dbb264b2cf070ed9 Gerrit-Change-Number: 30776 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 07 Nov 2019 07:09:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: hatch: Create puff variant
by Edward O'Callaghan (Code Review) 06 Nov '19

06 Nov '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36452 ) Change subject: hatch: Create puff variant ...................................................................... hatch: Create puff variant Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. BUG=b:141658115 TEST=util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 270 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36452/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e339693..8488762 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -93,6 +93,7 @@ default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Puff" if BOARD_GOOGLE_PUFF config MAINBOARD_VENDOR string @@ -118,6 +119,7 @@ default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "puff" if BOARD_GOOGLE_PUFF config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 160194b..2051e0f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -32,3 +32,9 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c new file mode 100644 index 0000000..baefcf2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* E23 : TP1 */ + PAD_NC(GPP_E23, NONE), + /* H17 : TP2 */ + PAD_NC(GPP_H17, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb new file mode 100644 index 0000000..d82030d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "name" = ""PS175"" + register "desc" = ""PCON PS175"" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" + register "has_power_resource" = "1" + device i2c 15 on end # ????? + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/generic + register "name" = ""RTD21"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end # ????? + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Gerrit-Change-Number: 36452 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019