coreboot-gerrit November 2019

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by Furquan Shaikh (Code Review) 08 Nov '19

08 Nov '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 16 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 08 Nov 2019 07:58:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] ELOG build errors
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36649 ) Change subject: [WIP] ELOG build errors ...................................................................... [WIP] ELOG build errors Change-Id: Idf7b04edc3fce147f7857691ce7d6a0ce03f43fe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/stout/ec.c 2 files changed, 8 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/36649/1 diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 92d361d..bc8dd98 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,9 +29,7 @@ static u8 mainboard_smi_ec(void) { u8 src; -#if CONFIG(ELOG_GSMI) static int battery_critical_logged; -#endif ec_kbc_write_cmd(0x56); src = ec_kbc_read_ob(); @@ -39,20 +37,15 @@ switch (src) { case EC_BATTERY_CRITICAL: -#if CONFIG(ELOG_GSMI) if (!battery_critical_logged) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_HOST_EVENT_BATTERY_CRITICAL); + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, + EC_HOST_EVENT_BATTERY_CRITICAL); battery_critical_logged = 1; -#endif break; case EC_LID_CLOSE: printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - -#if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_LID_CLOSED); -#endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); break; @@ -70,11 +63,8 @@ } else if (gpi_sts & (1 << EC_LID_GPI)) { printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - -#if CONFIG(ELOG_GSMI) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, + elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_LID_CLOSED); -#endif /* Go to S5 */ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 3569cae..95bc1ca 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -69,10 +69,8 @@ if (ec_reg & 0x8) { printk(BIOS_ERR, " EC Fan Error\n"); critical_shutdown = 1; -#if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, + elog_gsmi_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, EC_HOST_EVENT_THROTTLE_START); -#endif } @@ -80,10 +78,8 @@ if (ec_reg & 0x80) { printk(BIOS_ERR, " EC Thermal Device Error\n"); critical_shutdown = 1; -#if CONFIG(ELOG_GSMI) - elog_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, + elog_gsmi_add_event_word(EC_HOST_EVENT_BATTERY_CRITICAL, EC_HOST_EVENT_THERMAL); -#endif } @@ -93,17 +89,13 @@ if ((ec_reg & 0xCF) == 0xC0) { printk(BIOS_ERR, " EC Critical Battery Error\n"); critical_shutdown = 1; -#if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, + elog_gsmi_add_event_word(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_BATTERY_CRITICAL); -#endif } if ((ec_reg & 0x8F) == 0x8F) { printk(BIOS_ERR, " EC Read Battery Error\n"); -#if CONFIG(ELOG_GSMI) - elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_BATTERY); -#endif + elog_gsmi_add_event_word(ELOG_TYPE_EC_EVENT, EC_HOST_EVENT_BATTERY); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf7b04edc3fce147f7857691ce7d6a0ce03f43fe Gerrit-Change-Number: 36649 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: ELOG, soc/intel: Avoid some preprocessor use
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36646 ) Change subject: ELOG, soc/intel: Avoid some preprocessor use ...................................................................... ELOG, soc/intel: Avoid some preprocessor use Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/include/soc/pmc.h M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/smm.c M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/smm.c 7 files changed, 6 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/36646/1 diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 09d1322..6cdf419 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,11 +281,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 4f01922..9f10f70 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -38,7 +38,8 @@ uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5063342..744fcf0 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,11 +242,7 @@ void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 364cda5..c108a36 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -39,7 +39,8 @@ uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index af840a2..62201d9 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -262,14 +262,4 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1) -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -#if CONFIG(ELOG) -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - #endif /* _DENVERTON_NS_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 71c8e10..9e588ad 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -285,11 +285,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 0c40429..fbfd094 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -40,7 +40,8 @@ uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); -- To view, visit https://review.coreboot.org/c/coreboot/+/36646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Gerrit-Change-Number: 36646 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: sb,soc/intel: Reduce prepocessor use with ME debugging
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36639 ) Change subject: sb,soc/intel: Reduce prepocessor use with ME debugging ...................................................................... sb,soc/intel: Reduce prepocessor use with ME debugging Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/include/soc/me.h M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c 9 files changed, 70 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36639/1 diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index a213e37..69b75b4 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -493,11 +493,7 @@ void intel_me_hsio_version(uint16_t *version, uint16_t *checksum); -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(void); -#else -static inline void intel_me_status(void) { } -#endif #endif diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 6be1748..0461428 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,13 @@ /* MMIO base address for MEI interface */ static u8 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -88,9 +90,6 @@ break; } } -#else -# define mei_dump(ptr, dword, offset, type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -483,7 +482,6 @@ vers_name->hotfix_version, vers_name->build_version); } -#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -536,7 +534,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif /* Send END OF POST message to the ME */ static int mkhi_end_of_post(void) @@ -804,9 +801,8 @@ { me_print_fw_version(mbp_data->fw_version_name); -#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data->fw_capabilities); -#endif + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data->fw_capabilities); if (mbp_data->plat_time) { printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", @@ -912,12 +908,12 @@ } /* Dump out the MBP contents. */ -#if CONFIG(DEBUG_INTEL_ME) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); - for (i = 0; i < mbp->header.mbp_size - 1; i++) - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); -#endif + if (CONFIG(DEBUG_INTEL_ME)) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + for (i = 0; i < mbp->header.mbp_size - 1; i++) + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } #define ASSIGN_FIELD_PTR(field_, val_) \ { \ diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 08fd48f..1880da1 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -34,8 +34,6 @@ memcpy(ptr, &dword, sizeof(dword)); } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -210,6 +208,9 @@ void intel_me_status(void) { + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + struct me_hfs _hfs, *hfs = &_hfs; struct me_hfs2 _hfs2, *hfs2 = &_hfs2; @@ -302,7 +303,6 @@ } printk(BIOS_DEBUG, "\n"); } -#endif void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ea60085..5e355a1 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -60,11 +60,13 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -90,9 +92,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -373,9 +372,8 @@ } #endif -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ -static int mkhi_get_fw_version(void) +static int __unused mkhi_get_fw_version(void) { struct me_fw_version version; struct mkhi_header mkhi = { @@ -412,7 +410,7 @@ } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) +static int __unused mkhi_get_fwcaps(void) { u32 rule_id = 0; struct me_fwcaps cap; @@ -454,7 +452,6 @@ return 0; } -#endif #if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -714,12 +711,12 @@ if (intel_mei_setup(dev) < 0) break; -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); + } /* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 54c3fff..c224cb4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -62,11 +62,14 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) + static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -92,9 +95,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -350,14 +350,13 @@ return 0; } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); } -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -395,7 +394,7 @@ } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_fw_caps *caps_section) +static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; if (!caps_section->available) { @@ -421,7 +420,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif #if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -719,10 +717,10 @@ } #endif -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(&mbp_data.fw_version_name); + me_print_fwcaps(&mbp_data.fw_caps_sku); + } /* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376..4d9540a 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "me.h" -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -137,11 +136,12 @@ [0x0f] = "ME cannot access the chipset descriptor region", [0x10] = "Required VSCC values for flash parts do not match", }; -#endif void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -204,5 +204,4 @@ printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); } printk(BIOS_DEBUG, "\n"); -#endif } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index f804126..c944f63 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -59,11 +59,13 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -89,9 +91,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 59a8666..1c45e2d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -66,11 +66,13 @@ void intel_me_mbp_clear(struct device *dev); #endif -#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; + if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); switch (offset) { @@ -96,9 +98,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif /* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -380,7 +379,6 @@ return mei_wait_for_me_ready(); } -#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -418,7 +416,6 @@ return 0; } -#endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */ /* * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read @@ -469,8 +466,7 @@ } } -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -482,7 +478,6 @@ vers_name->hotfix_version, vers_name->build_version); } -#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -510,7 +505,7 @@ } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) +static void __unused me_print_fwcaps(mbp_mefwcaps *cap) { mbp_mefwcaps local_caps; if (!cap) { @@ -535,8 +530,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif /* CONFIG_DEBUG_INTEL_ME */ -#endif #if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -851,21 +844,21 @@ if (intel_me_read_mbp(&mbp_data, dev)) return; -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data.fw_capabilities); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(mbp_data.fw_version_name); - if (mbp_data.plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data.fw_capabilities); + + if (mbp_data.plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data.plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data.plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data.plat_time->pltrst_cpurst_time_ms); + } } -#endif /* Set clock enables according to devicetree */ if (config && config->icc_clock_disable) @@ -1004,15 +997,15 @@ #endif /* Dump out the MBP contents. */ -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG(DEBUG_INTEL_ME) - for (i = 0; i < mbp->header.mbp_size - 1; i++) { - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + if (CONFIG(DEBUG_INTEL_ME)) { + for (i = 0; i < mbp->header.mbp_size - 1; i++) { + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } + } } -#endif -#endif #define ASSIGN_FIELD_PTR(field_,val_) \ { \ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca5552..ad8362d 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "me.h" -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -138,11 +137,12 @@ [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -#endif void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -206,5 +206,4 @@ hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); -#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/36639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Gerrit-Change-Number: 36639 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: arch/x86: Drop some __SMM__ guards
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36637 ) Change subject: arch/x86: Drop some __SMM__ guards ...................................................................... arch/x86: Drop some __SMM__ guards Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/smm.h M src/mainboard/google/stout/ec.h M src/mainboard/hp/pavilion_m6_1035dx/ec.h M src/mainboard/lenovo/g505s/ec.h M src/mainboard/lenovo/s230u/ec.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/intel/broadwell/include/soc/xhci.h M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/pi/hudson/smi.h 15 files changed, 5 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36637/1 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 53a77a9..94fb3f1 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -81,12 +81,9 @@ #define PSS_LATENCY_BUSMASTER 10 #ifndef __ROMCC__ -#ifdef __SMM__ /* Lock MSRs */ void intel_model_406dx_finalize_smm(void); -#else int cpu_config_tdp_levels(void); #endif -#endif #endif /* _CPU_INTEL_MODEL_406DX_H */ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8087edb..f6982d9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -69,14 +69,12 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -#ifdef __SMM__ /* Lock MSRs */ void intel_model_2065x_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f2a0b71..7017c12 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -93,14 +93,12 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -#endif int get_platform_id(void); #endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8b9efe..cf107b1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -86,7 +86,6 @@ /* smm_handler_t is called with arg of smm_module_params pointer. */ typedef asmlinkage void (*smm_handler_t)(void *); -#ifdef __SMM__ /* SMM Runtime helpers. */ /* Entry point for SMM modules. */ @@ -95,7 +94,6 @@ /* Retrieve SMM save state for a given CPU. WARNING: This does not take into * account CPUs which are configured to not save their state to RAM. */ void *smm_get_save_state(int cpu); -#endif /* __SMM__ */ /* SMM Module Loading API */ diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index 8c7882f..f035e24 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -22,10 +22,7 @@ #define EC_SMI_LID_CLOSED 0x2B #ifndef __ACPI__ -extern void stout_ec_init(void); -#endif - -#ifdef __SMM__ +void stout_ec_init(void); void stout_ec_finalize_smm(void); #endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 40e33ee..5567251 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -19,8 +19,6 @@ #include "mainboard.h" -#ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); -#endif #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H */ diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 86fd673..52a3ab7 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -19,8 +19,6 @@ #include "mainboard.h" -#ifndef __SMM__ void lenovo_g505s_ec_init(void); -#endif #endif /* _MAINBOARD_LENOVO_G505S_EC_H */ diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index 87fbc7f..a5bc423 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -17,9 +17,7 @@ #ifndef _MAINBOARD_LENOVO_S230U_EC_H #define _MAINBOARD_LENOVO_S230U_EC_H -#ifndef __SMM__ void lenovo_s230u_ec_init(void); -#endif #define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) #define ec_mm_read(addr) (ECMM(0x100 + addr)) diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index ebec63d..493c5b1 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -249,17 +249,14 @@ #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 -#ifdef __SMM__ void intel_nehalem_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap); -#endif /* !__SMM__ */ - #endif #endif #endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8664c5d..31d4358 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -203,9 +203,8 @@ #ifndef __ASSEMBLER__ -#ifdef __SMM__ void intel_sandybridge_finalize_smm(void); -#else /* !__SMM__ */ + int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); @@ -213,8 +212,6 @@ void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); -#endif /* !__SMM__ */ - void pch_enable_lpc(void); void mainboard_early_init(int s3resume); void mainboard_config_superio(void); diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 66c2050..e7f9da6 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -232,8 +232,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#ifndef __SMM__ void enable_smi_generation(void); -#endif #endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 000eed8..5301dd7 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -235,8 +235,6 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#ifndef __SMM__ void enable_smi_generation(void); -#endif #endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h index 33e4c2d..87a5934 100644 --- a/src/soc/intel/broadwell/include/soc/xhci.h +++ b/src/soc/intel/broadwell/include/soc/xhci.h @@ -50,8 +50,6 @@ #define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ -#ifdef __SMM__ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); -#endif #endif diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index d1594f3..5e0c09a 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); -#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif #endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index dde9d6e..684dca5 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -71,8 +71,6 @@ void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); -#ifndef __SMM__ void hudson_enable_smi_generation(void); -#endif #endif /* _SOUTHBRIDGE_AMD_PI_HUDSON_SMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Gerrit-Change-Number: 36637 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: intel/braswell: Remove duplicate set_max_freq() prototypes
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36640 ) Change subject: intel/braswell: Remove duplicate set_max_freq() prototypes ...................................................................... intel/braswell: Remove duplicate set_max_freq() prototypes Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/braswell/bootblock/bootblock.c D src/soc/intel/braswell/include/soc/bootblock.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/include/soc/ramstage.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/braswell/tsc_freq.c 6 files changed, 1 insertion(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36640/1 diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index d8d953c..6147dca 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> -#include <soc/bootblock.h> #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/iosf.h> diff --git a/src/soc/intel/braswell/include/soc/bootblock.h b/src/soc/intel/braswell/include/soc/bootblock.h deleted file mode 100644 index e6e25cc..0000000 --- a/src/soc/intel/braswell/include/soc/bootblock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_BOOTBLOCK_H_ -#define _SOC_BOOTBLOCK_H_ - -void set_max_freq(void); - -#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 6137820..d0bfc8a 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -41,5 +41,6 @@ /* Read BCLK from MSR */ unsigned int cpu_bus_freq_khz(void); +void set_max_freq(void); #endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index f197bc8..17db2d8 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -98,7 +98,6 @@ */ void soc_init_pre_device(struct soc_intel_braswell_config *config); void soc_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); int SocStepping(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 9fad9bc..c9b559a 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -24,7 +24,6 @@ void gfx_init(void); void punit_init(void); -void set_max_freq(void); /* romstage.c functions */ int chipset_prev_sleep_state(struct chipset_power_state *ps); diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 28e3761..923d10c 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -17,11 +17,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/msr.h> -#if ENV_RAMSTAGE -#include <soc/ramstage.h> -#else -#include <soc/romstage.h> -#endif #include <stdint.h> static const unsigned int cpu_bus_clk_freq_table[] = { @@ -57,8 +52,6 @@ return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !ENV_SMM - void set_max_freq(void) { msr_t perf_ctl; @@ -91,5 +84,3 @@ wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* ENV_SMM */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195 Gerrit-Change-Number: 36640 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: eltan/security: Replace __PRE_RAM__ with ENV_ROMSTAGE_OR_BEFORE
by Patrick Georgi (Code Review) 08 Nov '19

08 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36635 ) Change subject: eltan/security: Replace __PRE_RAM__ with ENV_ROMSTAGE_OR_BEFORE ...................................................................... eltan/security: Replace __PRE_RAM__ with ENV_ROMSTAGE_OR_BEFORE Change-Id: Id56a63a67b7eb70dce6687bb9c2734a711f611b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36635 Reviewed-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/eltan/security/verified_boot/vboot_check.c 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Wim Vervoorn: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, approved diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index f77636b..1dc1c3a 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -222,16 +222,14 @@ start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); if (start && size) { /* Speed up processing by copying the file content to memory first */ -#ifndef __PRE_RAM__ - if ((type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && (*buffer) && - ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { + if (!ENV_ROMSTAGE_OR_BEFORE && (type & VERIFIED_BOOT_COPY_BLOCK) && (buffer) && + (*buffer) && ((uint32_t) start > (uint32_t)(~(CONFIG_CBFS_SIZE-1)))) { printk(BIOS_DEBUG, "%s: move buffer to memory\n", __func__); /* Move the file to a memory bufferof which we know it doesn't harm */ memcpy(*buffer, start, size); start = *buffer; printk(BIOS_DEBUG, "%s: done\n", __func__); } -#endif // __PRE_RAM__ verified_boot_check_buffer(name, start, size, hash_index, pcr); } else { printk(BIOS_EMERG, "CBFS Failed to get file content for %s\n", name); -- To view, visit https://review.coreboot.org/c/coreboot/+/36635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id56a63a67b7eb70dce6687bb9c2734a711f611b3 Gerrit-Change-Number: 36635 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wvervoorn <wvervoorn(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: eltan/security: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36634 ) Change subject: eltan/security: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK ...................................................................... eltan/security: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK Change-Id: I6ec5a33cd6a6342adfe73c050e0c376bbefad96a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/eltan/security/verified_boot/vboot_check.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/36634/1 diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 0e96f52..d08fa44 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -131,8 +131,6 @@ return 0; } -#ifndef __BOOTBLOCK__ - /* * * measure_item @@ -168,7 +166,6 @@ } return status; } -#endif static void verified_boot_check_buffer(const char *name, void *start, size_t size, uint32_t hash_index, int32_t pcr) @@ -198,8 +195,7 @@ printk(BIOS_EMERG, "%s ", name); die("HASH verification failed!\n"); } else { -#ifndef __BOOTBLOCK__ - if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { + if (!ENV_BOOTBLOCK && CONFIG(VENDORCODE_ELTAN_MBOOT)) { if (pcr != -1) { printk(BIOS_DEBUG, "%s: measuring %s\n", __func__, name); if (measure_item(pcr, digest, sizeof(digest), @@ -208,7 +204,6 @@ __func__); } } -#endif if (CONFIG(VENDORCODE_ELTAN_VBOOT)) printk(BIOS_DEBUG, "%s HASH verification success\n", name); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ec5a33cd6a6342adfe73c050e0c376bbefad96a Gerrit-Change-Number: 36634 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: eltan/security: Remove some preprocessor guards
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36632 ) Change subject: eltan/security: Remove some preprocessor guards ...................................................................... eltan/security: Remove some preprocessor guards We generally let garbage-collection take care of unused functions. While at it, move some related variable declarations in to the header file and declare them const like they should be. Change-Id: I7c6fa15bd45f861f13b6123ccb14c55415e42bc7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M src/vendorcode/eltan/security/verified_boot/vboot_check.h 3 files changed, 6 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/36632/1 diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 4823c6a..228d1a0 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -266,7 +266,6 @@ return status; } -#ifdef __PRE_RAM__ /* * Called from early romstage * @@ -473,4 +472,3 @@ return status; } -#endif // __PRE_RAM__ diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 88519bd..0e96f52 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,13 +276,11 @@ i++; } } -#ifdef __BOOTBLOCK__ + /* * BOOTBLOCK */ -extern verify_item_t bootblock_verify_list[]; - void verified_boot_bootblock_check(void) { printk(BIOS_SPEW, "%s: processing bootblock items\n", __func__); @@ -301,9 +299,7 @@ printk(BIOS_SPEW, "%s: bootblock\n", __func__); verified_boot_bootblock_check(); } -#endif //__BOOTBLOCK__ -#ifdef __ROMSTAGE__ /* * ROMSTAGE */ @@ -340,23 +336,17 @@ prepare_romstage = 1; } } -#endif //__ROMSTAGE__ -#ifdef __POSTCAR__ /* * POSTCAR */ -extern verify_item_t postcar_verify_list[]; - static void vendor_secure_prepare(void) { printk(BIOS_SPEW, "%s: postcar\n", __func__); process_verify_list(postcar_verify_list); } -#endif //__POSTCAR__ -#ifdef __RAMSTAGE__ /* * RAM STAGE */ @@ -408,10 +398,6 @@ return 0; } -extern verify_item_t payload_verify_list[]; - -extern verify_item_t oprom_verify_list[]; - int verified_boot_should_run_oprom(struct rom_header *rom_header) { return process_oprom_list(oprom_verify_list, rom_header); @@ -422,7 +408,6 @@ printk(BIOS_SPEW, "%s: ramstage\n", __func__); process_verify_list(payload_verify_list); } -#endif //__RAMSTAGE__ const struct cbfs_locator cbfs_master_header_locator = { .name = "Vendorcode Header Locator", diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index 22f1edf..36c8ffa 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -32,12 +32,8 @@ /* These method verifies the SHA256 hash over the 'named' CBFS component. * 'type' denotes the type of CBFS component i.e. stage, payload or fsp. */ -#ifdef __BOOTBLOCK__ void verified_boot_bootblock_check(void); -#endif -#ifdef __ROMSTAGE__ void verified_boot_early_check(void); -#endif int verified_boot_check_manifest(void); @@ -75,4 +71,9 @@ void process_verify_list(const verify_item_t list[]); +extern const verify_item_t bootblock_verify_list[]; +extern const verify_item_t postcar_verify_list[]; +extern const verify_item_t payload_verify_list[]; +extern const verify_item_t oprom_verify_list[]; + #endif //VBOOT_CHECK_H -- To view, visit https://review.coreboot.org/c/coreboot/+/36632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c6fa15bd45f861f13b6123ccb14c55415e42bc7 Gerrit-Change-Number: 36632 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/facebook/fbg1701: Remove some preprocessor guards
by Kyösti Mälkki (Code Review) 08 Nov '19

08 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36633 ) Change subject: mb/facebook/fbg1701: Remove some preprocessor guards ...................................................................... mb/facebook/fbg1701: Remove some preprocessor guards Change-Id: Ia7289fa8337e1a93e620a52a67ca8cbdd78a66bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/facebook/fbg1701/board_verified_boot.c 1 file changed, 2 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36633/1 diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 1ccb0b8e..bb5768f 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -15,7 +15,6 @@ #include "board_verified_boot.h" -#ifdef __BOOTBLOCK__ /* The items verified by the bootblock, the bootblock will not measure the * items to the TPM */ @@ -32,9 +31,7 @@ MBOOT_PCR_INDEX_0 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -#if defined(__ROMSTAGE__) || defined(__POSTCAR__) /* The FSP is already checked in romstage */ static const verify_item_t ram_stage_additional_list[] = { { VERIFY_FILE, OP_ROM_VBT, { { NULL, CBFS_TYPE_RAW } }, @@ -44,10 +41,8 @@ { VERIFY_FILE, "fallback/dsdt.aml", { { NULL, CBFS_TYPE_RAW } }, HASH_IDX_DSDT, MBOOT_PCR_INDEX_2 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } - }; -#endif +}; -#ifdef __ROMSTAGE__ /* The items used by the romstage */ const verify_item_t romstage_verify_list[] = { { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, @@ -75,10 +70,8 @@ CBFS_TYPE_STAGE } }, HASH_IDX_RAM_STAGE, MBOOT_PCR_INDEX_0 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -#ifdef __POSTCAR__ -/* POSTSTAGE */ +/* POSTCAR */ /* The items used by the postcar stage */ const verify_item_t postcar_verify_list[] = { { VERIFY_FILE, RAMSTAGE, { { ram_stage_additional_list, @@ -91,9 +84,7 @@ MBOOT_PCR_INDEX_1 }, { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -#ifdef __RAMSTAGE__ /* RAMSTAGE */ const verify_item_t payload_verify_list[] = { { VERIFY_FILE, PAYLOAD, { { NULL, CBFS_TYPE_SELF | @@ -105,4 +96,3 @@ const verify_item_t oprom_verify_list[] = { { VERIFY_TERMINATOR, NULL, { { NULL, 0 } }, 0, 0 } }; -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7289fa8337e1a93e620a52a67ca8cbdd78a66bc Gerrit-Change-Number: 36633 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

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