coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Copy acpi directory from icelake
by Subrata Banik (Code Review) 06 Nov '19

06 Nov '19

Hello Raj Astekar, Aaron Durbin, Patrick Rudolph, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36553 to look at the new patch set (#4). Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ...................................................................... soc/intel/tigerlake/acpi: Copy acpi directory from icelake Clone entirely from Icelake Tiger Lake specific changes will follow in subsequent patches. 1. Modify IP/Controller B:D:F as applicable as per TGP PCH "The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware." Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/pch_glan.asl A src/soc/intel/tigerlake/acpi/pch_hda.asl A src/soc/intel/tigerlake/acpi/pci_irqs.asl A src/soc/intel/tigerlake/acpi/pcie.asl A src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/scs.asl A src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/smbus.asl A src/soc/intel/tigerlake/acpi/southbridge.asl A src/soc/intel/tigerlake/acpi/xhci.asl 12 files changed, 1,507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/36553/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/36553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Gerrit-Change-Number: 36553 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Do initial SoC commit till ramstage
by build bot (Jenkins) (Code Review) 06 Nov '19

06 Nov '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 ) Change subject: soc/intel/tigerlake: Do initial SoC commit till ramstage ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/36087/15/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/ramstage.h: https://review.coreboot.org/c/coreboot/+/36087/15/src/soc/intel/tigerlake/i… PS15, Line 24: void mainboard_silicon_init_params(FSP_S_CONFIG *params); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/36087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Gerrit-Change-Number: 36087 Gerrit-PatchSet: 15 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Nov 2019 14:32:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Copy acpi directory from icelake
by Subrata Banik (Code Review) 06 Nov '19

06 Nov '19

Hello Raj Astekar, Aaron Durbin, Patrick Rudolph, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36553 to look at the new patch set (#3). Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ...................................................................... soc/intel/tigerlake/acpi: Copy acpi directory from icelake Clone entirely from Icelake Tiger Lake specific changes will follow in subsequent patches. 1. Modify IP/Controller B:D:F as applicable as per TGP PCH "The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware." Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/pch_glan.asl A src/soc/intel/tigerlake/acpi/pch_hda.asl A src/soc/intel/tigerlake/acpi/pci_irqs.asl A src/soc/intel/tigerlake/acpi/pcie.asl A src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/scs.asl A src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/smbus.asl A src/soc/intel/tigerlake/acpi/southbridge.asl A src/soc/intel/tigerlake/acpi/xhci.asl 12 files changed, 1,507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/36553/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Gerrit-Change-Number: 36553 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Create preprocessed __ROMCC__ bootblock source
by Kyösti Mälkki (Code Review) 06 Nov '19

06 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35602 ) Change subject: arch/x86: Create preprocessed __ROMCC__ bootblock source ...................................................................... arch/x86: Create preprocessed __ROMCC__ bootblock source Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35602/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 612424d..055911c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -163,6 +163,8 @@ @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d + $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ + $< > $(objgenerated)/bootblock_romcc.c $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ # bootblock.ld is part of $(bootblock-objs) -- To view, visit https://review.coreboot.org/c/coreboot/+/35602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Gerrit-Change-Number: 35602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIP
by Patrick Georgi (Code Review) 06 Nov '19

06 Nov '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36170 ) Change subject: drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIP ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/36170/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36170/5//COMMIT_MSG@9 PS5, Line 9: FSP > How so? This seems to be deep in nitpick territory (of course the CPU's capabilities have an influence on what FSP can do), and given that the comment to FSP_M_XIP states that FSP-M is execute-in-place... -- To view, visit https://review.coreboot.org/c/coreboot/+/36170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80 Gerrit-Change-Number: 36170 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Nov 2019 14:05:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Move Debug options to "Debugging"
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36165 ) Change subject: drivers/intel/fsp2_0: Move Debug options to "Debugging" ...................................................................... drivers/intel/fsp2_0: Move Debug options to "Debugging" TODO: Is verify HOBS really 'Debugging' and should this really be optional? Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/drivers/intel/fsp2_0/Kconfig 2 files changed, 40 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36165/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..80efb12 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,46 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + +config DISPLAY_FSP_HEADER + bool "Display the FSP header" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP header information when the FSP file is found. + +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP HOBs which are provided for coreboot. + +config DISPLAY_UPD_DATA + bool "Display UPD data" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the user specified product data prior to memory + initialization. + +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + depends on PLATFORM_USES_FSP2_0 + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + + + endmenu diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1e84dab..fee5de4 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,32 +39,6 @@ Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. -config DISPLAY_FSP_CALLS_AND_STATUS - bool "Display the FSP calls and status" - default n - help - Display the FSP call entry point and parameters prior to calling FSP - and display the status upon return from FSP. - -config DISPLAY_FSP_HEADER - bool "Display the FSP header" - default n - help - Display the FSP header information when the FSP file is found. - -config DISPLAY_HOBS - bool "Display the hand-off-blocks" - default n - help - Display the FSP HOBs which are provided for coreboot. - -config DISPLAY_UPD_DATA - bool "Display UPD data" - default n - help - Display the user specified product data prior to memory - initialization. - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" depends on FSP_CAR @@ -161,13 +135,6 @@ stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config VERIFY_HOBS - bool "Verify the FSP hand-off-blocks" - default n - help - Verify that the HOBs required by coreboot are returned by FSP and - that the resource HOBs are in the correct order and position. - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Gerrit-Change-Number: 36165 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: Kconfig: Organize debugging options per file extensions
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36616 ) Change subject: Kconfig: Organize debugging options per file extensions ...................................................................... Kconfig: Organize debugging options per file extensions Change-Id: Ia4553fb4cd95d2f1fa86eecbf382e6e6dec52b92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig R src/cpu/x86/Kconfig.debug_cpu 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/36616/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..38796b4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -738,7 +738,10 @@ menu "Debugging" comment "CPU Debug Settings" -source "src/cpu/*/Kconfig.debug" +source "src/*/Kconfig.debug_cpu" +source "src/*/*/Kconfig.debug_cpu" +source "src/*/*/*/Kconfig.debug_cpu" +source "src/*/*/*/*/Kconfig.debug_cpu" comment "General Debug Settings" diff --git a/src/cpu/x86/Kconfig.debug b/src/cpu/x86/Kconfig.debug_cpu similarity index 100% rename from src/cpu/x86/Kconfig.debug rename to src/cpu/x86/Kconfig.debug_cpu -- To view, visit https://review.coreboot.org/c/coreboot/+/36616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4553fb4cd95d2f1fa86eecbf382e6e6dec52b92 Gerrit-Change-Number: 36616 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/lint/kconfig_lint: Handle glob prefix and suffix
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36626 ) Change subject: util/lint/kconfig_lint: Handle glob prefix and suffix ...................................................................... util/lint/kconfig_lint: Handle glob prefix and suffix Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/lint/kconfig_lint 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36626/1 diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 47f0494..9ab05db 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -1213,9 +1213,11 @@ my @dir_file_data; #recursively handle coreboot's new source glob operator - if ( $input_file =~ /^(.*?)\/\*\/(.*)$/ ) { + if ( $input_file =~ /^(.*?)\/(\w*)\*(\w*)\/(.*)$/ ) { my $dir_prefix = $1; - my $dir_suffix = $2; + my $dir_glob_prefix = $2; + my $dir_glob_suffix = $3; + my $dir_suffix = $4; if ( -d "$dir_prefix" ) { opendir( D, "$dir_prefix" ) || die "Can't open directory '$dir_prefix'\n"; @@ -1225,7 +1227,8 @@ while ( my $directory = shift @dirlist ) { #ignore non-directory files - if ( ( -d "$dir_prefix/$directory" ) && !( $directory =~ /^\..*/ ) ) { + if ( ( -d "$dir_prefix/$directory" ) && !( $directory =~ /^\..*/ ) + && ( $directory =~ /$dir_glob_prefix.*$dir_glob_suffix/ ) ) { push @dir_file_data, load_kconfig_file( "$dir_prefix/$directory/$dir_suffix", $input_file, $loadline, 1, $loadfile, $loadline ); -- To view, visit https://review.coreboot.org/c/coreboot/+/36626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937 Gerrit-Change-Number: 36626 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: add calculate crc byte by byte
by Xiang Wang (Code Review) 06 Nov '19

06 Nov '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36624 ) Change subject: lib: add calculate crc byte by byte ...................................................................... lib: add calculate crc byte by byte Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- A src/include/crc_byte.h M src/lib/Makefile.inc A src/lib/crc_byte.c 3 files changed, 140 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36624/1 diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h new file mode 100644 index 0000000..07e2aeb --- /dev/null +++ b/src/include/crc_byte.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CRC_BYTE_H +#define CRC_BYTE_H + +#include <stdint.h> + +/* This function is used to calculate crc7 byte by byte. + * prev_crc: old crc result + * data: new byte + * return value: new crc result + */ +uint8_t crc7_byte(uint8_t prev_crc, uint8_t data); + +/* This function is used to calculate crc16 byte by byte. + * prev_crc: old crc result + * data: new byte + * return value: new crc result + */ +uint16_t crc16_byte(uint16_t prev_crc, uint8_t data); + + +#endif /* CRC_BYTE_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e5678ff..23468c9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -249,6 +249,14 @@ ramstage-y += string.c smm-y += string.c +decompressor-y += crc_byte.c +bootblock-y += crc_byte.c +verstage-y += crc_byte.c +romstage-y += crc_byte.c +postcar-y += crc_byte.c +ramstage-y += crc_byte.c +smm-y += crc_byte.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c diff --git a/src/lib/crc_byte.c b/src/lib/crc_byte.c new file mode 100644 index 0000000..9a89f55 --- /dev/null +++ b/src/lib/crc_byte.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <crc_byte.h> + +static const uint8_t crc7_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, + 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, + 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, + 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, + 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, + 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, + 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, + 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, + 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, + 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, + 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, + 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, + 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, + 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, + 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, + 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, + 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, + 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, + 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79 +}; + +uint8_t crc7_byte(uint8_t crc, uint8_t data) +{ + return crc7_table[(crc << 1) ^ data]; +} + +static const uint16_t crc16_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, +}; + +uint16_t crc16_byte(uint16_t prev, uint8_t in) +{ + return crc16_tab[((prev >> 8) ^ in) & 0xff] ^ (prev << 8); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992 Gerrit-Change-Number: 36624 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/g/drallion: Override smbios enclosure type for drallion
by Mathew King (Code Review) 06 Nov '19

06 Nov '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36512 ) Change subject: mb/g/drallion: Override smbios enclosure type for drallion ...................................................................... mb/g/drallion: Override smbios enclosure type for drallion Drallion can be either a clamshell or convertible depending on the presence of the 360 sensor board. Set the smbios type 3 enclosure type to either CONVERTIBLE or LAPTOP accordingly. BUG=b:143701965 TEST='dmidecode -t 3' Type = Convertible with sensor board connected Type = Laptop with sensor board disconnected Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/smbios.c 4 files changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36512/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 5edf3c6..261888f 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -492,7 +492,7 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } -u8 __weak smbios_mainboard_enclosure_type(void) +smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) { return CONFIG_SMBIOS_ENCLOSURE_TYPE; } diff --git a/src/include/smbios.h b/src/include/smbios.h index ef1c7de..d230fb2 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -65,7 +65,6 @@ const char *smbios_mainboard_asset_tag(void); u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); -u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) @@ -319,7 +318,7 @@ u8 eos[2]; } __packed; -enum { +typedef enum { SMBIOS_ENCLOSURE_OTHER = 0x01, SMBIOS_ENCLOSURE_UNKNOWN = 0x02, SMBIOS_ENCLOSURE_DESKTOP = 0x03, @@ -356,7 +355,7 @@ SMBIOS_ENCLOSURE_EMBEDDED_PC = 0x22, SMBIOS_ENCLOSURE_MINI_PC = 0x23, SMBIOS_ENCLOSURE_STICK_PC = 0x24, -}; +} smbios_enclosure_type; struct smbios_type3 { u8 type; @@ -798,5 +797,6 @@ struct smbios_type17 *t); smbios_board_type smbios_mainboard_board_type(void); +smbios_enclosure_type smbios_mainboard_enclosure_type(void); #endif diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index ccbcb08..7e4edc1 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -32,3 +32,5 @@ romstage-y += memory.c ramstage-y += sku.c + +ramstage-y += smbios.c diff --git a/src/mainboard/google/drallion/variants/drallion/smbios.c b/src/mainboard/google/drallion/variants/drallion/smbios.c new file mode 100644 index 0000000..f6c8491 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/smbios.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <variant/gpio.h> +#include <gpio.h> +#include <smbios.h> + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + if (gpio_get(SENSOR_DET_360) == 0) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + return SMBIOS_ENCLOSURE_LAPTOP; +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Gerrit-Change-Number: 36512 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019