coreboot-gerrit November 2019

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Change in coreboot[master]: mb/g/drallion: Consolidate 360 sensor board detection
by Mathew King (Code Review) 06 Nov '19

06 Nov '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36617 ) Change subject: mb/g/drallion: Consolidate 360 sensor board detection ...................................................................... mb/g/drallion: Consolidate 360 sensor board detection Create a single function to determine if the 360 sensor board is present on a device. BUG=b:143701965 TEST='emerge-drallion coreboot' Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/sku.c 3 files changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/36617/1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 5657eea..086dca0 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -14,6 +14,7 @@ */ #include <variant/gpio.h> +#include <variant/variant.h> #include <vendorcode/google/chromeos/chromeos.h> #include <gpio.h> #include <soc/romstage.h> @@ -274,17 +275,11 @@ return cros_gpios; } -static int is_ish_device_enabled(void) -{ - gpio_input(SENSOR_DET_360); - return gpio_get(SENSOR_DET_360) == 0; -} - void variant_mainboard_post_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig; if (fsp_m_cfg->PchIshEnable) - fsp_m_cfg->PchIshEnable = is_ish_device_enabled(); + fsp_m_cfg->PchIshEnable = has_360_sensor_board(); /* * Disable memory channel by HW strap pin, HW default is enable diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index 508654f..71d78ad 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -16,6 +16,9 @@ #ifndef VARIANT_H #define VARIANT_H +#include <gpio.h> +#include <variant/gpio.h> + /* Need to update for Drallion with right SKU IDs*/ typedef struct { int id; @@ -36,4 +39,9 @@ /* Return memory SKU for the variant */ int variant_memory_sku(void); +/* Check if the device has a 360 sensor board present */ +static inline int has_360_sensor_board(void) { + return gpio_get(SENSOR_DET_360) == 0; +} + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/sku.c b/src/mainboard/google/drallion/variants/drallion/sku.c index 7277629..736a145 100644 --- a/src/mainboard/google/drallion/variants/drallion/sku.c +++ b/src/mainboard/google/drallion/variants/drallion/sku.c @@ -14,15 +14,13 @@ */ #include <boardid.h> -#include <ec/google/wilco/commands.h> #include <smbios.h> +#include <ec/google/wilco/commands.h> #include <variant/variant.h> -#include <gpio.h> -#include <variant/gpio.h> static const uint32_t get_sku_index(void) { - return (gpio_get(SENSOR_DET_360) | (wilco_ec_signed_fw() << 1)); + return ((!has_360_sensor_board()) | (wilco_ec_signed_fw() << 1)); } uint32_t sku_id(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/36617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169 Gerrit-Change-Number: 36617 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: arch/riscv: Make the setting of fdt calling argument more explicit
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36599 ) Change subject: arch/riscv: Make the setting of fdt calling argument more explicit ...................................................................... arch/riscv: Make the setting of fdt calling argument more explicit Make sure to only rely on prog_entry_arg() in certain situations. For instance in romstage cbmem_top() is programmed there instead of the fdt. Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/boot.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/36599/1 diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 6a23b8a..ecc230f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -38,20 +38,22 @@ { int hart_id; struct prog *prog = args->prog; - void *fdt = prog_entry_arg(prog); + void *fdt = NULL; - /* - * Workaround selfboot putting the coreboot table into prog_entry_arg - */ if (prog_cbfs_type(prog) == CBFS_TYPE_SELF) fdt = HLS()->fdt; + if ((ENV_BOOTBLOCK || ENV_ROMSTAGE) && prog_cbfs_type(prog) == CBFS_TYPE_STAGE) + fdt = HLS()->fdt; /* * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS * instead. */ - if (fdt == NULL) - fdt = HLS()->fdt; + if (ENV_RAMSTAGE) { + fdt = prog_entry_arg(prog); + if (fdt == NULL) + fdt = HLS()->fdt; + } if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { if (CONFIG(RISCV_OPENSBI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/36599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9 Gerrit-Change-Number: 36599 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: arch/riscv: Rename `stages.c` to `romstage.c`
by Nico Huber (Code Review) 06 Nov '19

06 Nov '19

Hello Arthur Heymans, Jonathan Neuschäfer, Philipp Hug, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36611 to review the following change. Change subject: arch/riscv: Rename `stages.c` to `romstage.c` ...................................................................... arch/riscv: Rename `stages.c` to `romstage.c` It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/riscv/Makefile.inc R src/arch/riscv/romstage.c 2 files changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36611/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 16f160e..0038523 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -98,7 +98,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c -romstage-y += stages.c +romstage-y += romstage.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/romstage.c similarity index 73% rename from src/arch/riscv/stages.c rename to src/arch/riscv/romstage.c index 5b27508..d5f5a43 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/romstage.c @@ -14,10 +14,6 @@ */ /* - * This file contains entry/exit functions for each stage during coreboot - * execution (bootblock entry and ramstage exit will depend on external - * loading). - * * Entry points must be placed at the location the previous stage jumps * to (the lowest address in the stage image). This is done by giving * stage_entry() its own section in .text and placing it first in the @@ -31,11 +27,6 @@ void stage_entry(int hart_id, void *fdt) { - /* - * Save the FDT pointer before entering ramstage, because mscratch - * might be overwritten in the trap handler, and there is code in - * ramstage that generates misaligned access faults. - */ HLS()->hart_id = hart_id; HLS()->fdt = fdt; smp_pause(CONFIG_RISCV_WORKING_HARTID); -- To view, visit https://review.coreboot.org/c/coreboot/+/36611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Gerrit-Change-Number: 36611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: security/vboot/Kconfig: Remove unused symbols
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36605 ) Change subject: security/vboot/Kconfig: Remove unused symbols ...................................................................... security/vboot/Kconfig: Remove unused symbols Change-Id: I417a2ff45b4a8f5bc800459a64f1c5a861fcd3d5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/galileo/Kconfig M src/security/vboot/Kconfig 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/36605/1 diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 37f88dd..84f09c4 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -110,7 +110,6 @@ select VBOOT_SEPARATE_VERSTAGE select VBOOT select VBOOT_STARTS_IN_BOOTBLOCK - select VBOOT_SOFT_REBOOT_WORKAROUND select VBOOT_VBNV_CMOS help Perform a verified boot using the TPM on the Crypto Shield board. diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index d6d74ca..e3b8aa6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -174,10 +174,6 @@ Set this option to indicate to vboot that recovery data hash space is present in TPM. -config VBOOT_SOFT_REBOOT_WORKAROUND - bool - default n - config VBOOT_LID_SWITCH bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I417a2ff45b4a8f5bc800459a64f1c5a861fcd3d5 Gerrit-Change-Number: 36605 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/emulation/qemu: Add VBOOT support
by Patrick Rudolph (Code Review) 06 Nov '19

06 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35400 ) Change subject: mb/emulation/qemu: Add VBOOT support ...................................................................... mb/emulation/qemu: Add VBOOT support Add VBOOT support for testing purposes. Add a 16 MiB FMAP containing RO + RW_A. Tested on qemu. Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/cmos.layout A src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/cmos.layout A src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd 6 files changed, 81 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35400/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c5e325..4074fef 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,6 +12,22 @@ select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + + +config VBOOT_SLOTS_RW_A + default y + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_VBNV_OFFSET + hex + default 0x2c config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index b238a37..247a6a0 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -7,6 +7,10 @@ 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd new file mode 100644 index 0000000..aa081b2 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO 0x7ff000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS)@0x20000 0x7df000 + } + } +} diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index bfa38ed..811630c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,6 +11,21 @@ select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2c config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index b238a37..247a6a0 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -7,6 +7,10 @@ 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd new file mode 100644 index 0000000..aa081b2 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO 0x7ff000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS)@0x20000 0x7df000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Gerrit-Change-Number: 35400 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/so… File src/mainboard/solidrun/solidpc/com_init.c: https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/so… PS12, Line 26: : uint32_t *pad_config_reg; : : /* Enable the UART hardware for COM1. */ : pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 1); : : /* : * Set up the pads to select the UART function : * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD : * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD : */ : pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); : write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, : M2)); : : pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); : write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, : M2)); > No braswell board in coreboot except SolidPC uses it, however I agree it can be moved out to soc/braswell Both google/cyan and google/strago have the same code and the same meaningless Kconfig option ENABLE_BUILTIN_COM1. So it would make a lot of sense to move it there. However I don't think ENABLE_BUILTIN_COM1 is a good Kconfig. Pads should not be configured based on user selectable Kconfig options, so better call it MB_HAS_BUILTIN_COM1 or something like that. -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 06 Nov 2019 13:29:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/solidrun/solidpc: Do initial commit
by Michał Żygowski (Code Review) 06 Nov '19

06 Nov '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23027 ) Change subject: mb/solidrun/solidpc: Do initial commit ...................................................................... Patch Set 12: (2 comments) https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/so… File src/mainboard/solidrun/solidpc/Kconfig: https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/so… PS12, Line 6: ENABLE_BUILTIN_COM1 > Not used on braswell (but should be implemented like on ~baytrail) This is actually built-in serial port in the LPC, present on braswell and used on this board. The name is not misleading in any way. Can move the implementation out of mainboard directory as mentioned in other comment. https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/so… File src/mainboard/solidrun/solidpc/com_init.c: https://review.coreboot.org/c/coreboot/+/23027/12/src/mainboard/solidrun/so… PS12, Line 26: : uint32_t *pad_config_reg; : : /* Enable the UART hardware for COM1. */ : pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 1); : : /* : * Set up the pads to select the UART function : * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD : * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD : */ : pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); : write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, : M2)); : : pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); : write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, : M2)); > This should probably not be in the MB dir. No braswell board in coreboot except SolidPC uses it, however I agree it can be moved out to soc/braswell -- To view, visit https://review.coreboot.org/c/coreboot/+/23027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ff95313d74091e7411f6c8658d0d560a0e682b Gerrit-Change-Number: 23027 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 06 Nov 2019 13:23:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Copy acpi directory from icelake
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36553 ) Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ...................................................................... Patch Set 2: (8 comments) https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 41: remove space https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 226: : Name (EP_B, 0) /* to store EP BAR */ : Name (MH_B, 0) /* to store MCH BAR */ : Name (PC_B, 0) /* to store PCIe BAR */ : Name (PC_L, 0) /* to store PCIe BAR Length */ : Name (DM_B, 0) /* to store DMI BAR Why cache it? https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 236: If (LEqual (MH_B, 0)) { : ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) : } use new syntax. Same applies to all files in this CL btw. https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 310: LASH range memory mapped part of FLASH https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 311: FIOH Is it referenced somewhere? You can maybe drop it? It's not really a PCI resource either? https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 314: LIOH not referenced? https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 323: Store (\_SB.PCI0.GMHB (), MBR0) Are those functions necessary? Just do 'MBR0 = \_SB.PCI0.MCHC.MHBR << 15 https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/scs.asl: https://review.coreboot.org/c/coreboot/+/36553/2/src/soc/intel/tigerlake/ac… PS2, Line 26: ^PCRA use absolute references? -- To view, visit https://review.coreboot.org/c/coreboot/+/36553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Gerrit-Change-Number: 36553 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Nov 2019 13:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Copy acpi directory from icelake
by Subrata Banik (Code Review) 06 Nov '19

06 Nov '19

Hello Raj Astekar, Aaron Durbin, Patrick Rudolph, Angel Pons, Arthur Heymans, Ravishankar Sarawadi, build bot (Jenkins), Nico Huber, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36553 to look at the new patch set (#2). Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ...................................................................... soc/intel/tigerlake/acpi: Copy acpi directory from icelake Clone entirely from Icelake Tiger Lake specific changes will follow in subsequent patches. 1. Modify IP/Controller B:D:F as applicable as per TGP PCH "The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware." Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/pch_glan.asl A src/soc/intel/tigerlake/acpi/pch_hda.asl A src/soc/intel/tigerlake/acpi/pci_irqs.asl A src/soc/intel/tigerlake/acpi/pcie.asl A src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/scs.asl A src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/smbus.asl A src/soc/intel/tigerlake/acpi/southbridge.asl A src/soc/intel/tigerlake/acpi/xhci.asl 12 files changed, 1,507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/36553/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Gerrit-Change-Number: 36553 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake/acpi: Copy acpi directory from icelake
by Subrata Banik (Code Review) 06 Nov '19

06 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36553 ) Change subject: soc/intel/tigerlake/acpi: Copy acpi directory from icelake ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/c/coreboot/+/36553/1/src/soc/intel/tigerlake/ac… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/36553/1/src/soc/intel/tigerlake/ac… PS1, Line 40: ^ > This makes this hard to read, I'd have to look up the scope where this is defined and find this obje […] Done https://review.coreboot.org/c/coreboot/+/36553/1/src/soc/intel/tigerlake/ac… PS1, Line 85: LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_A23) > @Arthur, need your view here as well Done https://review.coreboot.org/c/coreboot/+/36553/1/src/soc/intel/tigerlake/ac… PS1, Line 87: Store (PID_GPIOCOM0, Local0) > same as above ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Gerrit-Change-Number: 36553 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 06 Nov 2019 12:48:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit November 2019