Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
hatch: Create puff variant
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus.
BUG=b:141658115 TEST=util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36452/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e339693..8488762 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -93,6 +93,7 @@ default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Puff" if BOARD_GOOGLE_PUFF
config MAINBOARD_VENDOR string @@ -118,6 +119,7 @@ default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "puff" if BOARD_GOOGLE_PUFF
config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 160194b..2051e0f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -32,3 +32,9 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c new file mode 100644 index 0000000..baefcf2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* E23 : TP1 */ + PAD_NC(GPP_E23, NONE), + /* H17 : TP2 */ + PAD_NC(GPP_H17, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb new file mode 100644 index 0000000..d82030d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "name" = ""PS175"" + register "desc" = ""PCON PS175"" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" + register "has_power_resource" = "1" + device i2c 15 on end # ????? + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/generic + register "name" = ""RTD21"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end # ????? + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36452
to look at the new patch set (#3).
Change subject: hatch: Create puff variant ......................................................................
hatch: Create puff variant
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus.
BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36452/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
Patch Set 4:
(14 comments)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/gpio.c:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 16: #include <arch/acpi.h> Is this required?
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 25: override_gpio_table nit: This is not required since there is already a weak implementation provided by baseboard.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 41: /* E23 : TP1 */ : PAD_NC(GPP_E23, NONE), : /* H17 : TP2 */ : PAD_NC(GPP_H17, NONE), Do you need to configure the TPs in bootblock?
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 65: /* F2 : MEM_CH_SEL */ : PAD_CFG_GPI(GPP_F2, NONE, PLTRST), This is not required.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 17: baseboard/ec.h Not everything from baseboard/ec.h applies to Puff. You can fix it later, but it would be good to have a bug to capture that.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 19: baseboard/gpio.h I am assuming you ensured everything in baseboard/gpio.h applies to Puff.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 4: PchSerialIoPci PchSerialIoDisabled? since it looks like you are disabling I2C0 below.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 5: PchSerialIoPci PchSerialIoDisabled? since it looks like you are disabling I2C1 below.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 18: # VR Slew rate setting : register "AcousticNoiseMitigation" = "1" : register "SlowSlewRateForIa" = "2" : register "SlowSlewRateForGt" = "2" : register "SlowSlewRateForSa" = "2" : register "FastPkgCRampDisableIa" = "1" : register "FastPkgCRampDisableGt" = "1" : register "FastPkgCRampDisableSa" = "1" These can be skipped for now. Those can be added if really required.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 47: .rise_time_ns = 0, : .fall_time_ns = 0, nit: You can set these later when/if required rather than setting to 0 explicitly.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 76: chip drivers/i2c/generic hid is a required field: https://review.coreboot.org/cgit/coreboot.git/tree/src/drivers/i2c/generic/c...
If you are unsure of the hid right now, you can skip adding this node for now and re-visit it later when support for some kernel driver needs to be enabled. For now, you can leave it as:
device pci 15.2 on end
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 82: # ????? Was there supposed to be a comment?
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 85: 15.3 Same comment as above.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 107: chip drivers/spi/acpi : register "name" = ""CRFP"" : register "hid" = "ACPI_DT_NAMESPACE_HID" : register "uid" = "1" : register "compat_string" = ""google,cros-ec-spi"" : register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" : register "wake" = "GPE0_DW0_23" : device spi 1 on end : end # FPMCU I don't think this is correct for Puff as per schematics.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 3: * While you're addressing Furquan's comments can you add
Copyright 2019 Google LLC
:)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 3: * Same here
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
Patch Set 5:
(16 comments)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/gpio.c:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 16: #include <arch/acpi.h>
Is this required?
Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 25: override_gpio_table
nit: This is not required since there is already a weak implementation provided by baseboard.
Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 41: /* E23 : TP1 */ : PAD_NC(GPP_E23, NONE), : /* H17 : TP2 */ : PAD_NC(GPP_H17, NONE),
Do you need to configure the TPs in bootblock?
I wasn't sure so I just included them however I removed them now which seems to be your advice here if I am not mistaken?
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 65: /* F2 : MEM_CH_SEL */ : PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
This is not required.
I only added it as it is specified on the Puff schematic however I shall drop it for now since we don't actually use it so lets keep the initial code simple.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 3: *
While you're addressing Furquan's comments can you add […]
We should probably not even bother having this header here as I don't think we can copyright a #include declaration :)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 3: *
Same here
Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 17: baseboard/ec.h
Not everything from baseboard/ec.h applies to Puff. […]
Ack
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 19: baseboard/gpio.h
I am assuming you ensured everything in baseboard/gpio.h applies to Puff.
For the moment yes.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 4: PchSerialIoPci
PchSerialIoDisabled? since it looks like you are disabling I2C0 below.
Ah I see, Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 5: PchSerialIoPci
PchSerialIoDisabled? since it looks like you are disabling I2C1 below.
Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 18: # VR Slew rate setting : register "AcousticNoiseMitigation" = "1" : register "SlowSlewRateForIa" = "2" : register "SlowSlewRateForGt" = "2" : register "SlowSlewRateForSa" = "2" : register "FastPkgCRampDisableIa" = "1" : register "FastPkgCRampDisableGt" = "1" : register "FastPkgCRampDisableSa" = "1"
These can be skipped for now. Those can be added if really required.
Ack, removed from this patch for now.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 47: .rise_time_ns = 0, : .fall_time_ns = 0,
nit: You can set these later when/if required rather than setting to 0 explicitly.
Seems harmless to be explicit and serves as a clear reminder how and were these need to be adjusted going forwards during bring up no?
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 76: chip drivers/i2c/generic
hid is a required field: https://review.coreboot.org/cgit/coreboot. […]
Yep ok, I commented out these blocks for now. I want to investigate once hardware is in my hands as coreboot will tell me stuff once I see the uart light up..
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 82: # ?????
Was there supposed to be a comment?
Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 85: 15.3
Same comment as above.
ditto, Done
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 107: chip drivers/spi/acpi : register "name" = ""CRFP"" : register "hid" = "ACPI_DT_NAMESPACE_HID" : register "uid" = "1" : register "compat_string" = ""google,cros-ec-spi"" : register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" : register "wake" = "GPE0_DW0_23" : device spi 1 on end : end # FPMCU
I don't think this is correct for Puff as per schematics.
I dropped it. Not important for booting proto.
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36452
to look at the new patch set (#6).
Change subject: hatch: Create puff variant ......................................................................
hatch: Create puff variant
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus.
V.2: Rework devicetree with comments and drop some useless gpio maps.
BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 227 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36452/6
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36452
to look at the new patch set (#7).
Change subject: hatch: Create puff variant ......................................................................
hatch: Create puff variant
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus.
V.2: Rework devicetree with comments and drop some useless gpio maps.
BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 223 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36452/7
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
Patch Set 7: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/gpio.c:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 41: /* E23 : TP1 */ : PAD_NC(GPP_E23, NONE), : /* H17 : TP2 */ : PAD_NC(GPP_H17, NONE),
I wasn't sure so I just included them however I removed them now which seems to be your advice here […]
That's right. In general, early_gpio_table[] is used to configure any pads that are: 1. Used by stages before getting to ramstage(which initializes everything including not-connected pads) 2. Controlling device power/reset which needs to be enabled/deasserted early on in the boot process.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 47: .rise_time_ns = 0, : .fall_time_ns = 0,
Seems harmless to be explicit and serves as a clear reminder how and were these need to be adjusted […]
Okay. SG.
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 76: chip drivers/i2c/generic
Yep ok, I commented out these blocks for now. […]
nit: You can just remove it and add it when really required. Upto you.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/gpio.c:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 41: /* E23 : TP1 */ : PAD_NC(GPP_E23, NONE), : /* H17 : TP2 */ : PAD_NC(GPP_H17, NONE),
That's right. In general, early_gpio_table[] is used to configure any pads that are: […]
Ack
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 47: .rise_time_ns = 0, : .fall_time_ns = 0,
Okay. SG.
Ack
https://review.coreboot.org/c/coreboot/+/36452/4/src/mainboard/google/hatch/... PS4, Line 76: chip drivers/i2c/generic
nit: You can just remove it and add it when really required. Upto you.
Ack, I'll leave for now until I see the thing boot and include dealing with this as part of the clean ups.
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36452 )
Change subject: hatch: Create puff variant ......................................................................
hatch: Create puff variant
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus.
V.2: Rework devicetree with comments and drop some useless gpio maps.
BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan quasisec@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 223 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e339693..8488762 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -93,6 +93,7 @@ default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Puff" if BOARD_GOOGLE_PUFF
config MAINBOARD_VENDOR string @@ -118,6 +119,7 @@ default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "puff" if BOARD_GOOGLE_PUFF
config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 160194b..2051e0f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -32,3 +32,9 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c new file mode 100644 index 0000000..b8b54d3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2c44a82 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1 @@ +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb new file mode 100644 index 0000000..d5e2e5a --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -0,0 +1,100 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on +# chip drivers/i2c/generic +# register "name" = ""PS175"" +# register "desc" = ""PCON PS175"" +# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" +# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" +# register "has_power_resource" = "1" +# device i2c 15 on end +# end + end # I2C #2 + device pci 15.3 on +# chip drivers/i2c/generic +# register "name" = ""RTD21"" +# register "desc" = ""Realtek RTD2142"" +# device i2c 4a on end +# end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 off end # GSPI #1 + end + +end
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Edward O'Callaghan (Code Review) -
Furquan Shaikh (Code Review)
-
Shelley Chen (Code Review)