coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7180: Add USB support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35503 ) Change subject: sc7180: Add USB support ...................................................................... sc7180: Add USB support This includes USB QUSB2,QMP Phy and Controller support And libpayload support for USB Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995 Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M payloads/libpayload/configs/config.trogdor M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/trogdor/romstage.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7180/include/soc/clock.h A src/soc/qualcomm/sc7180/include/soc/efuse.h A src/soc/qualcomm/sc7180/include/soc/usb.h A src/soc/qualcomm/sc7180/usb.c 9 files changed, 931 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35503/1 diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor index 0625ff5..7ca654b 100644 --- a/payloads/libpayload/configs/config.trogdor +++ b/payloads/libpayload/configs/config.trogdor @@ -3,3 +3,6 @@ CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_SC7180_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index dbdb4ed..170955a 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -19,10 +19,23 @@ #include <gpio.h> #include <timestamp.h> #include <soc/qupv3_fw_config.h> +#include <soc/usb.h> + +static struct usb_board_data usb0_board_data = { + .pll_bias_control_2 = 0x22, + .imp_ctrl1 = 0x08, + .port_tune1 = 0xc5, +}; + +static void setup_usb(void) +{ + setup_usb_host0(&usb0_board_data); +} static void mainboard_init(struct device *dev) { qupv3_fw_init(); + setup_usb(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index 7185387..872798a 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -14,10 +14,22 @@ */ #include <arch/stages.h> +#include <soc/usb.h> #include <soc/qclib_common.h> +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { + prepare_usb(); + /* QCLib: DDR init & train */ qclib_load_and_run(); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index d8fc33a..8db260d 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -28,6 +28,8 @@ romstage-y += timer.c romstage-y += gpio.c romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += usb.c romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c @@ -49,6 +51,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c +ramstage-y += usb.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 1a24d94..ae6bb6b 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -46,4 +46,16 @@ #define QUP_SERIAL10_BASE 0xA90000 #define QUP_SERIAL11_BASE 0xA94000 +/* + * USB BASE ADDRESSES + */ +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e3000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define USB_HOST_DWC3_BASE 0x0a60c100 + #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index d90779b..ae9abd2 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -76,7 +76,7 @@ struct sc7180_gpll gpll0; u8 _res0[0xf000 - 0x1000]; u32 usb30_prim_bcr; - u8 _res3[0x17000 - 0xf004]; + u8 _res1[0x17000 - 0xf004]; u32 qup_wrap0_bcr; u32 qup_wrap0_m_ahb_cbcr; u32 qup_wrap0_s_ahb_cbcr; @@ -84,33 +84,39 @@ u32 qup_wrap0_core_cdivr; u32 qup_wrap0_core_2x_cbcr; struct sc7180_rcg qup_wrap0_core_2x; - u8 _res4[0x17030 - 0x17020]; + u8 _res2[0x17030 - 0x17020]; struct sc7180_qupv3_clock qup_wrap0_s[6]; - u8 _res5[0x18000 - 0x17750]; + u8 _res3[0x18000 - 0x17750]; u32 qup_wrap1_bcr; u32 qup_wrap1_core_2x_cbcr; u32 qup_wrap1_core_cbcr; u32 qup_wrap1_m_ahb_cbcr; u32 qup_wrap1_s_ahb_cbcr; struct sc7180_qupv3_clock qup_wrap1_s[6]; - u8 _res6[0x18994 - 0x18734]; + u8 _res4[0x18994-0x18734]; u32 qup_wrap1_core_cdivr; - u8 _res7[0x4b000 - 0x18998]; + u8 _res5[0x26000-0x18998]; + u32 qusb2phy_prim_bcr; + u8 _res6[0x4B000 - 0x26004]; u32 qspi_bcr; u32 qspi_cnoc_ahb_cbcr; u32 qspi_core_cbcr; struct sc7180_rcg qspi_core; - u8 _res8[0x50000 - 0x4b014]; + u8 _res7[0x50000-0x4b014]; u32 usb3_phy_prim_bcr; u32 usb3phy_phy_prim_bcr; u32 usb3_dp_phy_prim_bcr; u32 usb3_phy_sec_bcr; u32 usb3phy_phy_sec_bcr; u32 usb3_dp_phy_sec_bcr; - u8 _res9[0x52008 - 0x50018]; + u8 _res8[0x52008-0x50018]; u32 apcs_clk_br_en1; - u8 _res10[0x1000000 - 0x5200c]; + u8 _res9[0x1000000-0x5200c]; }; +check_member(sc7180_gcc, usb30_prim_bcr, 0xf000); +check_member(sc7180_gcc, qusb2phy_prim_bcr, 0x26000); +check_member(sc7180_gcc, usb3phy_phy_prim_bcr, 0x50004); +check_member(sc7180_gcc, usb3_phy_prim_bcr, 0x50000); struct sc7180_aoss { u8 _res[0x5002c]; diff --git a/src/soc/qualcomm/sc7180/include/soc/efuse.h b/src/soc/qualcomm/sc7180/include/soc/efuse.h new file mode 100644 index 0000000..baaa971 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/efuse.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ + +/** + * USB EFUSE registers + */ +struct qfprom_corr { + u8 rsvd[0x4258 - 0x0]; + u32 qusb_hstx_trim_lsb; +}; +check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x4258); + +#endif /* __SOC_QUALCOMM_SC7180_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h new file mode 100644 index 0000000..3a8816a --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/usb.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <types.h> + +#ifndef _SC7180_USB_H_ +#define _SC7180_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x08 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0xc5 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x30 + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +void setup_usb_host0(struct usb_board_data *data); + +/* Call reset_ before setup_ */ +void reset_usb0(void); + + +#endif /* _SC7180_USB_H_ */ diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c new file mode 100644 index 0000000..7c65830 --- /dev/null +++ b/src/soc/qualcomm/sc7180/usb.c @@ -0,0 +1,750 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <stdlib.h> +#include <console/console.h> +#include <delay.h> +#include <soc/usb.h> +#include <soc/clock.h> +#include <soc/addressmap.h> +#include <soc/efuse.h> +#include <timer.h> + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +/* Only for QMP V3 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1; + u32 com_ssc_step_size2; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[20]; + u32 com_cp_ctrl_mode0; + u8 _reserved4[4]; + u32 com_pll_rctrl_mode0; + u8 _reserved5[4]; + u32 com_pll_cctrl_mode0; + u8 _reserved6[12]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u8 _reserved8[12]; + u32 com_dec_start_mode0; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u8 _reserved10[20]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[16]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u8 _reserved12[60]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[8]; + u32 com_coreclk_div_mode0; + u8 _reserved14[8]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; +}; +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); + +/* Only for QMP V3 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[68]; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[20]; + u32 tx_highz_drvr_en; + u8 _reserved3[40]; + u32 tx_lane_mode_1; + u8 _reserved4[20]; + u32 tx_rcv_detect_lvl_2; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); + +/* Only for QMP V3 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[8]; + u32 rx_ucdr_fo_gain; + u32 rx_ucdr_so_gain_half; + u8 _reserved2[32]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturtn_and_en; + u8 _reserved3[12]; + u32 rx_ucdr_pi_cntrls; + u8 _reserved4[120]; + u32 rx_vga_cal_ctrl2; + u8 _reserved5[16]; + u32 rx_rx_equ_adap_ctrl2; + u32 rx_rx_equ_adap_ctrl3; + u32 rx_rx_equ_adap_ctrl4; + u8 _reserved6[24]; + u32 rx_rx_eq_offset_adap_ctrl1; + u32 rx_rx_offset_adap_ctrl2; + u32 rx_sigdet_enables; + u32 rx_sigdet_ctrl; + u8 _reserved7[4]; + u32 rx_sigdet_deglitch_ctrl; + u32 rx_rx_band; + u8 _reserved8[80]; + u32 rx_rx_mode_00; +}; +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); + +/* Only for QMP V3 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u32 pcs_power_down_control; + u32 pcs_start_control; + u32 pcs_txmgn_v0; + u32 pcs_txmgn_v1; + u32 pcs_txmgn_v2; + u32 pcs_txmgn_v3; + u32 pcs_txmgn_v4; + u32 pcs_txmgn_ls; + u32 pcs_txdeemph_m6db_v0; + u32 pcs_txdeemph_m3p5db_v0; + u32 pcs_txdeemph_m6db_v1; + u32 pcs_txdeemph_m3p5db_v1; + u32 pcs_txdeemph_m6db_v2; + u32 pcs_txdeemph_m3p5db_v2; + u32 pcs_txdeemph_m6db_v3; + u32 pcs_txdeemph_m3p5db_v3; + u32 pcs_txdeemph_m6db_v4; + u32 pcs_txdeemph_m3p5db_v4; + u32 pcs_txdeemph_m6db_ls; + u32 pcs_txdeemph_m3p5db_ls; + u8 _reserved1[8]; + u32 pcs_rate_slew_cntrl; + u8 _reserved2[4]; + u32 pcs_power_state_config2; + u8 _reserved3[8]; + u32 pcs_rcvr_dtct_dly_p1u2_l; + u32 pcs_rcvr_dtct_dly_p1u2_h; + u32 pcs_rcvr_dtct_dly_u3_l; + u32 pcs_rcvr_dtct_dly_u3_h; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u32 pcs_tsync_rsync_time; + u8 _reserved4[16]; + u32 pcs_pwrup_reset_dly_time_auxclk; + u8 _reserved5[12]; + u32 pcs_lfps_ecstart_eqtlock; + u8 _reserved6[4]; + u32 pcs_rxeqtraining_wait_time; + u32 pcs_rxeqtraining_run_time; + u8 _reserved7[4]; + u32 pcs_fll_ctrl1; + u32 pcs_fll_ctrl2; + u32 pcs_fll_cnt_val_l; + u32 pcs_fll_cnt_val_h_tol; + u32 pcs_fll_man_code; + u32 pcs_autonomous_mode_ctrl; + u8 _reserved8[152]; + u32 pcs_ready_status; + u8 _reserved9[96]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved10[48]; + u32 pcs_refgen_req_config1; + u32 pcs_refgen_req_config2; +}; +check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); +check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); +check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); +check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); +check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); +check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); +check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); +check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; + + + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[124]; + u32 usb2phyacc; + u8 reserved4[60]; + u32 usb3pipectl; + u8 reserved5[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, + {&qserdes_com_reg_layout->com_clk_select, 0x30}, + {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&qserdes_com_reg_layout->com_cmn_config, 0x16}, + {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, + {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, + {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, + {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, +}; + + + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_qusb_phy_pll *qusb_phy_pll; + struct usb_qusb_phy_dig *qusb_phy_dig; + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; + + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; + struct usb_board_data *board_data; + u32 efuse_offset; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, + .efuse_offset = 25, +}; + + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert QUSB PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + + +/* + * Update board specific PHY tuning override values that specified from + * board file. + */ +static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + /* Override preemphasis value */ + write32(&dwc3->qusb_phy_dig->tune1, + dwc3->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + dwc3->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&dwc3->qusb_phy_dig->imp_ctrl1, + dwc3->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ +static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) +{ + /* + * Efuse registers 3 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 3 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 3; + int bit_pos = dwc3->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) +{ + write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); + write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); + + if (dwc3->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(dwc3); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(dwc3); + } +} + +static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* PWR_CTRL: set the power down bit to disable the PHY */ + setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&dwc3->qusb_phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&dwc3->qusb_phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&dwc3->qusb_phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&dwc3->qusb_phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&dwc3->qusb_phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(dwc3, dwc3->qusb_phy_dig); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* power up USB3 PHY */ + write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); + qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); + qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(1000, + !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits_le32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + struct usb_board_data *board_data) +{ + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize QUSB PHY */ + hs_qusb_phy_init(dwc3); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(dwc3); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} + +void setup_usb_host0(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} + + -- To view, visit https://review.coreboot.org/c/coreboot/+/35503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995 Gerrit-Change-Number: 35503 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: sc7180: Add AOP firmware support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35502 to review the following change. Change subject: sc7180: Add AOP firmware support ...................................................................... sc7180: Add AOP firmware support Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85 Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 89 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7ad0328..d8fc33a 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c +ramstage-y += aop_load_reset.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c new file mode 100644 index 0000000..8d22d62 --- /dev/null +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/aop.h> +#include <soc/clock.h> + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h new file mode 100644 index 0000000..5573163 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ +#define _SOC_QUALCOMM_SC7180_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index ae00816..f4e6f05 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -24,8 +24,24 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr) +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +/* AOPMSG : 0x0C300000 - 0x0C400000 */ +#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) +#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + AOPMSG_START(0x0C300000) + REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) + AOPMSG_END(0x0C400000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 14b779f..893ecc3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -26,5 +26,7 @@ DECLARE_REGION(dcb); DECLARE_REGION(pmic); DECLARE_REGION(limits_cfg); +DECLARE_REGION(aop); +DECLARE_REGION(aop_ss_msg_ram_drv15); #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index fd59a5a..2eb8c86 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -33,3 +33,7 @@ mmu_enable(); } +void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 4fc5b30..7039935 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -18,6 +18,7 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> +#include <soc/aop.h> static void soc_read_resources(struct device *dev) { @@ -34,7 +35,7 @@ static void soc_init(struct device *dev) { - + aop_fw_load_reset(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/35502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Gerrit-Change-Number: 35502 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: sc7180: Add SPI-NOR support
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35501 ) Change subject: sc7180: Add SPI-NOR support ...................................................................... sc7180: Add SPI-NOR support This implements the SPI-NOR driver for the Qualcomm QSPI core. Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/include/soc/qspi.h A src/soc/qualcomm/sc7180/qspi.c M src/soc/qualcomm/sc7180/spi.c 6 files changed, 452 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35501/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index a1a7f03..df5d116 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -28,4 +28,13 @@ help Select the QUP instance to be used for UART console output. +config SC7180_QSPI + bool + default y if COMMON_CBFS_SPI_WRAPPER + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 16 + endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 5a4b68c..7ad0328 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += qupv3_fw_config.c bootblock-y += qupv3_config.c bootblock-y += qcom_qup_se.c +bootblock-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ verstage-y += timer.c @@ -20,6 +21,7 @@ verstage-y += clock.c verstage-y += qcom_qup_se.c verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ romstage-y += cbmem.c @@ -32,6 +34,7 @@ romstage-y += clock.c romstage-y += qcom_qup_se.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ ramstage-y += soc.c @@ -44,6 +47,7 @@ ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b0cd9f2..8ee04d2 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -18,10 +18,12 @@ #include <soc/mmu.h> #include <soc/clock.h> #include <soc/qupv3_fw_config.h> +#include <soc/qspi.h> void bootblock_soc_init(void) { sc7180_mmu_init(); clock_init(); + quadspi_init(25 * MHz); qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7180/include/soc/qspi.h b/src/soc/qualcomm/sc7180/include/soc/qspi.h new file mode 100644 index 0000000..c3d1f78 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qspi.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Technologies. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <types.h> +#include <soc/addressmap.h> +#include <spi-generic.h> + +#ifndef __SOC_QUALCOMM_SC7180_QSPI_H__ +#define __SOC_QUALCOMM_SC7180_QSPI_H__ + +struct sc7180_qspi_regs { + u32 mstr_cfg; + u32 ahb_mstr_cfg; + u32 reserve_0; + u32 mstr_int_en; + u32 mstr_int_sts; + u32 pio_xfer_ctrl; + u32 pio_xfer_cfg; + u32 pio_xfer_sts; + u32 pio_dataout_1byte; + u32 pio_dataout_4byte; + u32 rd_fifo_cfg; + u32 rd_fifo_sts; + u32 rd_fifo_rst; + u32 reserve_1[3]; + u32 next_dma_desc_addr; + u32 current_dma_desc_addr; + u32 current_mem_addr; + u32 hw_version; + u32 rd_fifo[16]; +}; + +check_member(sc7180_qspi_regs, rd_fifo, 0x50); +static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE; + +// MSTR_CONFIG register + +#define TX_DATA_OE_DELAY_SHIFT 24 +#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) +#define TX_CS_N_DELAY_SHIFT 22 +#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) +#define TX_CLK_DELAY_SHIFT 20 +#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) +#define TX_DATA_DELAY_SHIFT 18 +#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) +#define LPA_BASE_SHIFT 14 +#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) +#define SBL_EN BIT(13) +#define CHIP_SELECT_NUM BIT(12) +#define SPI_MODE_SHIFT 10 +#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) +#define BIG_ENDIAN_MODE BIT(9) +#define DMA_ENABLE BIT(8) +#define PIN_WPN BIT(7) +#define PIN_HOLDN BIT(6) +#define FB_CLK_EN BIT(4) +#define FULL_CYCLE_MODE BIT(3) + +// MSTR_INT_ENABLE and MSTR_INT_STATUS register + +#define DMA_CHAIN_DONE BIT(31) +#define TRANSACTION_DONE BIT(16) +#define WRITE_FIFO_OVERRUN BIT(11) +#define WRITE_FIFO_FULL BIT(10) +#define HRESP_FROM_NOC_ERR BIT(3) +#define RESP_FIFO_RDY BIT(2) +#define RESP_FIFO_NOT_EMPTY BIT(1) +#define RESP_FIFO_UNDERRUN BIT(0) + +// PIO_TRANSFER_CONFIG register + +#define TRANSFER_FRAGMENT BIT(8) +#define MULTI_IO_MODE_SHIFT 1 +#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) +#define TRANSFER_DIRECTION BIT(0) + +// PIO_TRANSFER_STATUS register + +#define WR_FIFO_BYTES_SHIFT 16 +#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) + +// RD_FIFO_CONFIG register + +#define CONTINUOUS_MODE BIT(0) + +// RD_FIFO_STATUS register + +#define FIFO_EMPTY BIT(11) +#define WR_CNTS_SHIFT 4 +#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) +#define RDY_64BYTE BIT(3) +#define RDY_32BYTE BIT(2) +#define RDY_16BYTE BIT(1) +#define FIFO_RDY BIT(0) + +// RD_FIFO_RESET register + +#define RESET_FIFO BIT(0) + +#define QSPI_MAX_PACKET_COUNT 0xFFC0 + +void quadspi_init(uint32_t hz); +int sc7180_claim_bus(const struct spi_slave *slave); +int sc7180_setup_bus(const struct spi_slave *slave); +void sc7180_release_bus(const struct spi_slave *slave); +int sc7180_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +#endif /* __SOC_QUALCOMM_SC7180_QSPI_H__ */ diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c new file mode 100644 index 0000000..c589415 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <arch/cache.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/qspi.h> +#include <soc/gpio.h> +#include <soc/clock.h> +#include <symbols.h> +#include <assert.h> +#include <gpio.h> +#include <string.h> + +#define CACHE_LINE_SIZE 64 + +static int curr_desc_idx = -1; + +struct cmd_desc { + uint32_t data_address; + uint32_t next_descriptor; + uint32_t direction:1; + uint32_t multi_io_mode:3; + uint32_t reserved1:4; + uint32_t fragment:1; + uint32_t reserved2:7; + uint32_t length:16; + //------------------------// + uint32_t bounce_src; + uint32_t bounce_dst; + uint32_t bounce_length; + uint64_t padding[5]; +}; + +enum qspi_mode { + SDR_1BIT = 1, + SDR_2BIT = 2, + SDR_4BIT = 3, + DDR_1BIT = 5, + DDR_2BIT = 6, + DDR_4BIT = 7, +}; + +enum cs_state { + CS_DEASSERT, + CS_ASSERT +}; + +struct xfer_cfg { + enum qspi_mode mode; +}; + +enum bus_xfer_direction { + MASTER_READ = 0, + MASTER_WRITE = 1, +}; + +struct { + struct cmd_desc descriptors[3]; + uint8_t buffers[3][CACHE_LINE_SIZE]; +} *dma = (void *)_dma_coherent; + +static void dma_transfer_chain(struct cmd_desc *chain) +{ + uint32_t mstr_int_status; + + write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + + while (1) { + mstr_int_status = read32(&sc7180_qspi->mstr_int_sts); + if (mstr_int_status & DMA_CHAIN_DONE) + break; + } +} + +static void flush_chain(void) +{ + struct cmd_desc *desc = &dma->descriptors[0]; + uint8_t *src; + uint8_t *dst; + + dma_transfer_chain(desc); + + while (desc) { + if (desc->direction == MASTER_READ) { + if (desc->bounce_length == 0) + dcache_invalidate_by_mva( + (void *)(uintptr_t) desc->data_address, + desc->length); + else { + src = (void *)(uintptr_t) desc->bounce_src; + dst = (void *)(uintptr_t) desc->bounce_dst; + memcpy(dst, src, desc->bounce_length); + } + } + desc = (void *)(uintptr_t) desc->next_descriptor; + } + curr_desc_idx = -1; +} + +static struct cmd_desc *allocate_descriptor(void) +{ + struct cmd_desc *current; + struct cmd_desc *next; + uint8_t index; + + current = (curr_desc_idx == -1) ? + NULL : &dma->descriptors[curr_desc_idx]; + + index = ++curr_desc_idx; + next = &dma->descriptors[index]; + + next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + + next->next_descriptor = 0; + next->direction = MASTER_READ; + next->multi_io_mode = 0; + next->reserved1 = 0; + next->fragment = 0; + next->reserved2 = 0; + next->length = 0; + next->bounce_src = 0; + next->bounce_dst = 0; + next->bounce_length = 0; + + if (current) { + current->next_descriptor = (uint32_t)(uintptr_t) next; + current->fragment = 1; + } + + return next; +} + +static void cs_change(enum cs_state state) +{ + gpio_set(GPIO(68), state == CS_DEASSERT); +} + +static void configure_gpios(void) +{ + gpio_output(GPIO(68), 1); + + gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); + + gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); + + gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); +} + +static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + uint8_t *ptr; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + ptr = (void *)(uintptr_t) desc->data_address; + + if (write) { + memcpy(ptr, data, data_bytes); + } else { + desc->bounce_src = (uint32_t)(uintptr_t) ptr; + desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_length = data_bytes; + } + + desc->length = data_bytes; +} + +static void queue_direct_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + desc->data_address = (uint32_t)(uintptr_t) data; + desc->length = data_bytes; + + if (write) + dcache_clean_by_mva(data, data_bytes); + else + dcache_invalidate_by_mva(data, data_bytes); +} + +static void queue_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + uint8_t *aligned_ptr; + uint8_t *epilog_ptr; + uint32_t prolog_bytes, aligned_bytes, epilog_bytes; + + if (data_bytes == 0) + return; + + aligned_ptr = + (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); + + prolog_bytes = MIN(data_bytes, aligned_ptr - data); + aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); + epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; + + epilog_ptr = data + prolog_bytes + aligned_bytes; + + if (prolog_bytes) + queue_bounce_data(data, prolog_bytes, data_mode, write); + if (aligned_bytes) + queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); + if (epilog_bytes) + queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); +} + +static void reg_init(void) +{ + uint32_t spi_mode; + uint32_t tx_data_oe_delay, tx_data_delay; + uint32_t mstr_config; + + spi_mode = 0; + + tx_data_oe_delay = 0; + tx_data_delay = 0; + + mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (spi_mode << SPI_MODE_SHIFT) | + (PIN_HOLDN) | + (FB_CLK_EN) | + (DMA_ENABLE) | + (FULL_CYCLE_MODE); + + write32(&sc7180_qspi->mstr_cfg, mstr_config); + write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42); + write32(&sc7180_qspi->mstr_int_en, 0x0); + write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7180_qspi->rd_fifo_cfg, 0x0); + write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO); +} + +void quadspi_init(uint32_t hz) +{ + assert(dcache_line_bytes() == CACHE_LINE_SIZE); + clock_configure_qspi(hz * 4); + configure_gpios(); + reg_init(); +} + +int sc7180_claim_bus(const struct spi_slave *slave) +{ + cs_change(CS_ASSERT); + return 0; +} + +void sc7180_release_bus(const struct spi_slave *slave) +{ + cs_change(CS_DEASSERT); +} + +static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, + void *din, size_t in_bytes) +{ + if ((out_bytes && !dout) || (in_bytes && !din) || + (in_bytes && out_bytes)) { + return -1; + } + + queue_data((uint8_t *) (out_bytes ? dout : din), + in_bytes | out_bytes, mode, !!out_bytes); + + flush_chain(); + + return 0; +} + +int sc7180_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); +} + +int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); +} diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index 5abb81a..c6d4cb1 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,12 +15,19 @@ #include <spi-generic.h> #include <spi_flash.h> +#include <soc/qspi.h> -static const struct spi_ctrlr spi_ctrlr; +static const struct spi_ctrlr qspi_ctrlr = { + .claim_bus = sc7180_claim_bus, + .release_bus = sc7180_release_bus, + .xfer = sc7180_xfer, + .xfer_dual = sc7180_xfer_dual, + .max_xfer_size = QSPI_MAX_PACKET_COUNT, +}; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { - .ctrlr = &spi_ctrlr, + .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Gerrit-Change-Number: 35501 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mb/asrock/h110m: fix bug with onboard LAN
by Maxim Polyakov (Code Review) 05 Dec '19

05 Dec '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36377 ) Change subject: mb/asrock/h110m: fix bug with onboard LAN ...................................................................... mb/asrock/h110m: fix bug with onboard LAN Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36377/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 4323028..8f64d02 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -219,10 +219,6 @@ # Enable Root port 6(x1) for LAN. register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" # Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism -- To view, visit https://review.coreboot.org/c/coreboot/+/36377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Gerrit-Change-Number: 36377 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: sc7180: Add clock driver
by mturney mturney (Code Review) 05 Dec '19

05 Dec '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35496 ) Change subject: sc7180: Add clock driver ...................................................................... sc7180: Add clock driver Add support for clock driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/31083/6 Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Signed-off-by: srimuc <srimuc(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/clock.h 5 files changed, 468 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35496/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a973724..60ad516 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -7,12 +7,14 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += spi.c +bootblock-y += clock.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ verstage-y += timer.c verstage-y += gpio.c verstage-y += spi.c +verstage-y += clock.c verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ @@ -23,6 +25,7 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c +romstage-y += clock.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ @@ -31,6 +34,7 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += spi.c +ramstage-y += clock.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b9b8660..f073449 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -14,9 +14,12 @@ */ #include <bootblock_common.h> +#include <soc/clock.h> #include <soc/mmu.h> +#include <soc/clock.h> void bootblock_soc_init(void) { sc7180_mmu_init(); + clock_init(); } diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c new file mode 100644 index 0000000..0ccbaa6 --- /dev/null +++ b/src/soc/qualcomm/sc7180/clock.c @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <types.h> + +#define DIV(div) (2 * div - 1) + +struct clock_config qup_cfg[] = { + { + .hz = 7372800, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 384, + .n = 15625, + .d_2 = 15625, + }, + { + .hz = 19200 * KHz, + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + } +}; + +struct clock_config qspi_core_cfg[] = { + { + .hz = 19200 * KHz, + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(3), + }, + { + .hz = 150 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(2), + }, + { + .hz = 300 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + } +}; + +static int clock_configure_gpll0(void) +{ + write32(&gcc->gpll0.user_ctl_u, 0x00004805); + + /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ + setbits_le32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + + return 0; +} + +static int clock_configure_mnd(struct sc7180_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + setbits_le32(&clk->rcg.cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&clk->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&clk->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return 0; +} + +static int clock_configure_rcg(struct sc7180_rcg *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->cfg, reg_val); + + /* Commit config to RCG */ + setbits_le32(&clk->cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static int clock_configure(struct sc7180_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg.cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return 0; +} + +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + /* Set clock vote bit */ + setbits_le32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +static int clock_enable(void *cbcr_addr) +{ + /* Set clock enable bit */ + setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (clock_is_off(cbcr_addr)) + ; + + return 0; +} + +void clock_reset_aop(void) +{ + /* Bring AOP out of RESET */ + clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure_rcg(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct sc7180_bcr *bcr = bcr_addr; + + if (reset) + setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + else + clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + + return 0; +} + +void clock_configure_qup(int qup, uint32_t hz) +{ + int s = qup % QUP_WRAP1_S0; + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + (struct sc7180_qupv3_clock *)&gcc->qup_wrap0_s[s] : + (struct sc7180_qupv3_clock *)&gcc->qup_wrap1_s[s]; + + clock_configure(&qup_clk->clk, qup_cfg, hz, ARRAY_SIZE(qup_cfg)); +} + +void clock_enable_qup(int qup) +{ + int s = qup % QUP_WRAP1_S0; + int clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_enable_vote(&qup_clk->clk, &gcc->apcs_clk_br_en1, + clk_en_off); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index 93f0481..308b2fb 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (c) 2018-2019 Qualcomm Technologies + * Copyright (c) 2019 Qualcomm Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,4 +18,8 @@ #include <stdint.h> -#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ +#define AOSS_CC_BASE 0x0C2A0000 +#define GCC_BASE 0x00100000 +#define QSPI_BASE 0x088DC000 + +#endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h new file mode 100644 index 0000000..d90779b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <types.h> + +#ifndef __SOC_QUALCOMM_SC7180_CLOCK_H__ +#define __SOC_QUALCOMM_SC7180_CLOCK_H__ + +#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 +#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 +#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 +#define QUPV3_WRAP0_CORE_CLK_ENA 8 +#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 +#define QUPV3_WRAP1_CORE_CLK_ENA 19 +#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 +#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) + +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) +#define QUP_WRAP_CORE_2X_19_2MHZ (19200 * KHz) + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_600MHZ 1 +#define SRC_GPLL0_EVEN_300MHZ 6 + +#define AOP_RESET_SHFT 0 +#define RCG_MODE_DUAL_EDGE 2 + +struct sc7180_rcg { + u32 cmd; + u32 cfg; +}; + +struct sc7180_clock { + u32 cbcr; + struct sc7180_rcg rcg; + u32 m; + u32 n; + u32 d_2; +}; + +struct sc7180_qupv3_clock { + struct sc7180_clock clk; + u8 _res[0x130 - 0x18]; +}; + +struct sc7180_gpll { + u32 mode; + u32 l_val; + u32 cal_l_val; + u32 user_ctl; + u32 user_ctl_u; + u32 config_ctl; + u32 config_ctl_u; + u32 test_ctl; + u32 test_ctl_u; + u8 _res[0x1000 - 0x24]; +}; + +struct sc7180_gcc { + struct sc7180_gpll gpll0; + u8 _res0[0xf000 - 0x1000]; + u32 usb30_prim_bcr; + u8 _res3[0x17000 - 0xf004]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + struct sc7180_rcg qup_wrap0_core_2x; + u8 _res4[0x17030 - 0x17020]; + struct sc7180_qupv3_clock qup_wrap0_s[6]; + u8 _res5[0x18000 - 0x17750]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_core_2x_cbcr; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct sc7180_qupv3_clock qup_wrap1_s[6]; + u8 _res6[0x18994 - 0x18734]; + u32 qup_wrap1_core_cdivr; + u8 _res7[0x4b000 - 0x18998]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct sc7180_rcg qspi_core; + u8 _res8[0x50000 - 0x4b014]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u32 usb3_phy_sec_bcr; + u32 usb3phy_phy_sec_bcr; + u32 usb3_dp_phy_sec_bcr; + u8 _res9[0x52008 - 0x50018]; + u32 apcs_clk_br_en1; + u8 _res10[0x1000000 - 0x5200c]; +}; + +struct sc7180_aoss { + u8 _res[0x5002c]; + u32 aoss_cc_apcs_misc; +}; + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, + CLK_CTL_BCR_BLK_ARES_SHFT = 0, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, +}; + +struct clock_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +struct mdss_clock_config { + const char *clk_name; + uintptr_t rcgr; + uintptr_t cbcr; +}; + +static struct sc7180_gcc *const gcc = (void *)GCC_BASE; +static struct sc7180_aoss *const aoss = (void *)AOSS_CC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +void clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_qup(int qup, uint32_t hz); +void clock_enable_qup(int qup); + +#endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/35496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Gerrit-Change-Number: 35496 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

5 21

Change in ...coreboot[master]: riscv: add smp support for exception handle
by Xiang Wang (Code Review) 04 Dec '19

04 Dec '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33656 Change subject: riscv: add smp support for exception handle ...................................................................... riscv: add smp support for exception handle Change-Id: I637b3b3047d2c0e12842499fe61f740d0daf489f Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/payload.c M src/arch/riscv/trap_util.S 2 files changed, 104 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33656/1 diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index f3ed5a4..cfb84f2 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -19,6 +19,7 @@ #include <arch/boot.h> #include <arch/encoding.h> #include <console/console.h> +#include <mcall.h> void run_payload(struct prog *prog, void *fdt, int payload_mode) { @@ -40,6 +41,7 @@ die("wrong privilege level for payload"); break; } + write_csr(mscratch, MACHINE_STACK_TOP()); write_csr(mstatus, status); write_csr(mepc, doit); asm volatile( diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 8aba48b..67e917c 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -18,124 +18,115 @@ #include <mcall.h> .macro restore_regs - # restore x registers - LOAD x1,1*REGBYTES(a0) - LOAD x2,2*REGBYTES(a0) - LOAD x3,3*REGBYTES(a0) - LOAD x4,4*REGBYTES(a0) - LOAD x5,5*REGBYTES(a0) - LOAD x6,6*REGBYTES(a0) - LOAD x7,7*REGBYTES(a0) - LOAD x8,8*REGBYTES(a0) - LOAD x9,9*REGBYTES(a0) - LOAD x11,11*REGBYTES(a0) - LOAD x12,12*REGBYTES(a0) - LOAD x13,13*REGBYTES(a0) - LOAD x14,14*REGBYTES(a0) - LOAD x15,15*REGBYTES(a0) - LOAD x16,16*REGBYTES(a0) - LOAD x17,17*REGBYTES(a0) - LOAD x18,18*REGBYTES(a0) - LOAD x19,19*REGBYTES(a0) - LOAD x20,20*REGBYTES(a0) - LOAD x21,21*REGBYTES(a0) - LOAD x22,22*REGBYTES(a0) - LOAD x23,23*REGBYTES(a0) - LOAD x24,24*REGBYTES(a0) - LOAD x25,25*REGBYTES(a0) - LOAD x26,26*REGBYTES(a0) - LOAD x27,27*REGBYTES(a0) - LOAD x28,28*REGBYTES(a0) - LOAD x29,29*REGBYTES(a0) - LOAD x30,30*REGBYTES(a0) - LOAD x31,31*REGBYTES(a0) - # restore a0 last - LOAD x10,10*REGBYTES(a0) + # restore x registers + LOAD x1, 1 * REGBYTES(sp) + LOAD x3, 3 * REGBYTES(sp) + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) +.endm - - .endm .macro save_tf - # save gprs - STORE x1,1*REGBYTES(x2) - STORE x3,3*REGBYTES(x2) - STORE x4,4*REGBYTES(x2) - STORE x5,5*REGBYTES(x2) - STORE x6,6*REGBYTES(x2) - STORE x7,7*REGBYTES(x2) - STORE x8,8*REGBYTES(x2) - STORE x9,9*REGBYTES(x2) - STORE x10,10*REGBYTES(x2) - STORE x11,11*REGBYTES(x2) - STORE x12,12*REGBYTES(x2) - STORE x13,13*REGBYTES(x2) - STORE x14,14*REGBYTES(x2) - STORE x15,15*REGBYTES(x2) - STORE x16,16*REGBYTES(x2) - STORE x17,17*REGBYTES(x2) - STORE x18,18*REGBYTES(x2) - STORE x19,19*REGBYTES(x2) - STORE x20,20*REGBYTES(x2) - STORE x21,21*REGBYTES(x2) - STORE x22,22*REGBYTES(x2) - STORE x23,23*REGBYTES(x2) - STORE x24,24*REGBYTES(x2) - STORE x25,25*REGBYTES(x2) - STORE x26,26*REGBYTES(x2) - STORE x27,27*REGBYTES(x2) - STORE x28,28*REGBYTES(x2) - STORE x29,29*REGBYTES(x2) - STORE x30,30*REGBYTES(x2) - STORE x31,31*REGBYTES(x2) + # save gprs + STORE x1, 1 * REGBYTES(sp) + STORE x3, 3 * REGBYTES(sp) + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) - # get sr, epc, badvaddr, cause - csrrw t0,mscratch,x0 - csrr s0,mstatus - csrr t1,mepc - csrr t2,mbadaddr - csrr t3,mcause - STORE t0,2*REGBYTES(x2) - STORE s0,32*REGBYTES(x2) - STORE t1,33*REGBYTES(x2) - STORE t2,34*REGBYTES(x2) - STORE t3,35*REGBYTES(x2) + # get sr, epc, badvaddr, cause + csrr t0, mscratch + bnez t0, 1f # t0 == 0, trap come from current program + # t0 != 0, t0 is saved old sp + add t0, sp, MENTRY_FRAME_SIZE +1: + csrr s0, mstatus + csrr t1, mepc + csrr t2, mbadaddr + csrr t3, mcause + STORE t0, 2 * REGBYTES(sp) + STORE s0, 32 * REGBYTES(sp) + STORE t1, 33 * REGBYTES(sp) + STORE t2, 34 * REGBYTES(sp) + STORE t3, 35 * REGBYTES(sp) - # get faulting insn, if it wasn't a fetch-related trap - li x5,-1 - STORE x5,36*REGBYTES(x2) + # get faulting insn, if it wasn't a fetch-related trap + li x5, -1 + STORE x5, 36 * REGBYTES(sp) +.endm - .endm - -.globl estack - .text - - .global trap_entry - .align 2 # four byte alignment, as required by mtvec + .text + .global trap_entry + # four byte alignment, as required by mtvec + .align 2 trap_entry: - csrw mscratch, sp + # mscratch is initialized to 0 + # when exiting coreboot, write sp to mscratch + csrrw sp, mscratch, sp + bnez sp, 1f # sp == 0, trap come from current program + csrrw sp, mscratch, sp +1: + addi sp, sp, -MENTRY_FRAME_SIZE + save_tf - # SMP isn't supported yet, to avoid overwriting the same stack with different - # harts that handle traps at the same time. - # someday this gets fixed. - //csrr sp, mhartid - csrr sp, 0xf14 -.Lsmp_hang: - bnez sp, .Lsmp_hang + mv a0, sp + jal trap_handler - # Use a different stack than in the main context, to to avoid overwriting - # stack data. - # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if - # the previous mode was M, because it would be a very bad idea to use a stack - # pointer provided by unprivileged code! - la sp, _estack - addi sp, sp, -2048 # 2 KiB is half of the stack space - addi sp, sp, -MENTRY_FRAME_SIZE - - save_tf - move a0,sp - jal trap_handler - -trap_return: - csrr a0, mscratch restore_regs - # go back to the previous mode + addi sp, sp, MENTRY_FRAME_SIZE + + csrrw sp, mscratch, sp + bnez sp, 1f + csrrw sp, mscratch, sp +1: mret -- To view, visit https://review.coreboot.org/c/coreboot/+/33656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I637b3b3047d2c0e12842499fe61f740d0daf489f Gerrit-Change-Number: 33656 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: mb/intel/tglrvp: Add Place holder for Tigerlake RVP
by Wonkyu Kim (Code Review) 04 Dec '19

04 Dec '19

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33567 Change subject: mb/intel/tglrvp: Add Place holder for Tigerlake RVP ...................................................................... mb/intel/tglrvp: Add Place holder for Tigerlake RVP Add place holder with ICL code and tglrvp folder. tglrvp code will be add more. Change-Id: I9cec7925594ff4c60154723e1ffa561d01b5153f Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- A src/mainboard/intel/tglrvp/Kconfig A src/mainboard/intel/tglrvp/Kconfig.name A src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/acpi/mainboard.asl A src/mainboard/intel/tglrvp/acpi_tables.c A src/mainboard/intel/tglrvp/board_id.c A src/mainboard/intel/tglrvp/board_id.h A src/mainboard/intel/tglrvp/board_info.txt A src/mainboard/intel/tglrvp/bootblock.c A src/mainboard/intel/tglrvp/chromeos.c A src/mainboard/intel/tglrvp/chromeos.fmd A src/mainboard/intel/tglrvp/dsdt.asl A src/mainboard/intel/tglrvp/hda_verb.c A src/mainboard/intel/tglrvp/mainboard.c A src/mainboard/intel/tglrvp/romstage_fsp_params.c A src/mainboard/intel/tglrvp/spd/Makefile.inc A src/mainboard/intel/tglrvp/spd/empty.spd.hex A src/mainboard/intel/tglrvp/spd/samsung_K4F6E304HBMGCJ.spd.hex A src/mainboard/intel/tglrvp/spd/spd.h A src/mainboard/intel/tglrvp/spd/spd_util.c A src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc A src/mainboard/intel/tglrvp/variants/baseboard/gpio.c A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/tglrvp/variants/icl_u/Makefile.inc A src/mainboard/intel/tglrvp/variants/icl_u/devicetree.cb A src/mainboard/intel/tglrvp/variants/icl_u/gpio.c A src/mainboard/intel/tglrvp/variants/icl_u/include/variant/ec.h A src/mainboard/intel/tglrvp/variants/icl_u/include/variant/gpio.h A src/mainboard/intel/tglrvp/variants/icl_u/include/variant/hda_verb.h A src/mainboard/intel/tglrvp/variants/icl_y/Makefile.inc A src/mainboard/intel/tglrvp/variants/icl_y/devicetree.cb A src/mainboard/intel/tglrvp/variants/icl_y/gpio.c A src/mainboard/intel/tglrvp/variants/icl_y/include/variant/ec.h A src/mainboard/intel/tglrvp/variants/icl_y/include/variant/gpio.h A src/mainboard/intel/tglrvp/variants/icl_y/include/variant/hda_verb.h 37 files changed, 3,531 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33567/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig new file mode 100755 index 0000000..728a532 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -0,0 +1,60 @@ +if BOARD_INTEL_ICELAKE_RVPU || BOARD_INTEL_ICELAKE_RVPY + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_USB_ACPI + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_ICELAKE + select MAINBOARD_USES_IFD_EC_REGION + select INTEL_LPSS_UART_FOR_CONSOLE + +config MAINBOARD_DIR + string + default "intel/icelake_rvp" + +config VARIANT_DIR + string + default "icl_u" if BOARD_INTEL_ICELAKE_RVPU + default "icl_y" if BOARD_INTEL_ICELAKE_RVPY + +config MAINBOARD_PART_NUMBER + string + default "Icelake RVP" + +config MAINBOARD_VENDOR + string + default "Intel" + +config MAINBOARD_FAMILY + string + default "Intel_icelake_rvp" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + +config UART_FOR_CONSOLE + int + default 2 +endif diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name new file mode 100755 index 0000000..9ba17a6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_INTEL_ICELAKE_RVPU + bool "Icelake U DDR4/LPDDR4 RVP" +config BOARD_INTEL_ICELAKE_RVPY + bool "Icelake Y LPDDR4 RVP" diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc new file mode 100755 index 0000000..7e74f09 --- /dev/null +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += board_id.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl new file mode 100755 index 0000000..ef2e164 --- /dev/null +++ b/src/mainboard/intel/tglrvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if CONFIG(EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/intel/tglrvp/acpi_tables.c b/src/mainboard/intel/tglrvp/acpi_tables.c new file mode 100755 index 0000000..3b44754 --- /dev/null +++ b/src/mainboard/intel/tglrvp/acpi_tables.c @@ -0,0 +1 @@ +/* Nothing here */ diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c new file mode 100755 index 0000000..b56f047 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_id.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "board_id.h" +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <ec/google/chromeec/ec.h> + +static int get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) + id = get_board_id_via_ext_ec(); + else{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return id; +} diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h new file mode 100755 index 0000000..3ccfe37 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_BOARD_ID_H_ +#define _MAINBOARD_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/tglrvp/board_info.txt b/src/mainboard/intel/tglrvp/board_info.txt new file mode 100755 index 0000000..48ec997 --- /dev/null +++ b/src/mainboard/intel/tglrvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Icelake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c new file mode 100755 index 0000000..8655947 --- /dev/null +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c new file mode 100755 index 0000000..ce8e548 --- /dev/null +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd new file mode 100755 index 0000000..f4db8b4 --- /dev/null +++ b/src/mainboard/intel/tglrvp/chromeos.fmd @@ -0,0 +1,44 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x3F0000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x36F000 + } + SI_BIOS@0x400000 0xC00000 { + RW_SECTION_A@0x0 0x2d0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bffc0 + RW_FWID_A@0x2cffc0 0x40 + } + RW_SECTION_B@0x2d0000 0x2d0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bffc0 + RW_FWID_B@0x2cffc0 0x40 + } + RW_MISC@0x5a0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + SMMSTORE(PRESERVE)@0x5d0000 0x40000 + RW_LEGACY(CBFS)@0x610000 0x1c0000 + WP_RO@0x7d0000 0x430000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x42c000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x33c000 + } + } + } +} diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl new file mode 100755 index 0000000..ad469fa --- /dev/null +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include "variant/ec.h" +#include "variant/gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/icelake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/icelake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/icelake/acpi/northbridge.asl> + #include <soc/intel/icelake/acpi/southbridge.asl> + } + } + +#if CONFIG(CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + // Chipset specific sleep states + #include <soc/intel/icelake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + +} diff --git a/src/mainboard/intel/tglrvp/hda_verb.c b/src/mainboard/intel/tglrvp/hda_verb.c new file mode 100755 index 0000000..c87392d --- /dev/null +++ b/src/mainboard/intel/tglrvp/hda_verb.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c new file mode 100755 index 0000000..36d6a3e --- /dev/null +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +static unsigned long mainboard_write_acpi_tables(struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + + start_addr = current; + + return start_addr; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c new file mode 100755 index 0000000..fd1638b --- /dev/null +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "board_id.h" +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + u8 spd_index = (get_board_id() & 0x1F) & 0x7; + printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); + + if (spd_index > 0 && spd_index != 2) { + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[2] = 0x0; + mem_cfg->SpdAddressTable[3] = 0x0; + } else { + mem_cfg->MemorySpdPtr00 = 0; + mem_cfg->MemorySpdPtr01 = 0; + mem_cfg->MemorySpdPtr10 = 0; + mem_cfg->MemorySpdPtr11 = 0; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + } + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + + mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); +} diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc new file mode 100755 index 0000000..d92ce96 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001 +SPD_SOURCES += empty # 2b010 +SPD_SOURCES += empty # 3b011 +SPD_SOURCES += samsung_K4F6E304HBMGCJ # 4b100 +SPD_SOURCES += empty # 5b101 +SPD_SOURCES += samsung_K4F6E304HBMGCJ # 6b110 +SPD_SOURCES += empty # 7b111 diff --git a/src/mainboard/intel/tglrvp/spd/empty.spd.hex b/src/mainboard/intel/tglrvp/spd/empty.spd.hex new file mode 100755 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/samsung_K4F6E304HBMGCJ.spd.hex b/src/mainboard/intel/tglrvp/spd/samsung_K4F6E304HBMGCJ.spd.hex new file mode 100755 index 0000000..62dff16 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/samsung_K4F6E304HBMGCJ.spd.hex @@ -0,0 +1,32 @@ +23 11 10 0E 15 19 94 08 00 40 00 00 0A 22 00 00 +00 00 05 0F 92 54 01 00 8A 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h new file mode 100755 index 0000000..9b55563 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/spd.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/tglrvp/spd/spd_util.c b/src/mainboard/intel/tglrvp/spd/spd_util.c new file mode 100755 index 0000000..8d7eaf6 --- /dev/null +++ b/src/mainboard/intel/tglrvp/spd/spd_util.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <arch/cpu.h> +#include <intelblocks/mp_init.h> +#include <stdint.h> +#include <string.h> + +#include "../board_id.h" +#include "spd.h" + +enum icl_dimm_type { + icl_u_ddr4 = 0, + icl_u_lpddr4 = 1, + icl_u_lpddr4_type_3 = 4, + icl_y_lpddr4 = 6 +}; + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr) +{ + /* DQ byte map Ch0 */ + const u8 dq_map[12] = { + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dq_map_ch1(void *dq_map_ptr) +{ + const u8 dq_map[12] = { + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static uint8_t get_spd_index(void) +{ + uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; + + return spd_index; +} + +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map Ch0 */ + const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; + const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; + const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case icl_u_lpddr4: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case icl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, + sizeof(dqs_map_u_lpddr_type_3)); + break; + case icl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } +} + +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map Ch1 */ + const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; + const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; + + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case icl_u_lpddr4: + case icl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case icl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 100, 100, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { + 100, 33, 32, 33, 28 }; + static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { + 80, 40, 40, 40, 30 }; + static const u16 RcompTarget_LPDDR4_Bx[RCOMP_TARGET_PARAMS] = { + 60, 20, 20, 20, 20 }; + + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(rcomp_strength_ptr, RcompTarget_DDR4, + sizeof(RcompTarget_DDR4)); + break; + case icl_y_lpddr4: + case icl_u_lpddr4: + case icl_u_lpddr4_type_3: + if (cpu_get_cpuid() == CPUID_ICELAKE_A0) + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, + sizeof(RcompTarget_LPDDR4_Ax)); + else + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx, + sizeof(RcompTarget_LPDDR4_Bx)); + break; + default: + break; + } +} diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc new file mode 100755 index 0000000..9fb63f5 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/gpio.c b/src/mainboard/intel/tglrvp/variants/baseboard/gpio.c new file mode 100755 index 0000000..20029cf --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/gpio.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { +/* I2S2_SCLK */ +PAD_CFG_GPI(GPP_A7, NONE, PLTRST), +/* I2S2_RXD */ +PAD_CFG_GPI(GPP_A10, NONE, PLTRST), +/* TCH_PNL2_RST_N */ +PAD_CFG_GPO(GPP_A13, 1, DEEP), +/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ +PAD_CFG_GPO(GPP_A14, 0, DEEP), +/* TCH_PNL2_INT_N */ +PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), +/* TC_RETIMER_FORCE_PWR */ +PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* FPS_RST_N */ +PAD_CFG_GPO(GPP_B14, 1, DEEP), +/* WIFI_RF_KILL_N */ +PAD_CFG_GPO(GPP_B15, 1, PLTRST), +/* M2_SSD_PWREN_N */ +PAD_CFG_GPO(GPP_B16, 1, DEEP), +/* WWAN_PERST_N */ +PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* BT_RF_KILL_N */ +PAD_CFG_GPO(GPP_B18, 1, PLTRST), +/* CRD_CAM_PWREN_1 */ +PAD_CFG_GPO(GPP_B23, 1, PLTRST), +/* WF_CAM_CLK_EN */ +PAD_CFG_GPO(GPP_C2, 1, PLTRST), +/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ +PAD_CFG_GPO(GPP_C5, 1, DEEP), +/* TCH_PAD_INT_N */ +PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), +/* WWAN_RST_N */ +PAD_CFG_GPO(GPP_C10, 1, DEEP), +/* WWAN_FCP_OFF_N */ +PAD_CFG_GPO(GPP_C11, 1, DEEP), +/* CODEC_INT_N */ +PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), +/* SPKR_PD_N */ +PAD_CFG_GPO(GPP_C13, 1, PLTRST), +/* WF_CAM_RST_N */ +PAD_CFG_GPO(GPP_C15, 1, PLTRST), +/* CRD_CAM_STROBE_1 */ +PAD_CFG_GPO(GPP_C22, 0, PLTRST), +/* CRD_CAM_PRIVACY_LED_1 */ +PAD_CFG_GPO(GPP_C23, 0, PLTRST), +/* FLASH_DES_SEC_OVERRIDEs */ +PAD_CFG_GPO(GPP_D13, 0, DEEP), +/* TCH_PAD_LS_EN */ +PAD_CFG_GPO(GPP_D14, 1, PLTRST), +/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ +PAD_CFG_GPO(GPP_D15, 0, DEEP), +/* MFR_MODE_DET_STRAP */ +PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* TBT_CIO_PWR_EN */ +PAD_CFG_GPO(GPP_E0, 1, DEEP), +/* FPS_INT */ +PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), +/* EC_SLP_S0_CS_N */ +PAD_CFG_GPO(GPP_E6, 1, DEEP), +/* EC_SMI_N */ +PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), +/* TBT_CIO_PLUG_EVENT_N */ +PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), +/* DISP_AUX_P_BIAS_GPIO */ +PAD_CFG_GPO(GPP_E22, 0, PLTRST), +/* DISP_AUX_N_BIAS_GPIO */ +PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* SATA_HDD_PWREN */ +PAD_CFG_GPO(GPP_F4, 1, PLTRST), +/* BIOS_REC */ +PAD_CFG_GPI(GPP_F5, NONE, PLTRST), +/* SD_CD# */ +PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), +/* SD_WP */ +PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), +/* M2_SSD_RST_N */ +PAD_CFG_GPO(GPP_H0, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + +}; + +const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__attribute__((weak)) + variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h new file mode 100755 index 0000000..03096ac --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include <variant/gpio.h> + + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h new file mode 100755 index 0000000..ca303f9 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h new file mode 100755 index 0000000..12d16bc --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/icl_u/Makefile.inc b/src/mainboard/intel/tglrvp/variants/icl_u/Makefile.inc new file mode 100755 index 0000000..0c1af69 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_u/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/tglrvp/variants/icl_u/devicetree.cb new file mode 100755 index 0000000..6d7fad7 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_u/devicetree.cb @@ -0,0 +1,350 @@ +chip soc/intel/icelake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PrmrrSize" = "0x10000000" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + + register "PcieClkSrcUsage[0]" = "2" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "0xE" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Lower"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 4"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Upper"" + register "type" = "UPC_TYPE_A" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right Lower"" + register "type" = "UPC_TYPE_A" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right Upper"" + register "type" = "UPC_TYPE_A" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Lower"" + register "type" = "UPC_TYPE_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Upper"" + register "type" = "UPC_TYPE_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused1"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused2"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused3"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""ALPS0000"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C 0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end + end + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/tglrvp/variants/icl_u/gpio.c b/src/mainboard/intel/tglrvp/variants/icl_u/gpio.c new file mode 100755 index 0000000..ea96cbc --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_u/gpio.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { +/* I2S2_SCLK */ +PAD_CFG_GPI(GPP_A7, NONE, PLTRST), +/* I2S2_RXD */ +PAD_CFG_GPI(GPP_A10, NONE, PLTRST), +/* TCH_PNL2_RST_N */ +PAD_CFG_GPO(GPP_A13, 1, DEEP), +/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ +PAD_CFG_GPO(GPP_A14, 0, DEEP), +/* TCH_PNL2_INT_N */ +PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), +/* TC_RETIMER_FORCE_PWR */ +PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* FPS_RST_N */ +PAD_CFG_GPO(GPP_B14, 1, DEEP), +/* WIFI_RF_KILL_N */ +PAD_CFG_GPO(GPP_B15, 1, PLTRST), +/* M2_SSD_PWREN_N */ +PAD_CFG_GPO(GPP_B16, 1, DEEP), +/* WWAN_PERST_N */ +PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* BT_RF_KILL_N */ +PAD_CFG_GPO(GPP_B18, 1, PLTRST), +/* CRD_CAM_PWREN_1 */ +PAD_CFG_GPO(GPP_B23, 1, PLTRST), +/* WF_CAM_CLK_EN */ +PAD_CFG_GPO(GPP_C2, 1, PLTRST), +/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ +PAD_CFG_GPO(GPP_C5, 1, DEEP), +/* TCH_PAD_INT_N */ +PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), +/* WWAN_RST_N */ +PAD_CFG_GPO(GPP_C10, 1, DEEP), +/* WWAN_FCP_OFF_N */ +PAD_CFG_GPO(GPP_C11, 1, DEEP), +/* CODEC_INT_N */ +PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), +/* SPKR_PD_N */ +PAD_CFG_GPO(GPP_C13, 1, PLTRST), +/* WF_CAM_RST_N */ +PAD_CFG_GPO(GPP_C15, 1, PLTRST), +/* CRD_CAM_STROBE_1 */ +PAD_CFG_GPO(GPP_C22, 0, PLTRST), +/* CRD_CAM_PRIVACY_LED_1 */ +PAD_CFG_GPO(GPP_C23, 0, PLTRST), +/* FLASH_DES_SEC_OVERRIDEs */ +PAD_CFG_GPO(GPP_D13, 0, DEEP), +/* TCH_PAD_LS_EN */ +PAD_CFG_GPO(GPP_D14, 1, PLTRST), +/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ +PAD_CFG_GPO(GPP_D15, 0, DEEP), +/* MFR_MODE_DET_STRAP */ +PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* TBT_CIO_PWR_EN */ +PAD_CFG_GPO(GPP_E0, 1, DEEP), +/* FPS_INT */ +PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), +/* EC_SLP_S0_CS_N */ +PAD_CFG_GPO(GPP_E6, 1, DEEP), +/* EC_SMI_N */ +PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), +/* TBT_CIO_PLUG_EVENT_N */ +PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), +/* DISP_AUX_P_BIAS_GPIO */ +PAD_CFG_GPO(GPP_E22, 0, PLTRST), +/* DISP_AUX_N_BIAS_GPIO */ +PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* SATA_HDD_PWREN */ +PAD_CFG_GPO(GPP_F4, 1, PLTRST), +/* BIOS_REC */ +PAD_CFG_GPI(GPP_F5, NONE, PLTRST), +/* SD_CD# */ +PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), +/* SD_WP */ +PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), +/* M2_SSD_RST_N */ +PAD_CFG_GPO(GPP_H0, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/ec.h b/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/ec.h new file mode 100755 index 0000000..af41bf4 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/gpio.h b/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/gpio.h new file mode 100755 index 0000000..c34a9b3 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/hda_verb.h b/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/hda_verb.h new file mode 100755 index 0000000..d821a26 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_u/include/variant/hda_verb.h @@ -0,0 +1,700 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC 700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC10F2), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111F0), + AZALIA_PIN_CFG(0, 0x15, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x40622005), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x29, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/intel/tglrvp/variants/icl_y/Makefile.inc b/src/mainboard/intel/tglrvp/variants/icl_y/Makefile.inc new file mode 100755 index 0000000..0c1af69 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_y/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/tglrvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/tglrvp/variants/icl_y/devicetree.cb new file mode 100755 index 0000000..4f41308 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_y/devicetree.cb @@ -0,0 +1,350 @@ +chip soc/intel/icelake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # UNUSED + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED + + # Enable Pch iSCLK + register "pch_isclk" = "1" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PrmrrSize" = "0x10000000" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "0xC" + register "PcieClkSrcUsage[3]" = "0x70" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "2" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPortsDevSlp[3]" = "1" + register "SataPortsDevSlp[4]" = "1" + register "SataPortsDevSlp[5]" = "1" + register "SataPortsDevSlp[6]" = "1" + register "SataPortsDevSlp[7]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB3-2 Type-A Left Lower"" + register "type" = "UPC_TYPE_A" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3-2 Type-A Left Upper"" + register "type" = "UPC_TYPE_A" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB C Connector 3"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port Unused 1"" + register "type" = "UPC_TYPE_UNUSED" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port Unused 2"" + register "type" = "UPC_TYPE_UNUSED" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right Lower"" + register "type" = "UPC_TYPE_A" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right Upper"" + register "type" = "UPC_TYPE_A" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Lower"" + register "type" = "UPC_TYPE_A" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3/2 Type-A Left Upper"" + register "type" = "UPC_TYPE_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused1"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused2"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Port Unused3"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""ALPS0000"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C 0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + device spi 0 on end + end + end # GSPI #1 + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/tglrvp/variants/icl_y/gpio.c b/src/mainboard/intel/tglrvp/variants/icl_y/gpio.c new file mode 100755 index 0000000..ea96cbc --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_y/gpio.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { +/* I2S2_SCLK */ +PAD_CFG_GPI(GPP_A7, NONE, PLTRST), +/* I2S2_RXD */ +PAD_CFG_GPI(GPP_A10, NONE, PLTRST), +/* TCH_PNL2_RST_N */ +PAD_CFG_GPO(GPP_A13, 1, DEEP), +/* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ +PAD_CFG_GPO(GPP_A14, 0, DEEP), +/* TCH_PNL2_INT_N */ +PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), +/* TC_RETIMER_FORCE_PWR */ +PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* FPS_RST_N */ +PAD_CFG_GPO(GPP_B14, 1, DEEP), +/* WIFI_RF_KILL_N */ +PAD_CFG_GPO(GPP_B15, 1, PLTRST), +/* M2_SSD_PWREN_N */ +PAD_CFG_GPO(GPP_B16, 1, DEEP), +/* WWAN_PERST_N */ +PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* BT_RF_KILL_N */ +PAD_CFG_GPO(GPP_B18, 1, PLTRST), +/* CRD_CAM_PWREN_1 */ +PAD_CFG_GPO(GPP_B23, 1, PLTRST), +/* WF_CAM_CLK_EN */ +PAD_CFG_GPO(GPP_C2, 1, PLTRST), +/* ONBOARD_X4_PCIE_SLOT1_RESET_N */ +PAD_CFG_GPO(GPP_C5, 1, DEEP), +/* TCH_PAD_INT_N */ +PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), +/* WWAN_RST_N */ +PAD_CFG_GPO(GPP_C10, 1, DEEP), +/* WWAN_FCP_OFF_N */ +PAD_CFG_GPO(GPP_C11, 1, DEEP), +/* CODEC_INT_N */ +PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), +/* SPKR_PD_N */ +PAD_CFG_GPO(GPP_C13, 1, PLTRST), +/* WF_CAM_RST_N */ +PAD_CFG_GPO(GPP_C15, 1, PLTRST), +/* CRD_CAM_STROBE_1 */ +PAD_CFG_GPO(GPP_C22, 0, PLTRST), +/* CRD_CAM_PRIVACY_LED_1 */ +PAD_CFG_GPO(GPP_C23, 0, PLTRST), +/* FLASH_DES_SEC_OVERRIDEs */ +PAD_CFG_GPO(GPP_D13, 0, DEEP), +/* TCH_PAD_LS_EN */ +PAD_CFG_GPO(GPP_D14, 1, PLTRST), +/* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ +PAD_CFG_GPO(GPP_D15, 0, DEEP), +/* MFR_MODE_DET_STRAP */ +PAD_CFG_GPI(GPP_D16, NONE, PLTRST), +/* TBT_CIO_PWR_EN */ +PAD_CFG_GPO(GPP_E0, 1, DEEP), +/* FPS_INT */ +PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), +/* EC_SLP_S0_CS_N */ +PAD_CFG_GPO(GPP_E6, 1, DEEP), +/* EC_SMI_N */ +PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), +/* TBT_CIO_PLUG_EVENT_N */ +PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), +/* DISP_AUX_P_BIAS_GPIO */ +PAD_CFG_GPO(GPP_E22, 0, PLTRST), +/* DISP_AUX_N_BIAS_GPIO */ +PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* SATA_HDD_PWREN */ +PAD_CFG_GPO(GPP_F4, 1, PLTRST), +/* BIOS_REC */ +PAD_CFG_GPI(GPP_F5, NONE, PLTRST), +/* SD_CD# */ +PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), +/* SD_WP */ +PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), +/* M2_SSD_RST_N */ +PAD_CFG_GPO(GPP_H0, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/ec.h b/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/ec.h new file mode 100755 index 0000000..af41bf4 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/gpio.h b/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/gpio.h new file mode 100755 index 0000000..c34a9b3 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/hda_verb.h b/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/hda_verb.h new file mode 100755 index 0000000..d821a26 --- /dev/null +++ b/src/mainboard/intel/tglrvp/variants/icl_y/include/variant/hda_verb.h @@ -0,0 +1,700 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC 700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC10F2), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111F0), + AZALIA_PIN_CFG(0, 0x15, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x40622005), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x29, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cec7925594ff4c60154723e1ffa561d01b5153f Gerrit-Change-Number: 33567 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/g/hatch: Add privacy screen support to dratini variant
by Mathew King (Code Review) 03 Dec '19

03 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36073 ) Change subject: mb/g/hatch: Add privacy screen support to dratini variant ...................................................................... mb/g/hatch: Add privacy screen support to dratini variant Change-Id: I6787a7eb59017ac923798cad1c1aa8cf7b75aa52 --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h M src/mainboard/google/hatch/variants/dratini/overridetree.cb 6 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/36073/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..800fd02 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -3,6 +3,7 @@ def_bool n select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A + select DRIVERS_GENERIC_GFX if BOARD_GOOGLE_DRATINI select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e2959a7..3e81f5f 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -40,6 +40,7 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <soc/intel/cannonlake/acpi/gfx.asl> } /* Mainboard hooks */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 003b7d1..f03264a 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -33,6 +33,8 @@ PAD_NC(GPP_A19, NONE), /* C15 : NC */ PAD_NC(GPP_C15, NONE), + /* E0 : LCD_PRIVACY_PCH */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F1 : NC */ PAD_NC(GPP_F1, NONE), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl index 31f72b3..173222d 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -14,3 +14,34 @@ */ #include <baseboard/acpi/dptf.asl> + +Scope (\_SB.PCI0.GFX0) +{ + /* Read Privacy Screen Present */ + Method (GPVD, 0, Serialized) + { + Printf ("Read Privacy Screen Present") + Return (One) + } + + /* Read Privacy Screen Status */ + Method (GPVX, 0, Serialized) + { + Printf ("Read Privacy Screen Status") + Return (\_SB.PCI0.GTXS (PV_ENABLE_PIN)) + } + + /* Enable Privacy Screen */ + Method (EPVX, 0, Serialized) + { + Printf ("Enable Privacy Screen") + \_SB.PCI0.STXS (PV_ENABLE_PIN) + } + + /* Disable Privacy Screen */ + Method (DPVX, 0, Serialized) + { + Printf ("Disable Privacy Screen") + \_SB.PCI0.CTXS (PV_ENABLE_PIN) + } +} \ No newline at end of file diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h index 92f9d41..2542503 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -24,4 +24,6 @@ #define GPIO_MEM_CONFIG_2 GPP_F10 #define GPIO_MEM_CONFIG_3 GPP_F3 +#define PV_ENABLE_PIN GPP_E0 + #endif diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index f1e8239..ec23dd4 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -54,6 +54,19 @@ register "ScsEmmcHs400Enabled" = "1" device domain 0 on + device pci 02.0 on + chip drivers/generic/gfx + register "device_count" = "1" + register "device[0].name" = ""LCD"" + register "device[0].addr" = "0x0400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.detect_function" = ""^^GPVD"" + register "device[0].privacy.status_function" = ""^^GPVX"" + register "device[0].privacy.enable_function" = ""^^EPVX"" + register "device[0].privacy.disable_function" = ""^^DPVX"" + device generic 0 on end + end + end # Integrated Graphics Device device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/36073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6787a7eb59017ac923798cad1c1aa8cf7b75aa52 Gerrit-Change-Number: 36073 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform
by Name of user not set (Code Review) 03 Dec '19

03 Dec '19

Name of user not set #1002246 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31205 Change subject: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform ...................................................................... [RFC] Initial commit to support SKL SP and OCP Tiogapass platform Summary: This commit adds support for SK SP and OCP Tiogapass platform: * Added microcode files. * Added FSP header files. * Updated skylake soc code to accomodate FSP 2.0. * Added tiogapass platform code to accomodate FSP 2.0. With this commit, it is able to build coreboot.rom image. The 3 FSP binaries are added to the coreboot image. It looks okay by examining the coreboot.rom file through ifdtool command. However, when booting with this image, no postcode is observed on port 80, no UART message shows up. Debugging is on-going. This commit is submitted as draft to enable early review feedback. Change-Id: I389355162eb9515b533a8d7f77cc8f03b8beb019 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> test Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda --- M src/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi/mainboard.asl A src/mainboard/ocp/tiogapass/board_id.c A src/mainboard/ocp/tiogapass/board_id.h A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/cmos.default A src/mainboard/ocp/tiogapass/cmos.layout A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/gpio.h A src/mainboard/ocp/tiogapass/pei_data.c A src/mainboard/ocp/tiogapass/ramstage.c A src/mainboard/ocp/tiogapass/romstage.c A src/mainboard/ocp/tiogapass/spd/Makefile.inc A src/mainboard/ocp/tiogapass/spd/spd.h A src/mainboard/ocp/tiogapass/spd/spd_util.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/fsp20/soc/ramstage.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/vr_config.c M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h 34 files changed, 1,968 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31205/1 diff --git a/src/Kconfig b/src/Kconfig index a069f63..7de3335 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -360,6 +360,7 @@ source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" +source "src/drivers/intel/fsp2_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 5ed3801..666020a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -66,9 +66,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ -void setup_mma(FSP_M_CONFIG *memory_cfg); +void setup_mma(FSPM_CONFIG *memory_cfg); /* Update the SOC specific memory config param for mma. */ -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, +void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); /* diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig new file mode 100644 index 0000000..c411b15 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -0,0 +1,58 @@ +if BOARD_OCP_TIOGAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select CONSOLE_SERIAL + select DRIVERS_UART + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select EC_ACPI + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select SERIRQ_CONTINUOUS_MODE + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select MAINBOARD_USES_FSP2_0 + select HAVE_CMOS_DEFAULT + + +config PLATFORM_USES_FSP2_0 + bool "FSP driver 2.0" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "ocp/tiogapass" + +config MAINBOARD_PART_NUMBER + string + default "Tioga Pass" + +config MAINBOARD_FAMILY + string + default "OCP_TiogaPass" + +config CBFS_SIZE + hex + default 0x1000000 + +config VIRTUAL_ROM_SIZE + hex + default 0x2000000 + +config MAX_CPUS + int + default 8 + +config TPM_PIRQ + hex + default 0x18 # GPP_E0_IRQ + +endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name new file mode 100644 index 0000000..0c57fd3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_TIOGAPASS + bool "Tioga Pass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc new file mode 100644 index 0000000..77cdb16 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +romstage-y += pei_data.c +romstage-y += board_id.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/ocp/tiogapass/acpi/mainboard.asl b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl new file mode 100644 index 0000000..5174eeb --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> diff --git a/src/mainboard/ocp/tiogapass/board_id.c b/src/mainboard/ocp/tiogapass/board_id.c new file mode 100644 index 0000000..a362b08 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_id.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "board_id.h" +#include <ec/acpi/ec.h> +#include <stdint.h> + +/* + * Get Board ID via EC I/O port write/read + */ +int get_board_id(void) +{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + return (buffer[1] << 8) | buffer[0]; + } + return -1; +} diff --git a/src/mainboard/ocp/tiogapass/board_id.h b/src/mainboard/ocp/tiogapass/board_id.h new file mode 100644 index 0000000..881866f --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_id.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_BOARD_ID_H_ +#define _MAINBOARD_BOARD_ID_H_ + +/* Mobile Board Id 0x00 - 0xFF */ +#define BOARD_ID_SKL_A0_RVP3 0x04 +#define BOARD_ID_SKL_RVP7 0x0B + +/* 60-6F reserved for KBL RVPs */ +#define BOARD_ID_KBL_LPDDR3_RVP3 0x60 +#define BOARD_ID_KBL_LPDDR3_RVP7 0x64 + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt new file mode 100644 index 0000000..25dac38 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: Tioga Pass +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2017 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..cf9740d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/ocp/tiogapass/cmos.default b/src/mainboard/ocp/tiogapass/cmos.default new file mode 100644 index 0000000..cd8bd47 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/ocp/tiogapass/cmos.layout b/src/mainboard/ocp/tiogapass/cmos.layout new file mode 100644 index 0000000..83a2e05 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/cmos.layout @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#401 7 r 0 unused + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#544 440 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb new file mode 100644 index 0000000..9b23a0e --- /dev/null +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -0,0 +1,293 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "Heci3Enabled" = "0" + + register "SaGv" = "3" + register "PmTimerDisabled" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + register "SerialIrqConfigSirqMode" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + + # Skip coreboot MP Init + register "common_soc_config" = "{ + .use_fsp_mp_init = 1, + }" + + # Enable x1 slot + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 + + # Enable x4 slot + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 + + # Enable Root port 6 and 13. + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[12]" = "1" + + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + + # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[5]" = "0" + register "PcieRpClkReqNumber[12]" = "1" + + register "EnableLan" = "1" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor + register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "PmTimerDisabled" = "0" + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoPci, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration + #register "sdcard_cd_gpio_default" = "GPP_A7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl new file mode 100644 index 0000000..45d9a85 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h new file mode 100644 index 0000000..f8db6cd --- /dev/null +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP8_H +#define _GPIORVP8_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + +/* GPE_EC_WAKE */ +#define GPE_EC_WAKE GPE0_LAN_WAK +#define EC_SMI_GPI GPP_I3 + +/* + * Gpio based irq for touchpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define KBLRVP_TOUCHPAD_IRQ 33 + +#define KBLRVP_TOUCH_IRQ 31 + +#define BOARD_TOUCHPAD_NAME "touchpad" +#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ +#define BOARD_TOUCHPAD_I2C_BUS 0 +#define BOARD_TOUCHPAD_I2C_ADDR 0x20 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), +/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), +/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), +/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), +/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), +/* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP), +/* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0_DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS_N */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS_N */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS_N */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SSP0_SFRM */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1), +/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES), +/* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), +/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP), +/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP), +/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP), +/* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* USB_OC7_R_N */ PAD_CFG_GPO(GPP_F18, 1, DEEP), +/* GPIO_PEG_RESET */ PAD_CFG_GPO(GPP_F22, 1, DEEP), +/* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP), +/* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), +/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), +/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), +/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP), +/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES), +/* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP), +/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), +/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES), +/* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP), +/* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP), +/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP), +/* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), +/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP), +/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), +/* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP), +/* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP), +/* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), +/* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP), +/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP), +/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP), +/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP), +/* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP), +/* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), +/* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* USB_WAKEOUT_N */ PAD_CFG_NF(GPD7, NONE, DEEP, NF1), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + + +#endif +#endif diff --git a/src/mainboard/ocp/tiogapass/pei_data.c b/src/mainboard/ocp/tiogapass/pei_data.c new file mode 100644 index 0000000..ac4ce95 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/pei_data.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd/spd.h" + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c new file mode 100644 index 0000000..6fef017 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +// params->CdClock = 3; + + /* Enable Virtual Channel 1 */ +// params->PchHdaVcType = 0x1; +} + +static void ioexpander_init(void *unused) +{ + printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n"); + + /* I/O Expander 1, Port 0 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0DOUT, + 0xF7); + /* Port 0 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0CONF, + 0xE0); + + /* Port 1 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1DOUT, + 0x9E); + /* Port 1 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1CONF, + 0x8C); + + /* Port 2 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2DOUT, + 0xDA); + /* Port 2 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2CONF, + 0x08); + + /* I/O Expander 2, Port 0 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0DOUT, + 0xFF); + /* Port 0 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF, + 0x00); + +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, ioexpander_init, NULL); diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c new file mode 100644 index 0000000..230cc50 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" +#include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> +#include "board_id.h" + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSPM_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); +/* + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); +*/ + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + struct region_device spd_rdev; + +// mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); +// mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ +// mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */ + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + +// mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); +// mem_cfg->MemorySpdDataLen = blk.len; +// mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; +// mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { +// mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; +// mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + } + + } +// mupd->FspmTestConfig.DmiVc1 = 1; +// if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) +// mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} diff --git a/src/mainboard/ocp/tiogapass/spd/Makefile.inc b/src/mainboard/ocp/tiogapass/spd/Makefile.inc new file mode 100644 index 0000000..721736d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c diff --git a/src/mainboard/ocp/tiogapass/spd/spd.h b/src/mainboard/ocp/tiogapass/spd/spd.h new file mode 100644 index 0000000..a5f1af3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/spd.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/ocp/tiogapass/spd/spd_util.c b/src/mainboard/ocp/tiogapass/spd/spd_util.c new file mode 100644 index 0000000..2c26d78 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/spd_util.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 506a041..f1f03d7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,6 +20,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS @@ -28,43 +29,40 @@ select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select C_ENVIRONMENT_BOOTBLOCK - select FSP_M_XIP if MAINBOARD_USES_FSP2_0 - select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP - select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_INTEL_FIRMWARE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER - select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_64MB select REG_SCRIPT + select RTC select SA_ENABLE_DPR select SMM_TSEG select SMP - select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI - select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT @@ -76,10 +74,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC -config CPU_INTEL_NUM_FIT_ENTRIES - int - default 10 - config MAINBOARD_USES_FSP2_0 bool default n @@ -88,7 +82,7 @@ def_bool y depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING + select UDK_2017_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select POSTCAR_CONSOLE select POSTCAR_STAGE @@ -98,7 +92,6 @@ depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS - select SKIP_FSP_CAR config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -112,6 +105,10 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH +config BOOTBLOCK_RESETS + string + default "soc/intel/common/reset.c" + config CBFS_SIZE hex default 0x200000 @@ -124,6 +121,10 @@ hex default 0xfef00000 +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/skylake/bootblock/bootblock.c" + config DCACHE_RAM_SIZE hex default 0x40000 @@ -162,6 +163,10 @@ help This option allows you to select MMIO Base Address of sideband bus. +config SERIAL_CPU_INIT + bool + default n + config SERIRQ_CONTINUOUS_MODE bool default n @@ -181,12 +186,31 @@ string default "8086,0406" +config UART_DEBUG + bool "Enable UART debug port." + default y + select CONSOLE_SERIAL + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + +config UART_FOR_CONSOLE + int "Index for LPSS UART port to use for console" + default 2 if DRIVERS_UART_8250MEM + default 0 + help + Index for LPSS UART port to use for console: + 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 + config SKYLAKE_SOC_PCH_H bool default n help Choose this option if you have a PCH-H chipset. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + config NHLT_DMIC_2CH bool default n @@ -247,19 +271,37 @@ help Include DSP firmware settings for DA7219 headset codec. -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - # Use KabylakeFsp for both Skylake and Kabylake as it supports both. - # SkylakeFsp is FSP 1.1 and therefore incompatible. - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE +choice + prompt "Cache-as-ram implementation" + default USE_SKYLAKE_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. -config FSP_FD_PATH - string - depends on FSP_USE_REPO - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE +config USE_SKYLAKE_CAR_NEM_ENHANCED + bool "Enhanced Non-evict mode" + select SOC_INTEL_COMMON_BLOCK_CAR + select INTEL_CAR_NEM_ENHANCED + help + A current limitation of NEM (Non-Evict mode) is that code and data + sizes are derived from the requirement to not write out any modified + cache line. With NEM, if there is no physical memory behind the + cached area, the modified data will be lost and NEM results will be + inconsistent. ENHANCED NEM guarantees that modified data is always + kept in cache while clean data is replaced. + +config USE_SKYLAKE_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + +config SKIP_FSP_CAR + bool "Skip cache as RAM setup in FSP" + default y + help + Skip Cache as RAM setup in FSP. config SPI_FLASH_INCLUDE_ALL_DRIVERS bool diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ee2c928..c5451e6 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += nhlt subdirs-y += romstage -subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic @@ -11,7 +10,6 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c @@ -22,13 +20,13 @@ bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += lpc.c -bootblock-y += uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c verstage-y += spi.c -verstage-y += uart.c +verstage-$(CONFIG_UART_DEBUG) += uart.c romstage-y += gpio.c romstage-y += gspi.c @@ -40,7 +38,7 @@ romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c -romstage-y += uart.c +romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c @@ -67,33 +65,22 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += thermal.c -ramstage-y += uart.c -ramstage-y += vr_config.c +ramstage-$(CONFIG_UART_DEBUG) += uart.c +//ramstage-y += vr_config.c smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += uart.c +smm-$(CONFIG_UART_DEBUG) += uart.c postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c -postcar-y += i2c.c -postcar-y += uart.c +postcar-$(CONFIG_UART_DEBUG) += uart.c - -# Skylake D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin -# Skylake H Q0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin -# Kabylake H0, Y0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin -# Kabylake HB0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin -# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) -# since those are probably pre-release samples. +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include @@ -103,6 +90,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake endif # Currently used for microcode path. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3ade8d7..020dea3 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -20,12 +20,16 @@ #include <fsp/api.h> #include <arch/acpi.h> #include <arch/io.h> +#include <chip.h> +#include <compiler.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> +#include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/chip.h> -#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -34,7 +38,6 @@ #include <soc/interrupt.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -165,16 +168,8 @@ void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); - - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* swap enabled PCI ports in device tree if needed */ pcie_override_devicetree_after_silicon_init(); } @@ -227,8 +222,9 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - FSP_S_CONFIG *params = &supd->FspsConfig; - FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + FSPS_CONFIG *params = &supd->FspsConfig; +#if 0 +// FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; static struct soc_intel_skylake_config *config; uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; @@ -244,14 +240,14 @@ /* Set PsysPmax if it is available from DT */ if (config->psys_pmax) { /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; - printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); +// tconfig->PsysPmax = config->psys_pmax * 8; +// printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } - params->GraphicsConfigPtr = (u32) vbt_data; +// params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = +/* params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -295,6 +291,7 @@ sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); +*/ /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for @@ -341,15 +338,6 @@ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; params->ScsSdCardEnabled = config->ScsSdCardEnabled; - if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; - } - /* If ISH is enabled, enable ISH elements */ dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) @@ -365,20 +353,18 @@ params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; params->SataPwrOptEnable = config->SataPwrOptEnable; - params->EnableTcoTimer = !config->PmTimerDisabled; - tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; - tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; +// tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; +// tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; +// tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - tconfig->PchLockDownBiosInterface = 0; +// tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; /* @@ -390,17 +376,8 @@ */ params->SpiFlashCfgLockDown = 0; } - /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; - } - - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - } - + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; @@ -467,13 +444,13 @@ params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; /* Enable PMC XRAM read */ - tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; +// tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; /* Enable/Disable EIST */ - tconfig->Eist = config->eist_enable; +// tconfig->Eist = config->eist_enable; /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; +// tconfig->TccActivationOffset = config->tcc_offset; /* Enable VT-d and X2APIC */ if (!config->ignore_vtd && soc_is_vtd_capable()) { @@ -487,12 +464,13 @@ params->PchIoApicDeviceNumber = 31; params->PchIoApicFunctionNumber = 0; } +#endif soc_irq_settings(params); } /* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSPS_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index e75b350..820e517 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -22,10 +22,10 @@ #include <fsp/api.h> #include <fsp/util.h> -#define FSP_SIL_UPD FSP_S_CONFIG -#define FSP_MEM_UPD FSP_M_CONFIG +#define FSP_SIL_UPD FSPS_CONFIG +#define FSP_MEM_UPD FSPM_CONFIG -void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_silicon_init_params(FSPS_CONFIG *params); void soc_fsp_load(void); void soc_init_pre_device(void *chip_info); void soc_irq_settings(FSP_SIL_UPD *params); diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 7b3e1bd..d26bd84 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -22,6 +22,7 @@ #include <soc/irq.h> #include <string.h> +#if 0 static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { /* * cAVS(Audio, Voice, Speech), INTA is default, programmed in @@ -216,23 +217,26 @@ DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) }; +#endif void soc_irq_settings(FSP_SIL_UPD *params) { - uint32_t i, intdeventry; + uint32_t i; +// uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; +// const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); +// const struct soc_intel_skylake_config *config = dev->chip_info; /* Get Device Int Count */ - intdeventry = ARRAY_SIZE(devintconfig); +// intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ - memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) +/* memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) (params->DevIntConfigPtr), devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); params->NumOfDevIntConfig = intdeventry; +*/ /* PxRC to IRQ programming */ for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { switch (i) { @@ -250,13 +254,15 @@ break; } } - memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); +// memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); /* GPIO IRQ Route The valid values is 14 or 15 */ - if (config->GpioIrqSelect == 0) +/* if (config->GpioIrqSelect == 0) params->GpioIrqRoute = GPIO_IRQ14; else params->GpioIrqRoute = config->GpioIrqSelect; +*/ /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ +#if 0 if (config->SciIrqSelect == 0) params->SciIrqSelect = SCI_IRQ9; else @@ -268,6 +274,7 @@ params->TcoIrqSelect = config->TcoIrqSelect; /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; +#endif } /* diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..48f3429 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/symbols.h> #include <assert.h> +#include <compiler.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -37,6 +38,7 @@ #include <string.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> +#include <MemInfoHob.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -101,18 +103,18 @@ if (src_dimm->Status != DIMM_PRESENT) continue; - switch (memory_info_hob->MemoryType) { + switch(memory_info_hob->MemoryType) { case MRC_DDR_TYPE_DDR4: - ddr_type = MEMORY_TYPE_DDR4; + ddr_type = MEMORY_DEVICE_DDR4; break; case MRC_DDR_TYPE_DDR3: - ddr_type = MEMORY_TYPE_DDR3; + ddr_type = MEMORY_DEVICE_DDR3; break; case MRC_DDR_TYPE_LPDDR3: - ddr_type = MEMORY_TYPE_LPDDR3; + ddr_type = MEMORY_DEVICE_LPDDR3; break; default: - ddr_type = MEMORY_TYPE_UNKNOWN; + ddr_type = MEMORY_DEVICE_UNKNOWN; break; } @@ -190,19 +192,19 @@ run_postcar_phase(&pcf); } -static void cpu_flex_override(FSP_M_CONFIG *m_cfg) +static void cpu_flex_override(FSPM_CONFIG *m_cfg) { msr_t flex_ratio; - m_cfg->CpuRatioOverride = 1; +// m_cfg->CpuRatioOverride = 1; /* * Set cpuratio to that value set in bootblock, This will ensure FSPM * knows the intended flex ratio. */ flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; +// m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, +static void soc_memory_init_params(FSPM_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { int i; @@ -215,31 +217,30 @@ * With the default stolen size of 32MB(-8MB) there is not enough space * for FBC to work with a high resolution panel. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->MmioSize = 0x800; /* 2GB in MB */ - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; - m_cfg->CmdTriStateDis = config->CmdTriStateDis; - m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = config->VmxEnable; - m_cfg->PrmrrSize = config->PrmrrSize; +// m_cfg->IgdDvmt50PreAlloc = 2; +// m_cfg->MmioSize = 0x800; /* 2GB in MB */ +// m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; +// m_cfg->IedSize = CONFIG_IED_REGION_SIZE; +// m_cfg->ProbelessTrace = config->ProbelessTrace; +// m_cfg->SaGv = config->SaGv; +// m_cfg->UserBd = BOARD_TYPE_ULT_ULX; +// m_cfg->RMT = config->Rmt; +// m_cfg->DdrFreqLimit = config->DdrFreqLimit; +// m_cfg->VmxEnable = config->VmxEnable; +// m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); } - m_cfg->PcieRpEnableMask = mask; +// m_cfg->PcieRpEnableMask = mask; cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = 250; - m_cfg->PchHpetDeviceNumber = 15; - m_cfg->PchHpetFunctionNumber = 0; +// m_cfg->PchHpetBdfValid = 1; +// m_cfg->PchHpetBusNumber = 250; +// m_cfg->PchHpetDeviceNumber = 15; +// m_cfg->PchHpetFunctionNumber = 0; } } @@ -247,8 +248,8 @@ { const struct device *dev; const struct soc_intel_skylake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; + FSPM_CONFIG *m_cfg = &mupd->FspmConfig; +// FSPM_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; @@ -256,43 +257,43 @@ soc_memory_init_params(m_cfg, config); /* Skip creating Management Engine MBP HOB */ - m_t_cfg->SkipMbpHob = 0x01; +// m_t_cfg->SkipMbpHob = 0x01; /* Enable DMI Virtual Channel for ME */ - m_t_cfg->DmiVcm = 0x01; +// m_t_cfg->DmiVcm = 0x01; /* Enable Sending DID to ME */ - m_t_cfg->SendDidMsg = 0x01; - m_t_cfg->DidInitStat = 0x01; +// m_t_cfg->SendDidMsg = 0x01; +// m_t_cfg->DidInitStat = 0x01; /* DCI and TraceHub configs */ - m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; - m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; - m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; +// m_t_cfg->PchDciEn = config->PchDciEn; +// m_cfg->EnableTraceHub = config->EnableTraceHub; +// m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; +// m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; +// m_cfg->SmbusEnable = config->SmbusEnable; mainboard_memory_init_params(mupd); } -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, +void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); - memory_cfg->MrcFastBoot = 0x00; - memory_cfg->SaGv = 0x02; +// memory_cfg->MmaTestContentPtr = +// (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); +// memory_cfg->MmaTestContentSize = +// region_device_sz(&mma_cfg->test_content); +// memory_cfg->MmaTestConfigPtr = +// (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); +// memory_cfg->MmaTestConfigSize = +// region_device_sz(&mma_cfg->test_param); +// memory_cfg->MrcFastBoot = 0x00; +// memory_cfg->SaGv = 0x02; } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 4508fda..9266330 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -56,7 +56,7 @@ * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | * +----------------+-------------+---------------+------+-----+ */ - +#if 0 static const struct { uint16_t icc_max[NUM_VR_DOMAINS]; }sku_icc_max_mapping[] = { @@ -167,12 +167,13 @@ .voltage_limit = 1520, }, }; +#endif static uint16_t get_dev_id(struct device *dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } - +#if 0 static int get_kbl_sku(void) { static int sku = -1; @@ -201,7 +202,6 @@ sku = -2; return sku; } - static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max) { /* If board provided non-zero value, use it. */ @@ -229,7 +229,7 @@ cfg = chip_cfg; else cfg = &default_configs[domain]; - +/* vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; vr_params->Psi1Threshold[domain] = cfg->psi1threshold; vr_params->Psi2Threshold[domain] = cfg->psi2threshold; @@ -240,9 +240,10 @@ vr_params->ImonOffset[domain] = cfg->imon_offset; vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; - +*/ #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) - vr_params->AcLoadline[domain] = cfg->ac_loadline; - vr_params->DcLoadline[domain] = cfg->dc_loadline; +// vr_params->AcLoadline[domain] = cfg->ac_loadline; +// vr_params->DcLoadline[domain] = cfg->dc_loadline; #endif } +#endif diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h index 6983469..af0950f 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h @@ -605,7 +605,7 @@ UINT64 ELR; // Exception Link Register UINT64 SPSR; // Saved Processor Status Register UINT64 FPSR; // Floating Point Status Register - UINT64 ESR; // Exception syndrome register +// UINT64 ESR; // Exception syndrome register UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h new file mode 100644 index 0000000..fca01e9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h @@ -0,0 +1,67 @@ +/** @file + Header file for Firmware Version Information + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h new file mode 100644 index 0000000..cf543fe --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h new file mode 100644 index 0000000..a66b3306 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -0,0 +1,248 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Tseg Size + Size of SMRAM memory reserved. + 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB +**/ + UINT8 PcdSmmTsegSize; + +/** Offset 0x0041 - FSP Debug Print Level + Select the FSP debug message print level. + 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG +**/ + UINT8 PcdFspDebugPrintErrorLevel; + +/** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_0_0; + +/** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_0_1; + +/** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_1_0; + +/** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_1_1; + +/** Offset 0x0046 - Enable Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 PcdMrcRmtSupport; + +/** Offset 0x0047 - RMT CPGC exp_loop_cnt + Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1). + 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 PcdMrcRmtCpgcExpLoopCntValue; + +/** Offset 0x0048 - RMT CPGC num_bursts + Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1). + 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 PcdMrcRmtCpgcNumBursts; + +/** Offset 0x0049 - Preserve Memory Across Reset + Enable/disable memory preservation across reset. + $EN_DIS +**/ + UINT8 PcdMemoryPreservation; + +/** Offset 0x004A - Fast Boot + Enable/disable Fast Boot function. Once enabled, all following boots will use the + presaved MRC data to improve the boot performance. + $EN_DIS +**/ + UINT8 PcdFastBoot; + +/** Offset 0x004B - ECC Support + Enable/disable ECC Support. + $EN_DIS +**/ + UINT8 PcdEccSupport; + +/** Offset 0x004C - HSUART Device + Select the PCI High Speed UART Device for Serial Port. + 0:HSUART0, 1:HSUART1, 2:HSUART2 +**/ + UINT8 PcdHsuartDevice; + +/** Offset 0x004D - Memory Down + Enable/disable Memory Down function. + $EN_DIS +**/ + UINT8 PcdMemoryDown; + +/** Offset 0x004E +**/ + UINT32 PcdMemoryDownConfigPtr; + +/** Offset 0x0052 - SATA Controller 0 + Enable/disable SATA Controller 0. + $EN_DIS +**/ + UINT8 PcdEnableSATA0; + +/** Offset 0x0053 - SATA Controller 1 + Enable/disable SATA Controller 1. + $EN_DIS +**/ + UINT8 PcdEnableSATA1; + +/** Offset 0x0054 - Intel Quick Assist Technology + Enable/disable Intel Quick Assist Technology. + $EN_DIS +**/ + UINT8 PcdEnableIQAT; + +/** Offset 0x0055 - SPD Write Disable + Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = [FORCE_DISABLE]) + 0:Force Enable, 1:Force Disable +**/ + UINT8 PcdSmbusSpdWriteDisable; + +/** Offset 0x0056 - ME_SHUTDOWN Message + Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP Integration Guide + for details. + $EN_DIS +**/ + UINT8 PcdEnableMeShutdown; + +/** Offset 0x0057 - XHCI Controller + Enable / Disable XHCI controller + $EN_DIS +**/ + UINT8 PcdEnableXhci; + +/** Offset 0x0058 - Memory Frequency + Set DDR Memory Frequency, refer to FSP Integration Guide for details.. + 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400 +**/ + UINT8 PcdDdrFreq; + +/** Offset 0x0059 - MMIO Size + Set memory mapped IO space size + 0:2048M, 1:1024M, 2:3072M +**/ + UINT8 PcdMmioSize; + +/** Offset 0x005A +**/ + UINT8 UnusedUpdSpace0[6]; + +/** Offset 0x0060 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 PcdCustomerRevision[32]; + +/** Offset 0x0080 - 32-Bit bus mode + Enable/Disable 32-Bit bus memory mode. + $EN_DIS +**/ + UINT8 PcdHalfWidthEnable; + +/** Offset 0x0081 - TCL Performance + Enable/Disable Tcl timing for performance. + $EN_DIS +**/ + UINT8 PcdTclIdle; + +/** Offset 0x0082 - Interleave Mode + Select Interleave Mode + 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2 +**/ + UINT8 PcdInterleaveMode; + +/** Offset 0x0083 - Memory Thermal Throttling + Enable/disable Memory Thermal Throttling management mode + $EN_DIS +**/ + UINT8 PcdMemoryThermalThrottling; + +/** Offset 0x0084 +**/ + UINT8 UnusedUpdSpace1[348]; + +/** Offset 0x01E0 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSPM_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSPM_CONFIG FspmConfig; + +/** Offset 0x01F0 +**/ + UINT8 UnusedUpdSpace2[14]; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h new file mode 100644 index 0000000..5d0b793 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -0,0 +1,192 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie0; + +/** Offset 0x0021 - PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie1; + +/** Offset 0x0022 - Active Core Count + Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) + 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, + 14:14, 15:15 +**/ + UINT8 PcdActiveCoreCount; + +/** Offset 0x0023 +**/ + UINT32 PcdCpuMicrocodePatchBase; + +/** Offset 0x0027 +**/ + UINT32 PcdCpuMicrocodePatchSize; + +/** Offset 0x002B - PCIe Controller 0 + Enable / Disable PCI Express controller 0 + $EN_DIS +**/ + UINT8 PcdEnablePcie0; + +/** Offset 0x002C - PCIe Controller 1 + Enable / Disable PCI Express controller 1 + $EN_DIS +**/ + UINT8 PcdEnablePcie1; + +/** Offset 0x002D - Embedded Multi-Media Controller (eMMC) + Enable / Disable Embedded Multi-Media controller + $EN_DIS +**/ + UINT8 PcdEnableEmmc; + +/** Offset 0x002E - LAN Controllers + Enable / Disable LAN controllers, refer to FSP Integration Guide for details. + 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +**/ + UINT8 PcdEnableGbE; + +/** Offset 0x002F +**/ + UINT32 PcdFiaMuxConfigRequestPtr; + +/** Offset 0x0033 +**/ + UINT8 UnusedUpdSpace0[4]; + +/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort0DeEmphasis; + +/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort1DeEmphasis; + +/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort2DeEmphasis; + +/** Offset 0x003A - PCIe Root Port 3 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort3DeEmphasis; + +/** Offset 0x003B - PCIe Root Port 4 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort4DeEmphasis; + +/** Offset 0x003C - PCIe Root Port 5 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort5DeEmphasis; + +/** Offset 0x003D - PCIe Root Port 6 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort6DeEmphasis; + +/** Offset 0x003E - PCIe Root Port 7 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort7DeEmphasis; + +/** Offset 0x003F +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0040 +**/ + UINT32 PcdEMMCDLLConfigPtr; + +/** Offset 0x0044 +**/ + UINT8 UnusedUpdSpace2[156]; + +/** Offset 0x00E0 +**/ + UINT8 ReservedSiliconInitUpd[16]; +} FSPS_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_CONFIG FspsConfig; + +/** Offset 0x00F0 +**/ + UINT8 UnusedUpdSpace3[14]; + +/** Offset 0x00FE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h new file mode 100644 index 0000000..340f144 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h @@ -0,0 +1,109 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0030 +**/ + UINT8 Reserved1[16]; +} FSPT_CORE_UPD; + +/** FSP-T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Disable Port80 output in FSP-T + Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 + Output, refer to FSP Integration Guide for details + 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output +**/ + UINT8 PcdFsptPort80RouteDisable; + +/** Offset 0x0041 +**/ + UINT8 ReservedTempRamInitUpd[31]; +} FSPT_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSPT_CONFIG FsptConfig; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace0[30]; + +/** Offset 0x007E +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda Gerrit-Change-Number: 31205 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002246 Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/g/drallion: Enable privacy screen on Drallion variant
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36045 ) Change subject: mb/g/drallion: Enable privacy screen on Drallion variant ...................................................................... mb/g/drallion: Enable privacy screen on Drallion variant Enable ACPI methods to control privacy screen on Drallion devices. Drallion devices may not have a privacy screen and it is up to the EC to determine if the privacy screen is present on the system. BUG=b:142656363 TEST=emerge-drallion coreboot chromeos-bootimage Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/include/variant/ec.h 4 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/36045/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 256f8cb..1de5ea5 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GFX if BOARD_GOOGLE_DRALLION select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5c2a5c9 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,6 +39,7 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <soc/intel/cannonlake/acpi/gfx.asl> } /* Per board variant mainboard hooks. */ #include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 1f628d6..184ab63 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -222,7 +222,19 @@ end device domain 0 on device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on + chip drivers/generic/gfx + register "device_count" = "1" + register "device[0].name" = ""LCD"" + register "device[0].addr" = "0x0400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.detect_function" = ""\\_SB.PCI0.LPCB.EC0.GPVD"" + register "device[0].privacy.status_function" = ""\\_SB.PCI0.LPCB.EC0.GPVX"" + register "device[0].privacy.enable_function" = ""\\_SB.PCI0.LPCB.EC0.EPVX"" + register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" + device generic 0 on end + end + end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h index 01a17b5..9cb8ed0 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/ec.h @@ -31,4 +31,7 @@ /* Enable DPTF */ #define EC_ENABLE_DPTF +/* Enable Privacy */ +#define EC_ENABLE_PRIVACY + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7 Gerrit-Change-Number: 36045 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019