coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in ...coreboot[master]: mainboard/asus: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33890 Change subject: mainboard/asus: remove stdlib.h when unused ...................................................................... mainboard/asus: remove stdlib.h when unused Change-Id: I5f0d6ed989fbaf3905680ba2661b167f845e5225 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/am1i-a/buildOpts.c M src/mainboard/asus/f2a85-m/BiosCallOuts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/asus/kcma-d8/get_bus_conf.c M src/mainboard/asus/kfsn4-dre/get_bus_conf.c M src/mainboard/asus/kgpe-d16/get_bus_conf.c M src/mainboard/asus/m4a78-em/get_bus_conf.c M src/mainboard/asus/m4a785-m/get_bus_conf.c M src/mainboard/asus/m5a88-v/get_bus_conf.c 10 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33890/1 diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index ce54741..5e54ac9 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -21,7 +21,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> #include <pc80/mc146818rtc.h> #include <types.h> diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 30c0699..74216f0 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 9e60ca7..15ce47e 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index dc20dc7..8a1391d 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -25,7 +25,6 @@ * */ -#include <stdlib.h> #include <vendorcode/amd/agesa/f15tn/AGESA.h> diff --git a/src/mainboard/asus/kcma-d8/get_bus_conf.c b/src/mainboard/asus/kcma-d8/get_bus_conf.c index cc64dea..8fd10a1 100644 --- a/src/mainboard/asus/kcma-d8/get_bus_conf.c +++ b/src/mainboard/asus/kcma-d8/get_bus_conf.c @@ -16,7 +16,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c index dd7ebc9..ea32741 100644 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/asus/kgpe-d16/get_bus_conf.c b/src/mainboard/asus/kgpe-d16/get_bus_conf.c index 81d0fc1..e1e07df 100644 --- a/src/mainboard/asus/kgpe-d16/get_bus_conf.c +++ b/src/mainboard/asus/kgpe-d16/get_bus_conf.c @@ -16,7 +16,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index 6b5ae68..7aca540 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0d6ed989fbaf3905680ba2661b167f845e5225 Gerrit-Change-Number: 33890 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: mainboard/hp: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33894 Change subject: mainboard/hp: remove stdlib.h when unused ...................................................................... mainboard/hp: remove stdlib.h when unused Change-Id: Ie0a65b6a631aa9158fa7f432b5cd7967a518fa11 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/abm/BiosCallOuts.c M src/mainboard/hp/abm/buildOpts.c M src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c 5 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/33894/1 diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 4728c59..df0cb34 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -18,7 +18,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index bc1b172..f965d0d 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -30,7 +30,6 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include <stdlib.h> #include <AGESA.h> #define INSTALL_FT3_SOCKET_SUPPORT TRUE diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index e217aa7..c159c19 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 2b1ac04..afa2fce 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -16,10 +16,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/state_machine.h> - #include <southbridge/amd/agesa/hudson/imc.h> #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <stdlib.h> const BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index c6d62ed..e56d513 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -27,7 +27,6 @@ #include "mainboard.h" -#include <stdlib.h> #include <vendorcode/amd/agesa/f15tn/AGESA.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0a65b6a631aa9158fa7f432b5cd7967a518fa11 Gerrit-Change-Number: 33894 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: mainboard/jetway: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33896 Change subject: mainboard/jetway: remove stdlib.h when unused ...................................................................... mainboard/jetway: remove stdlib.h when unused Change-Id: I8e3e8071f9b46ea6857b906a442b5e7a668f5188 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/buildOpts.c M src/mainboard/jetway/pa78vm5/get_bus_conf.c 3 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33896/1 diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 86999fb..d71e5d8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -15,11 +15,9 @@ #include <AGESA.h> #include <northbridge/amd/agesa/BiosCallOuts.h> - #include <amdlib.h> #include <vendorcode/amd/cimx/sb800/SB800.h> #include <stdint.h> -#include <stdlib.h> static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 65986e2..1ad822a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -25,8 +25,6 @@ * */ -#include <stdlib.h> - #include <vendorcode/amd/agesa/f14/AGESA.h> /* Include the files that instantiate the configuration definitions. */ @@ -41,7 +39,6 @@ #include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> - /* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable -- To view, visit https://review.coreboot.org/c/coreboot/+/33896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e3e8071f9b46ea6857b906a442b5e7a668f5188 Gerrit-Change-Number: 33896 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: src/lib: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33692 Change subject: src/lib: Use 'include <stdlib.h>' when appropriate ...................................................................... src/lib: Use 'include <stdlib.h>' when appropriate Change-Id: I364bbb31e95958df2ac8188ba5618f4f1c3427a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/bootmem.c M src/lib/cbfs.c M src/lib/fit.c M src/lib/fit_payload.c M src/lib/imd.c M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/lib/rmodule.c M src/lib/selfboot.c 9 files changed, 10 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/33692/1 diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 01ad3e8..61253cf 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -19,7 +19,7 @@ #include <bootmem.h> #include <cbmem.h> #include <device/resource.h> -#include <stdlib.h> +#include <stddef.h> #include <symbols.h> #include <assert.h> diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..001d80f 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -17,12 +17,13 @@ #include <assert.h> #include <console/console.h> #include <string.h> -#include <stdlib.h> #include <boot_device.h> #include <cbfs.h> #include <commonlib/compression.h> #include <endian.h> #include <lib.h> +#include <stddef.h> +#include <stdint.h> #include <symbols.h> #include <timestamp.h> #include <fmap.h> diff --git a/src/lib/fit.c b/src/lib/fit.c index 045f52f..77bd766 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -20,7 +20,7 @@ #include <endian.h> #include <stdint.h> #include <bootmem.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> #include <program_loading.h> #include <memrange.h> diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 8e75915..1cf5ed8 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -19,10 +19,10 @@ #include <bootmem.h> #include <cbmem.h> #include <device/resource.h> -#include <stdlib.h> #include <commonlib/region.h> #include <fit.h> #include <program_loading.h> +#include <stddef.h> #include <timestamp.h> #include <string.h> #include <commonlib/cbfs_serialized.h> diff --git a/src/lib/imd.c b/src/lib/imd.c index 17ec2d9..de91f2a 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -17,7 +17,7 @@ #include <cbmem.h> #include <console/console.h> #include <imd.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> /* For more details on implementation and usage please see the imd.h header. */ diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 1a67ad5..6ec2150 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -19,8 +19,8 @@ #include <cbmem.h> #include <imd.h> #include <lib.h> -#include <stdlib.h> #include <arch/early_variables.h> +#include <stddef.h> /* * We need special handling on x86 where CAR global migration is employed. One diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 81ec2ec..b39d016 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -14,7 +14,6 @@ */ -#include <stdlib.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -26,6 +25,7 @@ #include <romstage_handoff.h> #include <rmodule.h> #include <stage_cache.h> +#include <stddef.h> #include <symbols.h> #include <timestamp.h> #include <fit_payload.h> diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 56529d2..a34bac7 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -15,8 +15,8 @@ #include <assert.h> #include <cbmem.h> #include <cbfs.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <console/console.h> #include <program_loading.h> diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index a0bb711..2d64634 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -18,8 +18,8 @@ #include <commonlib/compression.h> #include <commonlib/endian.h> #include <console/console.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <symbols.h> #include <cbfs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364bbb31e95958df2ac8188ba5618f4f1c3427a4 Gerrit-Change-Number: 33692 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: src/ec: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33693 Change subject: src/ec: Use 'include <stdlib.h>' when appropriate ...................................................................... src/ec: Use 'include <stdlib.h>' when appropriate Change-Id: I416f017b973ab4968a1d7028d741ee7054062a70 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/vstore.c M src/ec/google/wilco/chip.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33693/1 diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index b7d183e..28b9797 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -19,8 +19,8 @@ #include <delay.h> #include <device/pnp.h> #include <ec/google/common/mec.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include "chip.h" #include "ec.h" diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 28c2603..d1f90b1 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> #include <string.h> -#include <stdlib.h> #include "ec.h" #include "ec_commands.h" diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 09211f8..d27a3a7 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -21,8 +21,8 @@ #include <device/pnp.h> #include <ec/acpi/ec.h> #include <pc80/keyboard.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include "commands.h" #include "ec.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I416f017b973ab4968a1d7028d741ee7054062a70 Gerrit-Change-Number: 33693 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: {gm45,pineview,x4x}: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32586 Change subject: {gm45,pineview,x4x}: Remove redundant use of ACPI offset operator ...................................................................... {gm45,pineview,x4x}: Remove redundant use of ACPI offset operator Change-Id: Ie7a9df2275d9e02bc2793064903228c8cac4d17f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/x4x/acpi/hostbridge.asl 3 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32586/1 diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index afa7a61..624ca99 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -56,32 +56,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), // PAM1 + // PAM1 PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), // PAM2 + // PAM2 PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), // PAM3 + // PAM3 PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), // PAM4 + // PAM4 PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), // PAM5 + // PAM5 PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), // PAM6 + // PAM6 PM6L, 2, , 2, PM6H, 2, diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 3eff101..5fe1453 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -56,32 +56,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), /* PAM1 */ + /* PAM1 */ PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), /* PAM2 */ + /* PAM2 */ PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), /* PAM3 */ + /* PAM3 */ PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), /* PAM4 */ + /* PAM4 */ PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), /* PAM5 */ + /* PAM5 */ PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), /* PAM6 */ + /* PAM6 */ PM6L, 2, , 2, PM6H, 2, diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index 90f15c7..1e43511 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -57,32 +57,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), // PAM1 + // PAM1 PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), // PAM2 + // PAM2 PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), // PAM3 + // PAM3 PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), // PAM4 + // PAM4 PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), // PAM5 + // PAM5 PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), // PAM6 + // PAM6 PM6L, 2, , 2, PM6H, 2, -- To view, visit https://review.coreboot.org/c/coreboot/+/32586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a9df2275d9e02bc2793064903228c8cac4d17f Gerrit-Change-Number: 32586 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[master]: mb/oogle/beltino: Remove #include <stdlib.h> when not used
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33699 Change subject: mb/oogle/beltino: Remove #include <stdlib.h> when not used ...................................................................... mb/oogle/beltino: Remove #include <stdlib.h> when not used Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/romstage.c M src/mainboard/google/beltino/variants/mccloud/hda_verb.c M src/mainboard/google/beltino/variants/monroe/hda_verb.c M src/mainboard/google/beltino/variants/panther/hda_verb.c M src/mainboard/google/beltino/variants/tricky/hda_verb.c M src/mainboard/google/beltino/variants/zako/hda_verb.c 6 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33699/1 diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..ac6cdb5 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <cpu/intel/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 8482ec3..8281fb8 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Gerrit-Change-Number: 33699 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/google/hatch: Support separate fixed PL1 setting for tablet mode
by shkim (Code Review) 28 Nov '19

28 Nov '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35533 to review the following change. Change subject: mb/google/hatch: Support separate fixed PL1 setting for tablet mode ...................................................................... mb/google/hatch: Support separate fixed PL1 setting for tablet mode Some variants need separate PL1 setting since thier thermal tuning, but DPTF passive policy 1.0 cannot support it. So we would use MMIO PL1 register which is currently unused, it can reserve another PL1 setting for tablet mode. If the MMIO PL1 setting is lower than DPTF PL1 max setting, it will limit PL1 when DPTF sets higher PL1 in tablet mode. Otherwise, if the MMIO PL1 setting is lower than DPTF PL1 min setting, system will have a fixed PL1 value in tablet mode. BUG=b:138395625 BRANCH=none TEST=Verified MMIO PL1 value and it's enabled in tablet mode when it set Change-Id: I81c33f9df3e5431f04a08395141b5dc989474289 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/hatch/mainboard.asl M src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/cpu.c 5 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35533/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 962988e..0c4cc35 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -378,6 +378,9 @@ #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) #endif +#ifdef EC_ENABLE_MAINBOERD_TABLET_MODE_EVENT + \_SB.MTME(^TBMD) +#endif } /* diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl index dff1a75..769d429 100644 --- a/src/mainboard/google/hatch/mainboard.asl +++ b/src/mainboard/google/hatch/mainboard.asl @@ -55,3 +55,22 @@ LOCL (0) } } + +/* + * Additional action for tablet mode switch event + * Called from \_SB.PCI0.LPCB.EC0._Q1D + */ +Method (MTME, 1, Serialized) +{ + OperationRegion (MCHB, + SystemMemory, Add (\_SB.PCI0.GMHB(), 0x5000), 0x1000) + Field (MCHB, DWordAcc, Lock, Preserve) + { + Offset (0x9a0), /* PKG_POWER_LIMIT_LO */ + , 15, /* PKG_POWER_LIMIT_MASK */ + MP1E, 1, /* PKG_POWER_LIMIT_EN */ + } + + /* Enable MMIO PL1 at tablet mode */ + Store(Arg0, MP1E) +} diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index 84e050e..7cc5269 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -19,5 +19,6 @@ #include <baseboard/ec.h> #define EC_ENABLE_MULTIPLE_DPTF_PROFILES +#define EC_ENABLE_MAINBOERD_TABLET_MODE_EVENT #endif diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 451c920..df6be35 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -232,6 +232,8 @@ /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; + /* PL1 MMIO Override value in Watts */ + uint32_t mmio_pl1_override; /* PL2 Override value in Watts */ uint32_t tdp_pl2_override; /* SysPL2 Value in Watts */ diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0f4d52e..4ec45e5 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -160,6 +160,13 @@ limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; + /* Set PL1 MMIO override value */ + if (conf->mmio_pl1_override) { + tdp_pl1 = (conf->mmio_pl1_override * power_unit); + limit.lo &= (~(PKG_POWER_LIMIT_MASK)); + limit.lo |= tdp_pl1 & PKG_POWER_LIMIT_MASK; + } + /* Power limit 2 time is only programmable on server SKU */ wrmsr(MSR_PKG_POWER_LIMIT, limit); -- To view, visit https://review.coreboot.org/c/coreboot/+/35533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81c33f9df3e5431f04a08395141b5dc989474289 Gerrit-Change-Number: 35533 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: shkim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: mb/google/kohaku: Set mmio_pl1_override value for tablet mode
by shkim (Code Review) 28 Nov '19

28 Nov '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35534 to review the following change. Change subject: mb/google/kohaku: Set mmio_pl1_override value for tablet mode ...................................................................... mb/google/kohaku: Set mmio_pl1_override value for tablet mode This change limits PL1 to 5W in tablet mode for kohaku. BUG=b:138395625 BRANCH=none TEST=Verified PL1 is limited in tablet mode Change-Id: I79bea32cf46ffa50f83af3905f85a471cb94b339 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35534/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 8c7bb1f..9614ef8 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -1,6 +1,7 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "8" register "tdp_pl2_override" = "51" + register "mmio_pl1_override" = "5" register "tcc_offset" = "35" # TCC of 65C -- To view, visit https://review.coreboot.org/c/coreboot/+/35534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79bea32cf46ffa50f83af3905f85a471cb94b339 Gerrit-Change-Number: 35534 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]
by Surendranath R Gurivireddy (Code Review) 27 Nov '19

27 Nov '19

Surendranath R Gurivireddy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36519 ) Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP] ...................................................................... soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP] Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy(a)intel.com> Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36519/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4..27b109d 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -273,6 +273,9 @@ params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } + /* Disable USB2 PHY Power gating */ + params->PchUsb2PhySusPgEnable = 0; + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; -- To view, visit https://review.coreboot.org/c/coreboot/+/36519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Gerrit-Change-Number: 36519 Gerrit-PatchSet: 1 Gerrit-Owner: Surendranath R Gurivireddy <surendranath.r.gurivireddy(a)intel.com> Gerrit-MessageType: newchange

8 37

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019