coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ec/google/wilco: Add placeholder methods for privacy screen
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36044 ) Change subject: ec/google/wilco: Add placeholder methods for privacy screen ...................................................................... ec/google/wilco: Add placeholder methods for privacy screen Add placeholder ACPI methods to the Wilco EC for controlling a privacy screen on the device. These methods will be updteded when the EC has commands to control the screen. BUG=b:142237145, b:142656363 TEST=none Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/ec/google/wilco/acpi/ec.asl A src/ec/google/wilco/acpi/privacy.asl 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36044/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 532f421..8fcd0dd 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -178,4 +178,7 @@ #ifdef EC_ENABLE_DPTF #include "dptf.asl" #endif +#ifdef EC_ENABLE_PRIVACY + #include "privacy.asl" +#endif } diff --git a/src/ec/google/wilco/acpi/privacy.asl b/src/ec/google/wilco/acpi/privacy.asl new file mode 100644 index 0000000..2121d23 --- /dev/null +++ b/src/ec/google/wilco/acpi/privacy.asl @@ -0,0 +1,25 @@ +/* Read Privacy Screen Present */ +Method (GPVD, 0, Serialized) +{ + Printf ("Read Privacy Screen Present") + Return (One) +} + +/* Read Privacy Screen Status */ +Method (GPVX, 0, Serialized) +{ + Printf ("Read Privacy Screen Status") + Return (0x0) +} + +/* Enable Privacy Screen */ +Method (EPVX, 0, Serialized) +{ + Printf ("Enable Privacy Screen") +} + +/* Disable Privacy Screen */ +Method (DPVX, 0, Serialized) +{ + Printf ("Disable Privacy Screen") +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Gerrit-Change-Number: 36044 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Add gfx.asl file
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36043 ) Change subject: soc/intel/cannonlake: Add gfx.asl file ...................................................................... soc/intel/cannonlake: Add gfx.asl file Add gfx.asl file for cannonlake SOCs to allow for graphics related ACPI devices and methods on cannonlake devices. BUG=b:142237145 TEST=gfx.asl added to drallion dsdt.asl Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- A src/soc/intel/cannonlake/acpi/gfx.asl 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/36043/1 diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/cannonlake/acpi/gfx.asl new file mode 100644 index 0000000..fef28f0 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/gfx.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Gerrit-Change-Number: 36043 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: soc/intel: Intel graphics driver scans generic bus
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36042 ) Change subject: soc/intel: Intel graphics driver scans generic bus ...................................................................... soc/intel: Intel graphics driver scans generic bus This change allows for Intel graphics devices to use drivers/generic/gfx driver to populate ACPI SSDT table for common graphics related devices and methods. BUG=b:142237145 TEST=On sarien_cml add generic/gfx to the devicetree and device is enumerated and correct SSDT ASL is observed. Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/soc/intel/common/block/graphics/graphics.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36042/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 8e79eab..82133ff 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -118,6 +118,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .scan_bus = scan_generic_bus, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Gerrit-Change-Number: 36042 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: drivers/gfx: Add generic graphics with SSDT generator
by Mathew King (Code Review) 02 Dec '19

02 Dec '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36041 ) Change subject: drivers/gfx: Add generic graphics with SSDT generator ...................................................................... drivers/gfx: Add generic graphics with SSDT generator This change adds a generic graphics driver that can be added to a devicetree which populates graphics related ACPI table. It will write the _DOD method (Enumerate All Devices Attached to the Display Adapter) and a device object for each device defined. The device may optionally have a connected privacy screen which can be controlled with a _DSM. Example: chip drivers/generic/gfx register "device_count" = "1" register "device[0].name" = ""LCD"" register "device[0].addr" = "0x0400" register "device[0].privacy.enabled" = "1" register "device[0].privacy.detect_function" = ""\\_SB.PCI0.PVSC.GPVD"" register "device[0].privacy.status_function" = ""\\_SB.PCI0.PVSC.GPVX"" register "device[0].privacy.enable_function" = ""\\_SB.PCI0.PVSC.EPVX"" register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end ASL Scope (\_SB.PCI0.GFX0) { Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices { Return (Package (0x01) { 0x00000400 }) } Device (LCD) { Name (_HID, "GOOG0010") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_ADR, 0x0400) // _ADR: Address Name (_STA, 0x0F) // _STA: Status Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c7033113-8720-4ceb-9090-9d52b3e52d73"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Local2 = \_SB.PCI0.PVSC.GPVD () If ((Local2 == One)) { Return (Buffer (One) { 0x0F }) } } If ((Local1 == One)) { ToBuffer (\_SB.PCI0.PVSC.GPVX (), Local2) Return (Local2) } If ((Local1 == 0x02)) { \_SB.PCI0.PVSC.EPVX () } If ((Local1 == 0x03)) { \_SB.PCI0.PVSC.DPVX () } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } } } BUG=b:142237145 TEST=Added gfx to devicetree on sarien_cml and correct ASL in SSDT Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- A src/drivers/generic/gfx/Kconfig A src/drivers/generic/gfx/Makefile.inc A src/drivers/generic/gfx/chip.h A src/drivers/generic/gfx/gfx.c 4 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/36041/1 diff --git a/src/drivers/generic/gfx/Kconfig b/src/drivers/generic/gfx/Kconfig new file mode 100644 index 0000000..f59275a --- /dev/null +++ b/src/drivers/generic/gfx/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_GENERIC_GFX + bool + default n + depends on HAVE_ACPI_TABLES \ No newline at end of file diff --git a/src/drivers/generic/gfx/Makefile.inc b/src/drivers/generic/gfx/Makefile.inc new file mode 100644 index 0000000..c31986b --- /dev/null +++ b/src/drivers/generic/gfx/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_GFX) += gfx.c diff --git a/src/drivers/generic/gfx/chip.h b/src/drivers/generic/gfx/chip.h new file mode 100644 index 0000000..1d8f909 --- /dev/null +++ b/src/drivers/generic/gfx/chip.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__ +#define __DRIVERS_GENERIC_GFX_CHIP_H__ + +struct drivers_generic_gfx_privacy_screen_config +{ + int enabled; + const char *detect_function; + const char *status_function; + const char *enable_function; + const char *disable_function; +}; + +struct drivers_generic_gfx_device_config +{ + const char *name; + int addr; + struct drivers_generic_gfx_privacy_screen_config privacy; +}; + + +struct drivers_generic_gfx_config { + int device_count; + struct drivers_generic_gfx_device_config device[5]; +}; + +#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */ diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c new file mode 100644 index 0000000..40fc871 --- /dev/null +++ b/src/drivers/generic/gfx/gfx.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#define ACPI_DSM_PRIVACY_SCREEN_UUID "C7033113-8720-4CEB-9090-9D52B3E52D73" + +static void privacy_screen_detect_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_write_store(); + acpigen_emit_namestring(config->detect_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); + acpigen_write_return_singleton_buffer(0xF); + acpigen_pop_len(); +} +static void privacy_screen_get_status_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_byte(TO_BUFFER_OP); + acpigen_emit_namestring(config->status_function); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL2_OP); +} +static void privacy_screen_enable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->enable_function); +} +static void privacy_screen_disable_cb(void *arg) +{ + struct drivers_generic_gfx_privacy_screen_config *config = arg; + + acpigen_emit_namestring(config->disable_function); +} + +static void (*privacy_screen_callbacks[])(void *) = { + privacy_screen_detect_cb, + privacy_screen_get_status_cb, + privacy_screen_enable_cb, + privacy_screen_disable_cb, +}; + +static void gfx_fill_ssdt_generator(struct device *dev) +{ + size_t i; + struct drivers_generic_gfx_config *config = dev->chip_info; + + const char *scope = acpi_device_scope(dev); + + acpigen_write_scope(scope); + + /* Method (_DOD, 0) */ + acpigen_write_method("_DOD", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(config->device_count); + for (i = 0; i < config->device_count; i++) { + acpigen_write_dword (config->device[i].addr); + } + acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ + + for (i = 0; i < config->device_count; i++) { + acpigen_write_device(config->device[i].name); + + acpigen_write_name_integer("_ADR", config->device[i].addr); + acpigen_write_name_integer("_STA", 0xF); + + if (config->device[i].privacy.enabled) { + acpigen_write_dsm(ACPI_DSM_PRIVACY_SCREEN_UUID, + privacy_screen_callbacks, + ARRAY_SIZE(privacy_screen_callbacks), + &config->device[i].privacy); + } + + acpigen_pop_len(); /* Device */ + } + acpigen_pop_len(); /* Scope */ +} + +static const char *gfx_acpi_name(const struct device *dev) +{ + return "GFX0"; +} + +static struct device_operations gfx_ops = { + .acpi_name = gfx_acpi_name, + .acpi_fill_ssdt_generator = gfx_fill_ssdt_generator, +}; + +static void gfx_enable(struct device *dev) +{ + struct drivers_generic_gfx_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &gfx_ops; +} + +struct chip_operations drivers_generic_gfx_ops = { + CHIP_NAME("Graphics Device") + .enable_dev = gfx_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida520dd7aad81ee7c1e5f2d0d3f5cc1a766d78a0 Gerrit-Change-Number: 36041 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

6 35

Change in ...coreboot[master]: src: Move 'static' is at beginning of declaration
by HAOUAS Elyes (Code Review) 02 Dec '19

02 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33673 Change subject: src: Move 'static' is at beginning of declaration ...................................................................... src: Move 'static' is at beginning of declaration Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo/platform_cfg.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_crtm.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/intel/fsp_broadwell_de/gpio.c 7 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33673/1 diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 57b1aec..c56b537 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -212,7 +212,7 @@ */ #define GEC_CONFIG 0 -const static CODECENTRY gizmo_codec_alc272[] = +static const CODECENTRY gizmo_codec_alc272[] = { /* NID, PinConfig */ {0x11, 0x411111F0}, /* S/PDIF-OUT2 unused */ diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..a1ba310 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -88,7 +88,7 @@ } } -const static u8 max_tap[3] = {12, 10, 13}; +static const u8 max_tap[3] = {12, 10, 13}; static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) @@ -540,7 +540,7 @@ u32 emrs1; /* Is shifted by bits 2 later so u8 can be used to reduce size */ - const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + static const u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 32618e8..8ca6ec1 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -437,7 +437,7 @@ 5200 }; - const static u8 ddr3_turnaround_tab[3][6][4] = { + static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ @@ -459,7 +459,7 @@ }; /* [DDR freq][0x26F & 1][pagemod] */ - const static u8 ddr2_x252_tab[2][2][2] = { + static const u8 ddr2_x252_tab[2][2][2] = { { /* DDR2 667 */ {12, 16}, {14, 18} @@ -470,7 +470,7 @@ } }; - const static u8 ddr3_x252_tab[3][2][2] = { + static const u8 ddr3_x252_tab[3][2][2] = { { /* DDR3 800 */ {16, 20}, {18, 22} diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd614..50da155 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -173,7 +173,7 @@ * i.e. those which should not be possible to delete or modify once * the RO exits, and the rest of the NVRAM spaces. */ -const static TPMA_NV ro_space_attributes = { +static const TPMA_NV ro_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -182,7 +182,7 @@ .TPMA_NV_POLICY_DELETE = 1, }; -const static TPMA_NV rw_space_attributes = { +static const TPMA_NV rw_space_attributes = { .TPMA_NV_PPWRITE = 1, .TPMA_NV_AUTHREAD = 1, .TPMA_NV_PPREAD = 1, @@ -193,7 +193,7 @@ * This policy digest was obtained using TPM2_PolicyPCR * selecting only PCR_0 with a value of all zeros. */ -const static uint8_t pcr0_unchanged_policy[] = { +static const uint8_t pcr0_unchanged_policy[] = { 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..f68ab0a4 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -29,7 +29,7 @@ { int i; struct region_device fmap; - const static char *fmap_cbfs_names[] = { + static const char *fmap_cbfs_names[] = { "COREBOOT", "FW_MAIN_A", "FW_MAIN_B", diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 45408ea..e1df91f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -44,7 +44,7 @@ * waiting for each device to become available, a single delay will be * executed. */ -const static struct stoneyridge_aoac aoac_devs[] = { +static const struct stoneyridge_aoac aoac_devs[] = { { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, @@ -116,7 +116,7 @@ * amd_pci_int_defs.h, just add the pair at the end of this table. * Order is not important. */ -const static struct irq_idx_name irq_association[] = { +static const struct irq_idx_name irq_association[] = { { PIRQ_A, "INTA#" }, { PIRQ_B, "INTB#" }, { PIRQ_C, "INTC#" }, diff --git a/src/soc/intel/fsp_broadwell_de/gpio.c b/src/soc/intel/fsp_broadwell_de/gpio.c index 41100e9..01c4d9e 100644 --- a/src/soc/intel/fsp_broadwell_de/gpio.c +++ b/src/soc/intel/fsp_broadwell_de/gpio.c @@ -24,7 +24,7 @@ #include <soc/gpio.h> /* Use a wrapper for register addresses for different banks. */ -const static struct gpio_config_regs regs[GPIO_NUM_BANKS] = { +static const struct gpio_config_regs regs[GPIO_NUM_BANKS] = { [0] = { .use_sel = GPIO_1_USE_SEL, .io_sel = GPIO_1_IO_SEL, .level = GPIO_1_LVL, .nmi_en = GPIO_1_NMI_EN, .blink_en = GPIO_1_BLINK, .invert_input = GPIO_1_INVERT }, -- To view, visit https://review.coreboot.org/c/coreboot/+/33673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Gerrit-Change-Number: 33673 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch
by Kane Chen (Code Review) 02 Dec '19

02 Dec '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35596 ) Change subject: mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch ...................................................................... mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode. VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted. This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can program related setttings to save power. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: Ia02ff8823883489b36349457213409496f082f36 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35596/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..a2831e1 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -58,6 +58,8 @@ register "PmTimerDisabled" = "1" + register "PchPmSlpS0Vm075VSupport" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/c/coreboot/+/35596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia02ff8823883489b36349457213409496f082f36 Gerrit-Change-Number: 35596 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: [DO NOT SUBMIT] Dump full calibration params
by Yu-Ping Wu (Code Review) 02 Dec '19

02 Dec '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35618 ) Change subject: [DO NOT SUBMIT] Dump full calibration params ...................................................................... [DO NOT SUBMIT] Dump full calibration params This patch is only for debugging. Change-Id: I04ec044776f2168a149a21a199b0adb0aa68e46f Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h 4 files changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35618/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c old mode 100644 new mode 100755 index 2fbc789..0359887 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -108,6 +108,9 @@ if (err == 0) { printk(BIOS_INFO, "successfully load dram_blob and " "run DRAM calibration\n"); + just_for_test_dump_coreboot_params(&freq_params[DRAM_DFS_SHUFFLE_1]); + just_for_test_dump_coreboot_params(&freq_params[DRAM_DFS_SHUFFLE_2]); + just_for_test_dump_coreboot_params(&freq_params[DRAM_DFS_SHUFFLE_3]); write_calibration_data_to_flash(freq_params); return; } diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig old mode 100644 new mode 100755 index 576f2d5..ba65aa5 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -19,7 +19,7 @@ config DEBUG_DRAM bool "Output verbose DRAM related debug messages" - default n + default y help This option enables additional DRAM related debug messages. diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c old mode 100644 new mode 100755 index dfd59b1..1b0c120 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -65,6 +65,9 @@ bool have_calibration_params(const struct sdram_params *params) { + dramc_show("calibration_result_start:%#x, calibration_result_end:%#x\n", + params->calibration_result_start, + params->calibration_result_end); return (params->calibration_result_start == PARAM_START_PATTERN && params->calibration_result_end == PARAM_END_PATTERN); } @@ -477,6 +480,48 @@ } #endif +void just_for_test_dump_coreboot_params(const struct sdram_params *params) +{ + dramc_show("%s dump params calibration_result_start\n", __func__); + dramc_show("calibration_result_start = 0x%x\n", params->calibration_result_start); + + dramc_show("dump params frequency:%d\n", params->frequency); + + dramc_show("\n dump params write leveling\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 rk = 0; rk < 2; rk++) + for (u8 dqs = 0; dqs < 2; dqs++) + dramc_show("write leveling[%d][%d][%d] = 0x%x\n", + chn, rk, dqs, params->wr_level[chn][rk][dqs]); + + dramc_show("dump params cbt_cs\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 rk = 0; rk < 2; rk++) + dramc_show("cbt_cs[%d][%d] = 0x%x\n", + chn, rk, params->cbt_cs_dly[chn][rk]); + + dramc_show("dump params cbt_mr12\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 rk = 0; rk < 2; rk++) + dramc_show("cbt_mr12[%d][%d] = 0x%x\n", + chn, rk, params->cbt_final_vref[chn][rk]); + + dramc_show("dump params clk_delay\n"); + for (u8 chn = 0; chn < 2; chn++) + dramc_show("clk_delay[%d] = %d\n", chn, params->duty_clk_delay[chn]); + + dramc_show("dump params dqs_delay\n"); + for (u8 chn = 0; chn < 2; chn++) + for (u8 dqs = 0; dqs < 2; dqs++) + dramc_show("dqs_delay[%d][%d] = %d\n", + chn, dqs, params->duty_dqs_delay[chn][dqs]); + + dramc_show("dump params delay_cell_unit\n"); + dramc_show("delay_cell_unit = %d\n", params->delay_cell_unit); + dramc_show("calibration_result_end = 0x%x\n", params->calibration_result_end); + +} + void mt_set_emi(const struct sdram_params *freq_params) { int freq_shuffle = DRAM_DFS_SHUFFLE_1; @@ -489,6 +534,8 @@ u8 current_freqsel = freq_tbl[freq_shuffle]; params = &freq_params[freq_shuffle]; + just_for_test_dump_coreboot_params(params); + init_dram(params, current_freqsel); do_calib(params, current_freqsel); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h old mode 100644 new mode 100755 index cdaadbc..55a2b0e --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -88,4 +88,7 @@ bool have_calibration_params(const struct sdram_params *params); void clean_calibration_data(void); +void just_for_test_dump_coreboot_params(const struct sdram_params *params); + + #endif /* SOC_MEDIATEK_MT8183_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04ec044776f2168a149a21a199b0adb0aa68e46f Gerrit-Change-Number: 35618 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: crossgcc: Upgrade acpica to version 20190816
by HAOUAS Elyes (Code Review) 29 Nov '19

29 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34907 ) Change subject: crossgcc: Upgrade acpica to version 20190816 ...................................................................... crossgcc: Upgrade acpica to version 20190816 Changes: https://acpica.org/node/172 Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20190816_iasl.patch D util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/34907/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3b..0443ddb 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.3 -IASL_VERSION=20190703 +IASL_VERSION=20190816 PYTHON_VERSION=3.7.4 EXPAT_VERSION=2.2.7 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190816_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20190703_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190816_iasl.patch index 0f60974..01c66c7 100644 --- a/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190816_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20190703_/source/compiler/asloptions.c acpica-unix2-20190703/source/compiler/asloptions.c > acpica-unix2-20190703_iasl.patch ---- acpica-unix2-20190703_/source/compiler/asloptions.c -+++ acpica-unix2-20190703/source/compiler/asloptions.c +diff -Naur acpica-unix2-20190816_/source/compiler/asloptions.c acpica-unix2-20190816/source/compiler/asloptions.c > acpica-unix2-20190816_iasl.patch +--- acpica-unix2-20190816_/source/compiler/asloptions.c ++++ acpica-unix2-20190816/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum deleted file mode 100644 index 9a89796..0000000 --- a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum new file mode 100644 index 0000000..013541c --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum @@ -0,0 +1 @@ +fd8bc7ebb340d9c68279b3558158e7286294a72c tarballs/acpica-unix2-20190816.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/34907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c Gerrit-Change-Number: 34907 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 14

Change in ...coreboot[master]: soc/intel/braswell: Use sb/intel/common/spi
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33205 Change subject: soc/intel/braswell: Use sb/intel/common/spi ...................................................................... soc/intel/braswell: Use sb/intel/common/spi Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc D src/soc/intel/braswell/spi.c 3 files changed, 1 insertion(+), 586 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33205/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b2702f0..da0d7db 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -51,6 +51,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e479a3c..7f03b06 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -15,12 +15,10 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c -romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += memmap.c postcar-y += iosf.c -postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c @@ -45,7 +43,6 @@ ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += xhci.c @@ -54,7 +51,6 @@ smm-y += lpc_init.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += tsc_freq.c verstage-y += pmutil.c diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c deleted file mode 100644 index b968283..0000000 --- a/src/soc/intel/braswell/spi.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright (c) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <bootstate.h> -#include <commonlib/helpers.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <stdint.h> -#include <stdlib.h> - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%2.2x\n", addr, v); - return v; -} - -static u16 readw_(void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%4.4x\n", addr, v); - return v; -} - -static u32 readl_(void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%8.8x\n", addr, v); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%2.2x\n", addr, b); - write8(addr, b); -} - -static void writew_(u16 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%4.4x\n", addr, b); - write16(addr, b); -} - -static void writel_(u32 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%8.8x\n", addr, b); - write32(addr, b); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(void *src, void *value, uint32_t size) -{ - uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - if (!dev) { - printk(BIOS_ERR, "%s: PCI device not found", __func__); - return NULL; - } - - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -void spi_init(void) -{ - ich9_spi_regs *ich9_spi; - - ich9_spi = spi_regs(); - if (!ich9_spi) { - printk(BIOS_ERR, "Not initialising spi as %s returned NULL\n", - __func__); - return; - } - - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.preop = &ich9_spi->preop; -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } - - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", - trans->type); - return -1; - } -} - -/* - * Wait for up to 400ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; - - wait_til_set &= 1; - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_ERR, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - opcode_index = spi_setup_opcode(&trans); - if (opcode_index < 0) - return -1; - with_address = spi_setup_offset(&trans); - if (with_address < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_ERR, "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, - "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_ERR, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/33205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Gerrit-Change-Number: 33205 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 13

Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432 Change subject: drivers/smmstore: Fix some issues ...................................................................... drivers/smmstore: Fix some issues This fixes the following: - Make the API ARCH independent (no dependency on size_t) - clean up the code a little Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/store.c M src/include/smmstore.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 86 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1 diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 409949a..0a62b3c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -62,8 +62,8 @@ if (cbfs_locate_file_in_region(&file, CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", + printk(BIOS_WARNING, + "smm store: Unable to find SMM store file in region '%s'\n", CONFIG_SMMSTORE_REGION); return -1; } @@ -87,14 +87,13 @@ * returns 0 on success, -1 on failure * writes up to `*bufsize` bytes into `buf` and updates `*bufsize` */ -int smmstore_read_region(void *buf, ssize_t *bufsize) +int smmstore_read_region(void *buf, uint32_t *bufsize) { struct region_device store; if (bufsize == NULL) return -1; - *bufsize = 0; if (lookup_store(&store) < 0) { printk(BIOS_WARNING, "reading region failed\n"); return -1; @@ -109,6 +108,66 @@ return 0; } +static enum cb_err scan_end(ssize_t *end) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); + return CB_ERR; + } + ssize_t data_sz = region_device_sz(&store); + + /* scan for end */ + *end = 0; + uint32_t k_sz, v_sz; + while (*end < data_sz) { + /* make odd corner cases identifiable, eg. invalid v_sz */ + k_sz = 0; + + if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) { + printk(BIOS_WARNING, "failed reading key size\n"); + return CB_ERR; + } + + /* found the end */ + if (k_sz == 0xffffffff) + break; + + /* something is fishy here: + * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while + * other problems are covered by the loop condition + */ + if (k_sz > data_sz) { + printk(BIOS_WARNING, "key size out of bounds\n"); + return CB_ERR; + } + + if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) { + printk(BIOS_WARNING, "failed reading value size\n"); + return CB_ERR; + } + + if (v_sz > data_sz) { + printk(BIOS_WARNING, "value size out of bounds\n"); + return CB_ERR; + } + + *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1; + *end = ALIGN_UP(*end, sizeof(uint32_t)); + } + + printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end); + + if (k_sz != 0xffffffff) { + printk(BIOS_WARNING, + "eof of data marker looks invalid: 0x%x\n", k_sz); + return CB_ERR; + } + + return CB_SUCCESS; + +} /* * Append data to region * @@ -124,78 +183,38 @@ return -1; } - ssize_t data_sz = region_device_sz(&store); - - /* scan for end */ - ssize_t end = 0; - uint32_t k_sz, v_sz; - while (end < data_sz) { - /* make odd corner cases identifiable, eg. invalid v_sz */ - k_sz = 0; - - if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) { - printk(BIOS_WARNING, "failed reading key size\n"); - return -1; - } - - /* found the end */ - if (k_sz == 0xffffffff) - break; - - /* something is fishy here: - * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while - * other problems are covered by the loop condition - */ - if (k_sz > data_sz) { - printk(BIOS_WARNING, "key size out of bounds\n"); - return -1; - } - - if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) { - printk(BIOS_WARNING, "failed reading value size\n"); - return -1; - } - - if (v_sz > data_sz) { - printk(BIOS_WARNING, "value size out of bounds\n"); - return -1; - } - - end += 8 + k_sz + v_sz + 1; - end = ALIGN_UP(end, sizeof(uint32_t)); - } - - printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end); - - if (k_sz != 0xffffffff) { - printk(BIOS_WARNING, - "eof of data marker looks invalid: 0x%x\n", k_sz); + ssize_t end; + if (scan_end(&end) == CB_ERR) return -1; - } printk(BIOS_WARNING, "used size looks legit\n"); printk(BIOS_WARNING, "open (%zx, %zx) for writing\n", region_device_offset(&store), region_device_sz(&store)); - if (boot_device_rw_subregion(&store.region, &store) < 0) { + if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) { printk(BIOS_WARNING, "couldn't open store for writing\n"); return -1; } - uint32_t record_sz = 8 + key_sz + value_sz + 1; - if (end + record_sz >= data_sz) { + struct region subregion = + { + .offset = end, + .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1, + }; + + if (region_is_subregion(region_device_region(&store), &subregion)) { printk(BIOS_WARNING, "not enough space for new data\n"); return -1; } - if (rdev_writeat(&store, &key_sz, end, 4) != 4) { + if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing key size\n"); } - end += 4; - if (rdev_writeat(&store, &value_sz, end, 4) != 4) { + end += sizeof(key_sz); + if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing value size\n"); } - end += 4; + end += sizeof(value_sz); if (rdev_writeat(&store, key, end, key_sz) != key_sz) { printk(BIOS_WARNING, "failed writing key data\n"); } @@ -205,7 +224,7 @@ } end += value_sz; uint8_t nul = 0; - if (rdev_writeat(&store, &nul, end, 1) != 1) { + if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) { printk(BIOS_WARNING, "failed writing termination\n"); } diff --git a/src/include/smmstore.h b/src/include/smmstore.h index a535c5b..30a8191 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -28,22 +28,22 @@ #define SMMSTORE_CMD_APPEND 3 struct smmstore_params_read { - void *buf; - ssize_t bufsize; + uint32_t *buf; + uint32_t bufsize; }; struct smmstore_params_append { - void *key; - size_t keysize; - void *val; - size_t valsize; + uint32_t *key; + uint32_t keysize; + uint32_t *val; + uint32_t valsize; }; /* SMM responder */ uint32_t smmstore_exec(uint8_t command, void *param); /* implementation */ -int smmstore_read_region(void *buf, ssize_t *bufsize); +int smmstore_read_region(void *buf, uint32_t *bufsize); int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 2ffc00f..c125c0c 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -311,7 +311,7 @@ reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Gerrit-Change-Number: 30432 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019