coreboot-gerrit October 2019

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Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by Mike Banon (Code Review) 27 Mar '20

27 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33874 Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply two changes CB:31448 and CB:31450 to add the discrete GPU support for AMD Lenovo G505S. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2452a75d425f8f647e81314111c462d1195d595d --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33874/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..aca4adb --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < "./b7d4266.diff" +### diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..6137cc4 --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_dgpu_my.txt" +sha256sum "./8e35cfe.diff" > "./sha256sums_dgpu_my.txt" +sha256sum "./b7d4266.diff" >> "./sha256sums_dgpu_my.txt" +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" + exit 1 +fi +# diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..e0d4a2a --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +rm -f "./8e35cfe.diff" +wget "https://review.coreboot.org/changes/31448/revisions/17/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +rm -f "./b7d4266.diff" +wget "https://review.coreboot.org/changes/31450/revisions/12/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b7d4266.diff" +### diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b607b61 --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,2 @@ +284cb0908c498c730dd8ed994c65ffd186d1dd34b4bc3432c9e7ccf7f40313e2 ./8e35cfe.diff +0edfa4f1bb2310220f0d6be2228f0be15d2ab0256e63fa1ed6fecc1650e1f938 ./b7d4266.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2452a75d425f8f647e81314111c462d1195d595d Gerrit-Change-Number: 33874 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: mb/google/sarien: Modify Melfas touchscreen reset delay
by Ivy Jian (Code Review) 27 Mar '20

27 Mar '20

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34162 ) Change subject: mb/google/sarien: Modify Melfas touchscreen reset delay ...................................................................... mb/google/sarien: Modify Melfas touchscreen reset delay Modify reset_delay_ms as 115ms to waiting for Melfas device I2C interface ready after touch fw AU and rebind driver. BUG=b:136560969 BRANCH=sarien TEST=Touchscreen works fine after touch FW auto updated. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34162/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849..53189ce 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -343,7 +343,7 @@ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "reset_delay_ms" = "115" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/34162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Gerrit-Change-Number: 34162 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 3

Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503 Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ...................................................................... drivers/intel/gma: Add `new-pch.asl` for Skylake+ This should work as `pch.asl` equivalent for Skylake and later platforms. Untested. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1 diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Gerrit-Change-Number: 31503 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/secunet: Add driver to read DMI info from I2C EEPROM
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36298 ) Change subject: vendorcode/secunet: Add driver to read DMI info from I2C EEPROM ...................................................................... vendorcode/secunet: Add driver to read DMI info from I2C EEPROM Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/vendorcode/Makefile.inc A src/vendorcode/secunet/Kconfig A src/vendorcode/secunet/Makefile.inc A src/vendorcode/secunet/dmi/Makefile.inc A src/vendorcode/secunet/dmi/eeprom.h A src/vendorcode/secunet/dmi/smbios.c 6 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36298/1 diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 8ccb0d0..55c2bb1 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan +subdirs-y += secunet diff --git a/src/vendorcode/secunet/Kconfig b/src/vendorcode/secunet/Kconfig new file mode 100644 index 0000000..7e83f90 --- /dev/null +++ b/src/vendorcode/secunet/Kconfig @@ -0,0 +1,3 @@ +config SECUNET_DMI + bool + select SMBIOS_PROVIDED_BY_MOBO diff --git a/src/vendorcode/secunet/Makefile.inc b/src/vendorcode/secunet/Makefile.inc new file mode 100644 index 0000000..15d7360 --- /dev/null +++ b/src/vendorcode/secunet/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SECUNET_DMI) += dmi diff --git a/src/vendorcode/secunet/dmi/Makefile.inc b/src/vendorcode/secunet/dmi/Makefile.inc new file mode 100644 index 0000000..90da971 --- /dev/null +++ b/src/vendorcode/secunet/dmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += smbios.c diff --git a/src/vendorcode/secunet/dmi/eeprom.h b/src/vendorcode/secunet/dmi/eeprom.h new file mode 100644 index 0000000..c4cdd41 --- /dev/null +++ b/src/vendorcode/secunet/dmi/eeprom.h @@ -0,0 +1,62 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SECUNET_DMI_EEPROM_H +#define _SECUNET_DMI_EEPROM_H + +#include <stdint.h> + +enum bx26_strings { + BOARD_MATNR, + BOARD_SERIAL_NUMBER, + BOARD_VERSION, + BOARD_MCTRL_FW_VERSION, + BOARD_CCR_FW_VERSION, + BOARD_NIC_FW_VERSION, + BOARD_LP_VERSION, + BOARD_VERSION_ID, + + SYSTEM_PRODUCT_NAME, + SYSTEM_VERSION, + SYSTEM_SERIAL_NUMBER, + SYSTEM_UUID, + SYSTEM_MANUFACTURER, + SYSTEM_PRODUCTION_DATE, + SYSTEM_MLFB, + SYSTEM_MATNR, +}; + +struct bx26_location { + uint16_t offset; + uint16_t length; +}; + +static const struct bx26_location bx26_locations[] = { + [BOARD_MATNR] = { 0x0000, 0x20 }, + [BOARD_SERIAL_NUMBER] = { 0x0020, 0x20 }, + [BOARD_VERSION] = { 0x0040, 0x20 }, + [BOARD_MCTRL_FW_VERSION] = { 0x0060, 0x20 }, + [BOARD_CCR_FW_VERSION] = { 0x0080, 0x20 }, + [BOARD_NIC_FW_VERSION] = { 0x00a0, 0x20 }, + [BOARD_LP_VERSION] = { 0x00c0, 0x20 }, + [BOARD_VERSION_ID] = { 0x0100, 0x20 }, + + [SYSTEM_PRODUCT_NAME] = { 0x4000, 0x20 }, + [SYSTEM_VERSION] = { 0x4040, 0x10 }, + [SYSTEM_SERIAL_NUMBER] = { 0x4060, 0x10 }, + [SYSTEM_UUID] = { 0x4080, 0x24 }, + [SYSTEM_MANUFACTURER] = { 0x40c0, 0x20 }, + [SYSTEM_PRODUCTION_DATE] = { 0x4100, 0x20 }, + [SYSTEM_MLFB] = { 0x4140, 0x20 }, + [SYSTEM_MATNR] = { 0x4180, 0x20 }, +}; + +#endif diff --git a/src/vendorcode/secunet/dmi/smbios.c b/src/vendorcode/secunet/dmi/smbios.c new file mode 100644 index 0000000..c299516d --- /dev/null +++ b/src/vendorcode/secunet/dmi/smbios.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <ctype.h> +#include <commonlib/helpers.h> +#include <uuid.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> +#include <smbios.h> + +#include "eeprom.h" + +#define MAX_STRING_LENGTH 256 + +static struct device *eeprom; + +static const char *eeprom_read_string(const enum bx26_strings idx) +{ + static char str[MAX_STRING_LENGTH + 1]; + + if (!eeprom) { + printk(BIOS_WARNING, "DMI: Serial EEPROM not found\n"); + str[0] = '\0'; + return str; + } + + const size_t offset = bx26_locations[idx].offset; + const size_t length = MIN(bx26_locations[idx].length, MAX_STRING_LENGTH); + + if (i2c_dev_read_at16(eeprom, (u8 *)str, length, offset) != length) { + printk(BIOS_WARNING, "DMI: Failed to read serial EEPROM\n"); + str[0] = '\0'; + } else { + unsigned int i; + /* Terminate at first non-printable character. */ + for (i = 0; i < length; ++i) { + if (!isprint(str[i])) + break; + } + str[i] = '\0'; + } + + return str; +} + +const char *smbios_system_manufacturer(void) +{ + return eeprom_read_string(SYSTEM_MANUFACTURER); +} + +const char *smbios_system_product_name(void) +{ + return eeprom_read_string(SYSTEM_PRODUCT_NAME); +} + +const char *smbios_system_serial_number(void) +{ + return eeprom_read_string(SYSTEM_SERIAL_NUMBER); +} + +const char *smbios_system_version(void) +{ + return eeprom_read_string(SYSTEM_VERSION); +} + +void smbios_system_set_uuid(u8 *const uuid) +{ + if (parse_uuid(uuid, eeprom_read_string(SYSTEM_UUID))) { + printk(BIOS_WARNING, "DMI: Cannot parse UUID\n"); + memset(uuid, 0x00, UUID_LEN); + } +} + +const char *smbios_mainboard_serial_number(void) +{ + return eeprom_read_string(BOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + return eeprom_read_string(BOARD_VERSION); +} + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_I2C || (dev->path.i2c.device & 0xf0) != 0x50) + return; + eeprom = dev; +} + +struct chip_operations vendorcode_secunet_dmi_ops = { + CHIP_NAME("secunet DMI") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Gerrit-Change-Number: 36298 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/skylake: Add Lewisburg PCH GPIOs support
by Maxim Polyakov (Code Review) 23 Mar '20

23 Mar '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35031 ) Change subject: soc/intel/skylake: Add Lewisburg PCH GPIOs support ...................................................................... soc/intel/skylake: Add Lewisburg PCH GPIOs support The pin layout in this patch corresponds to the driver in the linux kernel for Lewisburg PCH GPIO hardware [1] [1] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h A src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h M src/soc/intel/skylake/include/soc/pcr_ids.h 5 files changed, 440 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35031/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 13c1517..34fd97c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -175,6 +175,12 @@ help Choose this option if you have a PCH-H chipset. +config WELISBURG_SOC_PCH_H + bool + default n + help + Choose this option if you have the Lewisburg C62x PCH chipset. + config NHLT_DMIC_2CH bool default n diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..0130936 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -36,6 +36,9 @@ static const struct pad_group skl_community_com0_groups[] = { INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ +#if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */ +#endif }; static const struct pad_group skl_community_com1_groups[] = { @@ -48,19 +51,38 @@ INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */ #else INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ +# if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ +# else INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */ +# endif #endif }; static const struct pad_group skl_community_com3_groups[] = { #if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +#elif CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_I0, GPP_I0, RCOMP_3P3), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */ #endif }; +#if CONFIG(WELISBURG_SOC_PCH_H) +static const struct pad_group skl_community_com4_groups[] = { + INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */ + INTEL_GPP(GPP_J0, GPP_K0, RCOMP_1P8_3P3), /* GPP G */ +}; + +static const struct pad_group skl_community_com5_groups[] = { + INTEL_GPP(GPP_J0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_J0, GPP_H0, GPP_H23), /* GPP H */ + INTEL_GPP(GPP_J0, GPP_L2, GPP_L19), /* GPP L */ +}; +#endif + static const struct pad_group skl_community_com2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ }; @@ -69,7 +91,11 @@ { .port = PID_GPIOCOM0, .first_pad = GPP_A0, +#if CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_F23, +#else .last_pad = GPP_B23, +#endif .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -89,6 +115,8 @@ .first_pad = GPP_C0, #if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, +#elif CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_E12, #else .last_pad = GPP_E23, #endif @@ -108,7 +136,7 @@ .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if CONFIG(SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -130,6 +158,44 @@ .groups = skl_community_com3_groups, .num_groups = ARRAY_SIZE(skl_community_com3_groups), }, { +#if CONFIG(WELISBURG_SOC_PCH_H) + .port = PID_GPIOCOM4, + .first_pad = GPP_J0, + .last_pad = GPP_K10, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com4_groups, + .num_groups = ARRAY_SIZE(skl_community_com4_groups), + }, { + .port = PID_GPIOCOM4, + .first_pad = GPP_G0, + .last_pad = GPP_L19, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com5_groups, + .num_groups = ARRAY_SIZE(skl_community_com5_groups), + }, { +#endif .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -161,17 +227,27 @@ static const struct pmc_to_gpio_route routes[] = { { GPP_A, GPP_A}, { GPP_B, GPP_B}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_F, GPP_F}, +#endif { GPP_C, GPP_C}, { GPP_D, GPP_D}, { GPP_E, GPP_E}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_I, GPP_I}, + { GPP_J, GPP_J}, + { GPP_K, GPP_K}, +#else { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if CONFIG(SKYLAKE_SOC_PCH_H) +# if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, +# endif #endif { GPD, GPD}, }; + *num = ARRAY_SIZE(routes); return routes; } @@ -179,7 +255,7 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (CONFIG(SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..0285989 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -20,6 +20,8 @@ #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> +#elif CONFIG(WELISBURG_SOC_PCH_H) +# include <soc/gpio_wlb_pch_defs.h> #else # include <soc/gpio_soc_defs.h> #endif @@ -33,6 +35,22 @@ #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#if CONFIG(WELISBURG_SOC_PCH_H) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) +#endif + +#if CONFIG(WELISBURG_SOC_PCH_H) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + +#else #define NUM_GPI_STATUS_REGS \ ((NUM_GPIO_COM0_GPI_REGS) +\ @@ -218,6 +236,8 @@ #define GPD10_IRQ 0x5a #define GPD11_IRQ 0x5b +#endif + /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 diff --git a/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h new file mode 100644 index 0000000..636837c --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_WLB_PCH_DEFS_H_ +#define _SOC_GPIO_WLB_PCH_DEFS_H_ + +/* GPIO Community 0 */ +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_F 0x2 +/* GPIO Community 1 */ +#define GPP_C 0x3 +#define GPP_D 0x4 +#define GPP_E 0x5 +/* GPIO Community 3 */ +#define GPP_I 0x6 +/* GPIO Community 4 */ +#define GPP_J 0x7 +#define GPP_K 0x8 +/* GPIO Community 5 */ +#define GPP_G 0x9 +#define GPP_H 0xA +#define GPP_L 0xB +/* GPIO Community 2 */ +#define GPD 0xC + +#define GPIO_NUM_GROUPS 13 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group F */ +#define GPP_F0 48 +#define GPP_F1 49 +#define GPP_F2 50 +#define GPP_F3 51 +#define GPP_F4 52 +#define GPP_F5 53 +#define GPP_F6 54 +#define GPP_F7 55 +#define GPP_F8 56 +#define GPP_F9 57 +#define GPP_F10 58 +#define GPP_F11 59 +#define GPP_F12 60 +#define GPP_F13 61 +#define GPP_F14 62 +#define GPP_F15 63 +#define GPP_F16 64 +#define GPP_F17 65 +#define GPP_F18 66 +#define GPP_F19 67 +#define GPP_F20 68 +#define GPP_F21 69 +#define GPP_F22 70 +#define GPP_F23 71 + +#define NUM_GPIO_COM0_PADS (GPP_F23 - GPP_A0 + 1) + +/* Group C */ +#define GPP_C0 72 +#define GPP_C1 73 +#define GPP_C2 74 +#define GPP_C3 75 +#define GPP_C4 76 +#define GPP_C5 77 +#define GPP_C6 78 +#define GPP_C7 79 +#define GPP_C8 80 +#define GPP_C9 81 +#define GPP_C10 82 +#define GPP_C11 83 +#define GPP_C12 84 +#define GPP_C13 85 +#define GPP_C14 86 +#define GPP_C15 87 +#define GPP_C16 88 +#define GPP_C17 89 +#define GPP_C18 90 +#define GPP_C19 91 +#define GPP_C20 92 +#define GPP_C21 93 +#define GPP_C22 94 +#define GPP_C23 95 +/* Group D */ +#define GPP_D0 96 +#define GPP_D1 97 +#define GPP_D2 98 +#define GPP_D3 99 +#define GPP_D4 100 +#define GPP_D5 101 +#define GPP_D6 102 +#define GPP_D7 103 +#define GPP_D8 104 +#define GPP_D9 105 +#define GPP_D10 106 +#define GPP_D11 107 +#define GPP_D12 108 +#define GPP_D13 109 +#define GPP_D14 110 +#define GPP_D15 111 +#define GPP_D16 112 +#define GPP_D17 113 +#define GPP_D18 114 +#define GPP_D19 115 +#define GPP_D20 116 +#define GPP_D21 117 +#define GPP_D22 118 +#define GPP_D23 119 +/* Group E */ +#define GPP_E0 120 +#define GPP_E1 121 +#define GPP_E2 122 +#define GPP_E3 123 +#define GPP_E4 124 +#define GPP_E5 125 +#define GPP_E6 126 +#define GPP_E7 127 +#define GPP_E8 128 +#define GPP_E9 129 +#define GPP_E10 130 +#define GPP_E11 131 +#define GPP_E12 132 + +#define NUM_GPIO_COM1_PADS (GPP_E12 - GPP_C0 + 1) + +/* Group I */ +#define GPP_I0 133 +#define GPP_I1 134 +#define GPP_I2 135 +#define GPP_I3 136 +#define GPP_I4 137 +#define GPP_I5 138 +#define GPP_I6 139 +#define GPP_I7 140 +#define GPP_I8 141 +#define GPP_I9 142 +#define GPP_I10 143 +#define RCOMP_3P3 144 + +#define NUM_GPIO_COM3_PADS (RCOMP_3P3 - GPP_I0 + 1) + +/* Group J */ +#define GPP_J0 145 +#define GPP_J1 146 +#define GPP_J2 147 +#define GPP_J3 148 +#define GPP_J4 149 +#define GPP_J5 150 +#define GPP_J6 151 +#define GPP_J7 152 +#define GPP_J8 153 +#define GPP_J9 154 +#define GPP_J10 155 +#define GPP_J11 156 +#define GPP_J12 157 +#define GPP_J13 158 +#define GPP_J14 159 +#define GPP_J15 160 +#define GPP_J16 161 +#define GPP_J17 162 +#define GPP_J18 163 +#define GPP_J19 164 +#define GPP_J20 165 +#define GPP_J21 166 +#define GPP_J22 167 +#define GPP_J23 168 +/* Group K */ +#define GPP_K0 169 +#define GPP_K1 170 +#define GPP_K2 171 +#define GPP_K3 172 +#define GPP_K4 173 +#define GPP_K5 174 +#define GPP_K6 175 +#define GPP_K7 176 +#define GPP_K8 177 +#define GPP_K9 178 +#define GPP_K10 179 + +#define RCOMP_1P8_3P3 180 + +#define NUM_GPIO_COM4_PADS (RCOMP_1P8_3P3 - GPP_J0 + 1) + +/* Group G */ +#define GPP_G0 181 +#define GPP_G1 182 +#define GPP_G2 183 +#define GPP_G3 184 +#define GPP_G4 185 +#define GPP_G5 186 +#define GPP_G6 187 +#define GPP_G7 188 +#define GPP_G8 189 +#define GPP_G9 190 +#define GPP_G10 191 +#define GPP_G11 192 +#define GPP_G12 193 +#define GPP_G13 194 +#define GPP_G14 195 +#define GPP_G15 196 +#define GPP_G16 197 +#define GPP_G17 198 +#define GPP_G18 199 +#define GPP_G19 200 +#define GPP_G20 201 +#define GPP_G21 202 +#define GPP_G22 203 +#define GPP_G23 204 +/* Group H */ +#define GPP_H0 205 +#define GPP_H1 206 +#define GPP_H2 207 +#define GPP_H3 208 +#define GPP_H4 209 +#define GPP_H5 210 +#define GPP_H6 211 +#define GPP_H7 212 +#define GPP_H8 213 +#define GPP_H9 214 +#define GPP_H10 215 +#define GPP_H11 216 +#define GPP_H12 217 +#define GPP_H13 218 +#define GPP_H14 219 +#define GPP_H15 220 +#define GPP_H16 221 +#define GPP_H17 222 +#define GPP_H18 223 +#define GPP_H19 224 +#define GPP_H20 225 +#define GPP_H21 226 +#define GPP_H22 227 +#define GPP_H23 228 +/* Group L */ +#define GPP_L2 229 +#define GPP_L3 230 +#define GPP_L4 231 +#define GPP_L5 232 +#define GPP_L6 233 +#define GPP_L7 234 +#define GPP_L8 235 +#define GPP_L9 236 +#define GPP_L10 237 +#define GPP_L11 238 +#define GPP_L12 239 +#define GPP_L13 240 +#define GPP_L14 241 +#define GPP_L15 242 +#define GPP_L16 243 +#define GPP_L17 244 +#define GPP_L18 245 +#define GPP_L19 246 + +#define NUM_GPIO_COM5_PADS (GPP_L23 - GPP_G0 + 1) + +/* Group GPD */ +#define GPD0 247 +#define GPD1 248 +#define GPD2 249 +#define GPD3 250 +#define GPD4 251 +#define GPD5 252 +#define GPD6 253 +#define GPD7 254 +#define GPD8 255 +#define GPD9 256 +#define GPD10 257 +#define GPD11 258 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#endif diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index 71affd8..1185e17 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -20,6 +20,8 @@ * Port ids */ #define PID_PSTH 0x89 +#define PID_GPIOCOM5 0x11 +#define PID_GPIOCOM4 0xAB #define PID_GPIOCOM3 0xAC #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE -- To view, visit https://review.coreboot.org/c/coreboot/+/35031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Gerrit-Change-Number: 35031 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 24

Change in coreboot[master]: ec/lenovo/h8: Add a config to indicate whether dock init is needed
by Bill XIE (Code Review) 20 Mar '20

20 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36385 ) Change subject: ec/lenovo/h8: Add a config to indicate whether dock init is needed ...................................................................... ec/lenovo/h8: Add a config to indicate whether dock init is needed Discussed in CB:36093, in the past many lenovo boards need to declare empty h8_mainboard_init_dock() to satisfy h8.c. Since H8_DOCK_EARLY_INIT has a different meaning, it had better add another config to indicate whether dock init is needed, thus eliminating the necessity to declare empty h8_mainboard_init_dock() in the future. Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/h8.c M src/mainboard/lenovo/l520/mainboard.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430/mainboard.c M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc D src/mainboard/lenovo/x200/variants/x301/dock.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/mainboard.c M src/mainboard/lenovo/x60/Kconfig 21 files changed, 16 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36385/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f3df56a..5cc26d6 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,7 +44,14 @@ bool default n -endif +config H8_NEED_DOCK_INIT + bool "Dock init during boot is necessary" + +if H8_NEED_DOCK_INIT config H8_DOCK_EARLY_INIT bool + +endif # H8_NEED_DOCK_INIT + +endif # EC_LENOVO_H8 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3a99b52..679b96c 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -354,7 +354,7 @@ h8_set_audio_mute(0); -#if !CONFIG(H8_DOCK_EARLY_INIT) +#if CONFIG(H8_NEED_DOCK_INIT) && !CONFIG(H8_DOCK_EARLY_INIT) h8_mainboard_init_dock(); #endif } diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index db695b1..88c7884 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2caf1d3..171cb29 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -10,6 +10,7 @@ select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..600b8a6 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -21,6 +21,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select MAINBOARD_HAS_LIBGFXINIT config VBOOT diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index 99a5bd8..a86a90e 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -17,10 +17,6 @@ #include <drivers/intel/gma/int15.h> #include <ec/lenovo/h8/h8.h> -void h8_mainboard_init_dock (void) -{ -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index bd4292a..6825b6b 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -28,10 +28,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index bc8fa29..86351c8 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -19,6 +19,7 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT select I945_LVDS diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca..50b4de1 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -24,10 +24,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index 64cc15b..bc6dcb1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -29,8 +29,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - -/* TODO: this device doesnt have a dock */ -void h8_mainboard_init_dock (void) -{ -} diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index fab8a88..8cab040 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -23,6 +23,7 @@ select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select H8_NEED_DOCK_INIT if BOARD_LENOVO_X200 config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index f6c2c0c..7e38a78 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -ramstage-y += variants/$(VARIANT_DIR)/dock.c +ramstage-$(CONFIG_BOARD_LENOVO_X200) += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c deleted file mode 100644 index f8a2dc4..0000000 --- a/src/mainboard/lenovo/x200/variants/x301/dock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/h8.h> - -void h8_mainboard_init_dock(void) -{ -} diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index e40c0d3..21edec79 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index e3aabf3..27c953b 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select I945_LVDS -- To view, visit https://review.coreboot.org/c/coreboot/+/36385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Gerrit-Change-Number: 36385 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

8 25

Change in ...coreboot[master]: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINU...
by Jeremy Soller (Code Review) 17 Mar '20

17 Mar '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31536 Change subject: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE ...................................................................... soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d..3716640 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -172,6 +172,13 @@ default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..c95a68f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -246,6 +246,12 @@ /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Set correct Sirq mode based on config */ + if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + params->PchSirqMode = 1; + else + params->PchSirqMode = 0; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Gerrit-Change-Number: 31536 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

7 22

Change in ...coreboot[master]: nb/intel/i945: Correct mask for CxDRT1
by HAOUAS Elyes (Code Review) 16 Mar '20

16 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31144 Change subject: nb/intel/i945: Correct mask for CxDRT1 ...................................................................... nb/intel/i945: Correct mask for CxDRT1 [27:24] and [31:30] are reserved, so we shouldn't change them. Tested on i945G-M4 board. Change-Id: I0cac9160c756405838706edb0461575241faae35 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31144/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..2a62ca3 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1475,7 +1475,7 @@ /* Calculate DRT1 */ - temp_drt = MCHBAR32(C0DRT1) & 0x00020088; + temp_drt = MCHBAR32(C0DRT1) & 0xcf020088; /* DRAM RASB Precharge */ temp_drt |= (sysinfo->trp - 2) << 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cac9160c756405838706edb0461575241faae35 Gerrit-Change-Number: 31144 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: Add support for the 51nb X210
by Matthew Garrett (Code Review) 16 Mar '20

16 Mar '20

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32531 Change subject: Add support for the 51nb X210 ...................................................................... Add support for the 51nb X210 The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal Coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes: * EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc A configs/config.51nb_x210 M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 31 files changed, 2,530 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/1 diff --git a/Makefile.inc b/Makefile.inc index fc04a16..6e379dd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -88,7 +88,7 @@ ####################################################################### # root source directories of coreboot subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi -subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) +subdirs-y += src/ec/acpi src/ec/51nb $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) diff --git a/configs/config.51nb_x210 b/configs/config.51nb_x210 new file mode 100644 index 0000000..6217eb6 --- /dev/null +++ b/configs/config.51nb_x210 @@ -0,0 +1,838 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="1" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +CONFIG_BOOTSPLASH_IMAGE=y +CONFIG_BOOTSPLASH_FILE="" + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +CONFIG_VENDOR_51NB=y +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_51NB_X210=y +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="51nb" +CONFIG_MAINBOARD_FAMILY="X210" +CONFIG_MAINBOARD_PART_NUMBER="X210" +CONFIG_MAINBOARD_VERSION="2.0" +CONFIG_MAINBOARD_DIR="51nb/x210" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_MAX_CPUS=8 +# CONFIG_NO_POST is not set +CONFIG_VGA_BIOS_ID="8086,5917" +CONFIG_DIMM_MAX=2 +CONFIG_DIMM_SPD_SIZE=512 +CONFIG_CPU_MICROCODE_CBFS_LEN=0x18000 +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFE115A0 +CONFIG_CBFS_SIZE=0x5c0000 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="Unknown Serial Number" +CONFIG_VGA_BIOS_FILE="vgabios.bin" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="51nb" +CONFIG_INTEL_GMA_VBT_FILE="vbt.bin" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +# CONFIG_POST_IO is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_VBOOT is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="X210" +CONFIG_IFD_BIN_PATH="descriptor.bin" +CONFIG_ME_BIN_PATH="me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_HEAP_SIZE=0x80000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +# CONFIG_CONSOLE_CBMEM is not set +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_SKYLAKE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +# CONFIG_SKYLAKE_SOC_PCH_H is not set +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y + +# +# Multiple Processor (MP) Initialization Options +# +CONFIG_USE_COREBOOT_NATIVE_MP_INIT=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_51NB=y + +# +# Please select the following otherwise your laptop cannot be powered on. +# +CONFIG_51NB_EC_FIRMWARE=y +CONFIG_51NB_EC_FW="ec.bin" +CONFIG_51NB_EC_FW_OFFSET="0x00200000" +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_CHECK_ME is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SMMSTORE=y +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SMMSTORE_REGION="SMMSTORE" +CONFIG_SMMSTORE_FILENAME="smm_store" +CONFIG_SMMSTORE_SIZE=0x40000 +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +CONFIG_SPI_FLASH_SMM=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_TPM_INIT=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_FSP_CAR is not set +CONFIG_FSP_M_XIP=y +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +# CONFIG_USER_NO_TPM is not set +# CONFIG_USER_TPM1 is not set +CONFIG_USER_TPM2=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_PAYLOAD_FILE="payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_TIANOCORE_STABLE=y +# CONFIG_TIANOCORE_REVISION is not set +# CONFIG_TIANOCORE_TARGET_IA32 is not set +CONFIG_TIANOCORE_TARGET_X64=y +# CONFIG_TIANOCORE_DEBUG is not set +CONFIG_TIANOCORE_RELEASE=y +# CONFIG_TIANOCORE_USE_8254_TIMER is not set +# CONFIG_TIANOCORE_BOOTSPLASH_IMAGE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set +CONFIG_MEMTEST_STABLE=y +# CONFIG_MEMTEST_MASTER is not set +# CONFIG_MEMTEST_REVISION is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_SPD_READ_BY_WORD=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/src/Kconfig b/src/Kconfig index 90c724e..4688fd3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -369,6 +369,7 @@ source "src/superio/*/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" +source "src/ec/51nb/Kconfig" source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" diff --git a/src/ec/51nb/51nb.c b/src/ec/51nb/51nb.c new file mode 100644 index 0000000..2559176 --- /dev/null +++ b/src/ec/51nb/51nb.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> + +#include "ec.h" + +static void ec_51nb_ops_enable(struct device *dev) +{ + /* Enable function 5 (PS/2 AUX) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x05, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); + + /* Enable function 6 (PS/2 KB) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x06, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); + + /* Enable funcion 17 (EC) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x11, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); +} + +struct chip_operations ec_51nb_ops = { + CHIP_NAME("51NB EC") + .enable_dev = ec_51nb_ops_enable, +}; diff --git a/src/ec/51nb/Kconfig b/src/ec/51nb/Kconfig new file mode 100644 index 0000000..ca93a7e --- /dev/null +++ b/src/ec/51nb/Kconfig @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config EC_51NB + bool + help + Support for the 51NB EC + +if EC_51NB + +comment "Please select the following otherwise your laptop cannot be powered on." + +config 51NB_EC_FIRMWARE + bool "Add firmware images for 51NB EC" + depends on EC_51NB + default y + help + Select this option to add the firmware blob for the 51NB EC. + You need this blob to power on your machine. + +config 51NB_EC_FW + string "51NB EC firmware path" + depends on 51NB_EC_FIRMWARE + default "ec.bin" + help + The path and filename of the file to use as 51NB firmware. + +config 51NB_EC_FW_OFFSET + string + depends on 51NB_EC_FIRMWARE + default "0x00200000" + +endif diff --git a/src/ec/51nb/Makefile.inc b/src/ec/51nb/Makefile.inc new file mode 100644 index 0000000..b41febb --- /dev/null +++ b/src/ec/51nb/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_EC_51NB),y) +51NB_EC_INSERT:=$(top)/util/51nb/51nb_ec_insert +INTERMEDIATE+=51nb_ec_insert + +51nb_ec_insert: $(obj)/coreboot.pre +ifeq ($(CONFIG_51NB_EC_FIRMWARE),y) + printf " Building 51nb_ec_insert.\n" + $(MAKE) -C util/51nb + printf " Inserting EC firmware blobs.\n" + $(51NB_EC_INSERT) $(obj)/coreboot.pre \ + $(CONFIG_51NB_EC_FW) $(CONFIG_51NB_EC_FW_OFFSET) +endif + +PHONY+=51nb_ec_insert + +build_complete:: +ifeq ($(CONFIG_51NB_EC_FIRMWARE),) + printf "\n** WARNING **\n" + printf "You haven't added the firmware blobs for 51NB EC.\n" + printf "You may be unable to power on your laptop without these blobs.\n" + printf "Please select the following option to add them:\n\n" + printf " Chipset --->\n" + printf " [*] Add firmware images for 51NB EC\n\n" +endif + +ramstage-y += 51nb.c + +endif diff --git a/src/ec/51nb/ec.h b/src/ec/51nb/ec.h new file mode 100644 index 0000000..831514c --- /dev/null +++ b/src/ec/51nb/ec.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _EC_51NB_H +#define _EC_51NB_H + +#define SETUP_COMMAND 0x4e +#define SETUP_DATA 0x4f +#define LDN_SEL 0x07 +#define LDN_ENABLE 0x30 + +#endif /* _EC_51NB_H */ diff --git a/src/mainboard/51nb/Kconfig b/src/mainboard/51nb/Kconfig new file mode 100644 index 0000000..12d2c0d --- /dev/null +++ b/src/mainboard/51nb/Kconfig @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if VENDOR_51NB + +choice + prompt "Mainboard model" + +source "src/mainboard/51nb/*/Kconfig.name" + +endchoice + +source "src/mainboard/51nb/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "51NB" + +endif # VENDOR_51NB diff --git a/src/mainboard/51nb/Kconfig.name b/src/mainboard/51nb/Kconfig.name new file mode 100644 index 0000000..6f99514 --- /dev/null +++ b/src/mainboard/51nb/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_51NB + bool "51NB" diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig new file mode 100644 index 0000000..d5dd278 --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig @@ -0,0 +1,76 @@ +config BOARD_51NB_X210 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select EC_51NB + +if BOARD_51NB_X210 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "51NB" + +config MAINBOARD_FAMILY + string + default "X210" + +config MAINBOARD_PART_NUMBER + string + default "X210" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "51nb/x210" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 8 + +config NO_POST + def_bool y + help + This platform does not have any way to see POST codes + so disable them by default. + +config VGA_BIOS_ID + string + default "8086,5917" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/51nb/x210/Kconfig.name b/src/mainboard/51nb/x210/Kconfig.name new file mode 100644 index 0000000..1cae5dd --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_51NB_X210 + bool "51NB X210" diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc new file mode 100644 index 0000000..5d44e9b --- /dev/null +++ b/src/mainboard/51nb/x210/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += pei_data.c + +ramstage-y += pei_data.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl new file mode 100644 index 0000000..1b0d6c2 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 0x4F) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x50), + CTMP, 8, + CFAN, 8, + B1SS, 1, + BSTS, 2, + ACIN, 1, + Offset (0x53), + BKLG, 8, + TOUP, 1, + WIRE, 1, + BLTH, 1, + LIDC, 1, + APFG, 1, + WRST, 1, + BTST, 1, + ACEB, 1, + CAME, 1, + Offset (0x60), + DGCP, 16, + FLCP, 16, + DGVO, 16, + BDW, 16, + BDL, 16, + BPR, 16, + BRC, 16, + BPV, 16 + } + + Method (_REG, 2, NotSerialized) + { + /* Initialize AC power state */ + Store (ACIN, \PWRS) + + /* Initialize LID switch state */ + Store (LIDC, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q04) + { + Notify(\_SB.PCI0.GFX0.LCD, 0x86) + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q05) + { + Notify(\_SB.PCI0.GFX0.LCD, 0x87) + } + + /* Battery Information Event */ + Method (_Q0C) + { + Notify (BAT, 0x81) + } + + /* AC event */ + Method (_Q0D) + { + Store (ACIN, \PWRS) + Notify (AC, 0x80) + } + + /* Lid event */ + Method (_Q0E) + { + Store (LIDC, \LIDS) + Notify (LID0, 0x80) + } + + /* Battery Information Event */ + Method (_Q13) + { + Notify (BAT, 0x81) + } + + /* Battery Status Event */ + Method (_Q14) + { + Notify (BAT, 0x80) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_STA) + { + Return (0x0F) + } + Method (_PSR) + { + Return (\PWRS) + } + } + + Device (BAT) + { + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B1SS) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "Y91", /* 0x09: Model Number */ + "", /* 0x0a: Serial Number */ + "LION", /* 0x0b: Battery Type */ + "CJOYIN" /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, Serialized) + { + /* Design Capacity */ + Store (DGCP, Index (PBIF, 1)) + + /* Last Full Charge Capacity */ + Store (FLCP, Index (PBIF, 2)) + + /* Design Voltage */ + Store (DGVO, Index (PBIF, 4)) + + /* Design Capacity of Warning */ + Store (BDW, Index (PBIF, 5)) + + /* Design Capacity of Low */ + Store (BDL, Index (PBIF, 6)) + + Return (PBIF) + } + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + /* + * 0: BATTERY STATE + * + * bit 0 = discharging + * bit 1 = charging + * bit 2 = critical level + */ + Store (BSTS, Index (PBST, 0)) + + /* + * 1: BATTERY PRESENT RATE + */ + Store (BPR, Index (PBST, 1)) + + /* + * 2: BATTERY REMAINING CAPACITY + */ + Store (BRC, Index (PBST, 2)) + + /* + * 3: BATTERY PRESENT VOLTAGE + */ + Store (BPV, Index (PBST, 3)) + + Return (PBST) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl new file mode 100644 index 0000000..ce9fb04 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.GFX0) +{ + Device (LCD) + { + Method (_ADR, 0, Serialized) + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) + { + Return (Package (0x12) + { + 0x0A, + 0x0F, + 0x00, + 0x01, + 0x02, + 0x03, + 0x04, + 0x05, + 0x06, + 0x07, + 0x08, + 0x09, + 0x0A, + 0x0B, + 0x0C, + 0x0D, + 0x0E, + 0x0F + }) + } + Method (_BCM, 1, NotSerialized) + { + \_SB.PCI0.LPCB.EC.BKLG = Arg0 + } + Method (_BQC, 0, NotSerialized) + { + Return (\_SB.PCI0.LPCB.EC.BKLG) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl new file mode 100644 index 0000000..efe0e8d --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) + { + Return (0xF) + } + + Method (_LID) + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl new file mode 100644 index 0000000..7ea85b6 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014-2019 Google LLC + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS) + Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS) + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/51nb/x210/acpi_tables.c b/src/mainboard/51nb/x210/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi_tables.c diff --git a/src/mainboard/51nb/x210/board_info.txt b/src/mainboard/51nb/x210/board_info.txt new file mode 100644 index 0000000..65c4608 --- /dev/null +++ b/src/mainboard/51nb/x210/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: 51NB +Board name: Thinkpad X210 +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb new file mode 100644 index 0000000..9463470 --- /dev/null +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -0,0 +1,222 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable Root Ports 1, 4 and 9 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/51nb + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl new file mode 100644 index 0000000..f651532 --- /dev/null +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015-2019 Google LLC + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h new file mode 100644 index 0000000..2a00d54 --- /dev/null +++ b/src/mainboard/51nb/x210/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +}; + +#endif + +#endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c new file mode 100644 index 0000000..e8eecdf --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/51nb/x210/hda_verb.h b/src/mainboard/51nb/x210/hda_verb.h new file mode 100644 index 0000000..c721c25 --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2019 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa2155, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa2155 */ + AZALIA_SUBVENDOR(0x0, 0x17aa2155), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x042140f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a190f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a190f0), + + /* Pin Complex (NID 0x1C) */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x612140f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x601700f0), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + + /* Pin Complex (NID 0x1F) */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x901701f0), + + /* Pin Complex (NID 0x20) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x40f001f0), + + /* Pin Complex (NID 0x22) */ + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + + /* Pin Complex (NID 0x23) */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a601f0), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c new file mode 100644 index 0000000..8e9266d --- /dev/null +++ b/src/mainboard/51nb/x210/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <device/device.h> +#include <intelblocks/lpc_lib.h> +#include <string.h> +#include <smbios.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} + +static void mainboard_enable(struct device *dev) +{ + /* Route 0x4e/4f to LPC */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/51nb/x210/pei_data.c b/src/mainboard/51nb/x210/pei_data.c new file mode 100644 index 0000000..0be917d --- /dev/null +++ b/src/mainboard/51nb/x210/pei_data.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "pei_data.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/51nb/x210/pei_data.h b/src/mainboard/51nb/x210/pei_data.h new file mode 100644 index 0000000..320d980 --- /dev/null +++ b/src/mainboard/51nb/x210/pei_data.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_PEI_DATA_H_ +#define _MAINBOARD_PEI_DATA_H_ + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/51nb/x210/ramstage.c b/src/mainboard/51nb/x210/ramstage.c new file mode 100644 index 0000000..7888c39 --- /dev/null +++ b/src/mainboard/51nb/x210/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015-2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c new file mode 100644 index 0000000..98270f0 --- /dev/null +++ b/src/mainboard/51nb/x210/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015-2019 Google LLC + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <arch/io.h> +#include "pei_data.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} diff --git a/util/51nb/51nb_ec_insert.c b/util/51nb/51nb_ec_insert.c new file mode 100644 index 0000000..0f5e204 --- /dev/null +++ b/util/51nb/51nb_ec_insert.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> + +static void usage(const char *s) +{ + printf("insert firmware blobs:\n\t" + "%s <rom file> <fw> <fw offset>\n\n", + s); + exit(1); +} + +static void FseekEnd(FILE *fp, long o) +{ + if (fseek(fp, o, SEEK_END) != 0) { + puts("fseek() error!\n"); + exit(1); + } +} + +static long negoffset(long a, long romsz) +{ + if (a > 0) { + if (a & 0x80000000) /* the address in memory, and sizeof(long) + is 8 */ + return a - 0x100000000; + else /* the file offset */ + return a - romsz; + } else { + return a; + } +} + +int main(int argc, char *argv[]) +{ + FILE *fp, *fw; + long offset; + + if (argc != 4) + usage(argv[0]); + + fp = fopen(argv[1], "rb+"); + if (fp == NULL) { + puts("Error opening firmware image!"); + exit(1); + } + + fw = fopen(argv[2], "rb"); + offset = strtoul(argv[3], NULL, 0); + if (fw == NULL) { + puts("Error opening file!"); + exit(1); + } + + if (offset & 0xf) { + puts("The offsets must be aligned to 0x100"); + exit(1); + } + + long romsz; + FseekEnd(fp, -1); + romsz = ftell(fp) + 1; + printf("size of %s: 0x%lx\n", argv[1], romsz); + + if (romsz & 0xff) { + puts("The ROM size must be multiple of 0x100"); + exit(1); + } + + offset = negoffset(offset, romsz); + + puts(""); + + /* write fw1 and fw2 */ + char c; + FseekEnd(fp, offset); + printf("writing to 0x%lx\n", ftell(fp)); + while (fread(&c, 1, 1, fw) == 1) { + fwrite(&c, 1, 1, fp); + } + fclose(fw); + fclose(fp); + return 0; +} diff --git a/util/51nb/Makefile b/util/51nb/Makefile new file mode 100644 index 0000000..b6c13d6 --- /dev/null +++ b/util/51nb/Makefile @@ -0,0 +1,12 @@ +obj = 51nb_ec_insert +HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) + +all: $(obj) + +%: %.c + $(HOSTCC) -Wall -o $@ $< + +clean: + rm -f 51nb_ec_insert + +.PHONY: all clean -- To view, visit https://review.coreboot.org/c/coreboot/+/32531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Gerrit-Change-Number: 32531 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

11 83

Change in ...coreboot[master]: crossgcc: Upgrade GCC to 9.1.0
by HAOUAS Elyes (Code Review) 15 Mar '20

15 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32564 Change subject: crossgcc: Upgrade GCC to 9.1.0 ...................................................................... crossgcc: Upgrade GCC to 9.1.0 Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch R util/crossgcc/patches/gcc-9.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-9.1.0_gnat.patch R util/crossgcc/patches/gcc-9.1.0_libgcc.patch D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum A util/crossgcc/sum/gcc-9.1.0.tar.xz.cksum 7 files changed, 2 insertions(+), 21,021 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/32564/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Gerrit-Change-Number: 32564 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019