coreboot-gerrit October 2019

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Change in coreboot[master]: cpu/x86/mtrr: Add function to set MTRR with CR0.CD set
by Arthur Heymans (Code Review) 10 Apr '20

10 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36382 ) Change subject: cpu/x86/mtrr: Add function to set MTRR with CR0.CD set ...................................................................... cpu/x86/mtrr: Add function to set MTRR with CR0.CD set MTRRs should only be changed when CR0.CD is set. In a CAR environment this is a rather fragile thing to do. This is why it is best to implement this in assembly. Change-Id: I4ff59d35ade125f60ed0002a386f41fd8ad54073 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c A src/cpu/x86/mtrr/set_mtrr.S M src/include/cpu/x86/mtrr.h 4 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36382/1 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..4052c52 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -3,6 +3,9 @@ romstage-y += earlymtrr.c bootblock-y += earlymtrr.c +bootblock-y += set_mtrr.S +verstage-y += set_mtrr.S + bootblock-y += debug.c romstage-y += debug.c postcar-y += debug.c diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 02dfbdc..2f6a64d 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -52,3 +52,17 @@ maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(MTRR_PHYS_MASK(reg), maskm); } + +void set_var_mtrr_uncached( + unsigned int reg, unsigned int base, unsigned int size, + unsigned int type) +{ + /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + /* FIXME: It only support 4G less range */ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; + maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + set_var_mtrr_uncached_asm(reg, basem, maskm); +} diff --git a/src/cpu/x86/mtrr/set_mtrr.S b/src/cpu/x86/mtrr/set_mtrr.S new file mode 100644 index 0000000..43c19f7 --- /dev/null +++ b/src/cpu/x86/mtrr/set_mtrr.S @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +.global set_var_mtrr_uncached_asm + /* ARG0: mtrr_num + * ARG1: mtrr_base.lo + * ARG2: mtrr_base.hi + * ARG3: mtrr_mask.lo + * ARG4: mtrr_mask.hi + */ +.code32 +set_var_mtrr_uncached_asm: + /* Callee saved registers */ + pushl %ebp + movl %esp, %ebp + addl $8, %ebp + pushl %ebx + pushl %edx + pushl %esi + pushl %edi + + movl 0(%ebp), %ecx + movl 4(%ebp), %ebx + movl 8(%ebp), %edx + movl 12(%ebp), %esi + movl 16(%ebp), %edi + + /* Disable caching before setting MTRR */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + /* MTRR_PHYS_BASE */ + imul $2, %ecx, %ecx + addl $MTRR_PHYS_BASE(0), %ecx + movl %ebx, %eax + wrmsr + /* MTRR_PHYS_MASK */ + addl $1, %ecx + movl %esi, %eax + movl %edi, %edx + wrmsr + + /* Enable cache again. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + movl %eax, %cr0 + + /* Restore Callee saved registers */ + popl %edi + popl %esi + popl %edx + popl %ebx + popl %ebp + ret diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..103388f 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -107,6 +107,10 @@ void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, unsigned int type); int get_free_var_mtrr(void); +void set_var_mtrr_uncached(unsigned int reg, unsigned int base, + unsigned int size, unsigned int type); +__attribute__((cdecl)) void set_var_mtrr_uncached_asm(unsigned int reg, + msr_t base, msr_t mask); asmlinkage void display_mtrrs(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ff59d35ade125f60ed0002a386f41fd8ad54073 Gerrit-Change-Number: 36382 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/amd: Use common functions to pass UMA information to ramstage
by Arthur Heymans (Code Review) 08 Apr '20

08 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36292 ) Change subject: soc/amd: Use common functions to pass UMA information to ramstage ...................................................................... soc/amd: Use common functions to pass UMA information to ramstage This removes the custom implementation using the BIOSRAM scratchpad space. Change-Id: I97a14044a93d1188cacc488006abe50a112d0eb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/pi/Makefile.inc M src/soc/amd/common/block/pi/agesawrapper.c A src/soc/amd/common/block/pi/uma.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 10 files changed, 65 insertions(+), 122 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36292/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index edb3882..03cea2e 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -139,45 +139,6 @@ /* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */ #endif -#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE -/* biosram read/write - access registers at 0xfed80500 */ - -uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - -uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ -{ - return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); -} - -uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - -void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - -void biosram_write16(uint8_t reg, uint16_t value) -{ - biosram_write8(reg, value & 0xff); - value >>= 8; - biosram_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void biosram_write32(uint8_t reg, uint32_t value) -{ - biosram_write16(reg, value & 0xffff); - value >>= 16; - biosram_write16(reg + sizeof(uint16_t), value & 0xffff); -} -#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */ - #if SUPPORTS_ACPIMMIO_CMOSRAM_BASE /* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */ #endif diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 59ab9e5..879b9b9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -194,14 +194,6 @@ void pm2_write16(uint8_t reg, uint16_t value); void pm2_write32(uint8_t reg, uint32_t value); -/* Access BIOS RAM storage at 0xfed80500 */ -uint8_t biosram_read8(uint8_t reg); -uint16_t biosram_read16(uint8_t reg); -uint32_t biosram_read32(uint8_t reg); -void biosram_write8(uint8_t reg, uint8_t value); -void biosram_write16(uint8_t reg, uint16_t value); -void biosram_write32(uint8_t reg, uint32_t value); - /* Access ACPI registers at 0xfed80800 */ uint8_t acpi_read8(uint8_t reg); uint16_t acpi_read16(uint8_t reg); diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index 5afbb3e..41995f6 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -1,11 +1,13 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PI),y) +romstage-y += uma.c romstage-y += agesawrapper.c romstage-y += def_callouts.c romstage-y += heapmanager.c romstage-y += image.c romstage-y += refcode_loader.c +ramstage-y += uma.c ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += amd_resume_final.c diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 022a8bc..77afeab 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -205,8 +205,8 @@ top = PostParams->MemConfig.Sub4GCacheTop; save_ram_top(top); - save_uma_size(PostParams->MemConfig.UmaSize * 64 * KiB); - save_uma_base((u64)PostParams->MemConfig.UmaBase * 64 * KiB); + save_uma((u64)PostParams->MemConfig.UmaBase * 64 * KiB, + PostParams->MemConfig.UmaSize * 64 * KiB); print_init_post_settings(PostParams); diff --git a/src/soc/amd/common/block/pi/uma.c b/src/soc/amd/common/block/pi/uma.c new file mode 100644 index 0000000..5d46855 --- /dev/null +++ b/src/soc/amd/common/block/pi/uma.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <romstage_handoff.h> +#include <soc/southbridge.h> +#include <console/console.h> + + +struct save_uma { + uint64_t base; + uint32_t size; +}; + +void save_uma(uint64_t uma_base, uint32_t uma_size) +{ + struct save_uma save = { + .base = uma_base, + .size = uma_size + }; + if (save_romstage_info(&save, sizeof(save))) { + printk(BIOS_DEBUG, "Saving uma information failed!\n"); + return; + } +} + +void get_uma(uint64_t *uma_base, uint32_t *uma_size) +{ + struct save_uma save; + if (get_romstage_info(&save, sizeof(save))) { + printk(BIOS_ERR, "Getting saved uma information failed!\n"); + return; + } + *uma_base = save.base; + *uma_size = save.size; +} diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 36135f9..f52c622 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -261,14 +261,16 @@ void domain_set_resources(struct device *dev) { - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); + uint64_t uma_base; + uint32_t uma_size; uint32_t mem_useable = (uintptr_t)cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; int idx = 0x10; + get_uma(&uma_base, &uma_size); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 00e7b0f..1562dc7 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -576,27 +576,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index dd514ab..4504621 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -353,35 +353,19 @@ /** * @brief Save the UMA bize returned by AGESA * - * @param size = in bytes + * @param base, size = in bytes * * @return none */ -void save_uma_size(uint32_t size); +void save_uma(uint64_t uma_base, uint32_t uma_size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Get the UMA bize returned by AGESA * - * @param base = 64bit base address + * @param Pointer base, size = in bytes * * @return none */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); +void get_uma(uint64_t *uma_base, uint32_t *uma_size); /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..c6f7058 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -413,14 +413,16 @@ void domain_set_resources(struct device *dev) { - uint64_t uma_base = get_uma_base(); - uint32_t uma_size = get_uma_size(); + uint64_t uma_base; + uint32_t uma_size; uint32_t mem_useable = (uintptr_t)cbmem_top(); msr_t tom = rdmsr(TOP_MEM); msr_t high_tom = rdmsr(TOP_MEM2); uint64_t high_mem_useable; int idx = 0x10; + get_uma(&uma_base, &uma_size); + /* 0x0 -> 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d7a09aa..96e587d 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -36,6 +36,7 @@ #include <agesa_headers.h> #include <soc/nvs.h> #include <types.h> +#include <romstage_handoff.h> /* * Table of devices that need their AOAC registers enabled and waited @@ -648,27 +649,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a14044a93d1188cacc488006abe50a112d0eb8 Gerrit-Change-Number: 36292 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: lib/romstage_handoff: Add methods to pass on romstage information
by Arthur Heymans (Code Review) 08 Apr '20

08 Apr '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36291 ) Change subject: lib/romstage_handoff: Add methods to pass on romstage information ...................................................................... lib/romstage_handoff: Add methods to pass on romstage information Add 2 generic function that can be used to pass on information from romstage to ramstage. The implementation is such that the saving can be done even if cbmem is not set up initially. TODO: Does it need guarding because it needlessly increases .bss usage? Change-Id: I71bbe1b776cbc74468a6218b315894602b6152ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/include/romstage_handoff.h M src/lib/romstage_handoff.c 3 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36291/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88a..89d9478 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -77,6 +77,7 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_ROMSTAGE_SAVE 0xa7d1f2f3 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index db998ec..bbb0869 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -21,4 +21,11 @@ /* Return 1 if resuming or 0 if not. */ int romstage_handoff_is_resume(void); +/* Returns 0 on success, 1 if the info was copied to a buffer to be migrated + to cbmem later on, < 0 on failure. */ +int save_romstage_info(void *info, size_t info_size); + +/* Return 0 on success, else < 0 on failure */ +int get_romstage_info(void *info, size_t info_size); + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index 04ead0a..2f26194 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -77,3 +77,74 @@ return handoff->s3_resume; } + +static u8 save_buffer[256]; +static size_t used_buffer_size; +static int is_migrated; + +static void migrate_save_buffer(int is_recovery) +{ + if (used_buffer_size) + printk(BIOS_DEBUG, "Migrating the romstage save buffer to cbmem\n"); + is_migrated = 1; + save_romstage_info(save_buffer, used_buffer_size); +} + +ROMSTAGE_CBMEM_INIT_HOOK(migrate_save_buffer); + +int save_romstage_info(void *info, size_t save_size) +{ + const struct cbmem_entry *e; + + printk(BIOS_SPEW, "Romstage save: saving %p, size %zu\n", + info, save_size); + + e = cbmem_entry_find(CBMEM_ID_ROMSTAGE_SAVE); + if (e != NULL) { + if (cbmem_entry_size(e) > save_size) { + memcpy(cbmem_entry_start(e), info, save_size); + return 0; + } + cbmem_entry_remove(e); + } + + e = cbmem_entry_add(CBMEM_ID_ROMSTAGE_SAVE, save_size); + if (e == NULL && is_migrated) { + printk(BIOS_ERR, "Can't copy romstage save buffer to cbmem!\n"); + return -1; + } + + if (e != NULL) { + memcpy(cbmem_entry_start(e), info, save_size); + return 0; + } + + /* Cbmem is not yet up, save it for later */ + printk(BIOS_SPEW, "Romstage save: cbmem not yet up, saving info buffer for later\n"); + if (sizeof(save_buffer) < save_size) { + printk(BIOS_ERR, "Romstage save: buffer too small!\n"); + return -1; + } + memcpy(save_buffer, info, save_size); + used_buffer_size = save_size; + return 1; +} + +int get_romstage_info(void *info, size_t save_size) +{ + const struct cbmem_entry *e; + e = cbmem_entry_find(CBMEM_ID_ROMSTAGE_SAVE); + + if (e == NULL) { + printk(BIOS_ERR, "Can't find romstage save\n"); + return -1; + } + + if (save_size > cbmem_entry_size(e)) { + printk(BIOS_ERR, "Romstage save: requested size too large!\n"); + return -1; + } + + memcpy(info, cbmem_entry_start(e), save_size); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71bbe1b776cbc74468a6218b315894602b6152ba Gerrit-Change-Number: 36291 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: soc/amd/picasso: Convert TSEG and BERT info to cbmem
by Marshall Dawson (Code Review) 03 Apr '20

03 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36114 ) Change subject: soc/amd/picasso: Convert TSEG and BERT info to cbmem ...................................................................... soc/amd/picasso: Convert TSEG and BERT info to cbmem Remove the convoluted memory map calculation for cbmem_top() and put the two reserved regions into cbmem. There is no compellng reason to keep these regions above cbmem. AMD can lock any region with Tvalid and the appropriate mask. The memory pointed to by the BERT table simply needs to be reserved from the OS. Change-Id: I6fa0544d642bbd8e2b3c21c3d186459ac8f6d477 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/romstage.c 3 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36114/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index b54a8ef..cf1d2d4 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -41,6 +41,6 @@ #define EARLY_DRAM_MTRR_TOP \ (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) -#define EARLY_RAMSTAGE_MTRR_SZ (32 * MiB) +#define EARLY_RAMSTAGE_MTRR_SZ (32 * MiB + CONFIG_SMM_TSEG_SIZE) #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 09af7e4..7b21bb8 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -28,6 +28,8 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h> +#define BERT_REGION_MAX_SIZE 0x100000 + void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); @@ -38,24 +40,19 @@ return biosram_read32(BIOSRAM_CBMEM_TOP); } -#if CONFIG(ACPI_BERT) - #if CONFIG_SMM_TSEG_SIZE == 0x0 - #define BERT_REGION_MAX_SIZE 0x100000 - #else - /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ - #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE - #endif -#else - #define BERT_REGION_MAX_SIZE 0 -#endif - void bert_reserved_region(void **start, size_t *size) { - if (CONFIG(ACPI_BERT)) - *start = cbmem_top(); - else - start = NULL; - *size = BERT_REGION_MAX_SIZE; + const struct cbmem_entry *bert; + + *start = 0; + *size = 0; + + bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA); + if (!bert) + return; + + *start = cbmem_entry_start(bert); + *size = cbmem_entry_size(bert); } void *cbmem_top(void) @@ -66,19 +63,7 @@ return 0; /* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() - - CONFIG_SMM_TSEG_SIZE - - BERT_REGION_MAX_SIZE, 8*MiB); -} - -static uintptr_t smm_region_start(void) -{ - return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; -} - -static size_t smm_region_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; + return (void *)ALIGN_DOWN(restore_top_of_low_cacheable(), 8 * MiB); } /* @@ -106,12 +91,39 @@ void smm_region(uintptr_t *start, size_t *size) { static int once; + const struct cbmem_entry *smm; - *start = smm_region_start(); - *size = smm_region_size(); + *start = 0; + *size = 0; + + smm = cbmem_entry_find(CBMEM_ID_SMM_TSEG_SPACE); + if (!smm) + return; + + *start = ALIGN_UP((uintptr_t)cbmem_entry_start(smm), CONFIG_SMM_TSEG_SIZE); + *size = CONFIG_SMM_TSEG_SIZE; if (!once) { clear_tvalid(); once = 1; } } + +/* Add or find TSEG and BERT storage prior to ramstage. ramstage may need + * to be recovered from cached space in TSEG. BERT storage is consumed at + * ROMSTAGE_CBMEM_INIT_HOOK and ordering can't be enforced for a hook. + */ +static void alloc_reserved_in_cbmem(int unused) +{ + void *p; + + /* Make large enough so TSEG can have alignment = size, allowing a + * good mask. + */ + p = cbmem_add(CBMEM_ID_SMM_TSEG_SPACE, 2 * CONFIG_SMM_TSEG_SIZE); + + if (CONFIG(ACPI_BERT)) + p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, BERT_REGION_MAX_SIZE); +} + +ROMSTAGE_CBMEM_INIT_HOOK(alloc_reserved_in_cbmem) diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index eb39cc4..f4ae24b 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -78,27 +78,24 @@ static void set_mtrrs_for_ramstage(void) { - uintptr_t smm_base; - size_t smm_size; - uintptr_t smm_top; uintptr_t mem_top; uintptr_t ramstage_wb_base; size_t ramstage_wb_size; int mtrr; - smm_region(&smm_base, &smm_size); - smm_top = smm_base + smm_size; - mem_top = (uintptr_t)cbmem_top(); - /* Cache anticipated ramstage location through the top of TSEG */ - ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; - ramstage_wb_size = smm_top - ramstage_wb_base; + /* Cache anticipated ramstage location through the top of cbmem. + * Unlike some other implementations, TSEG is in cbmem so it will + * be cached as well. + */ + ramstage_wb_size = EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_base = mem_top - ramstage_wb_size; - /* Make sure MTRR base and size are usable */ + /* Ensure base and size are usable in a single MTRR pair */ if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); - ramstage_wb_base = smm_top - ramstage_wb_size; + ramstage_wb_base = mem_top - ramstage_wb_size; } if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa0544d642bbd8e2b3c21c3d186459ac8f6d477 Gerrit-Change-Number: 36114 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/amd/picasso: Add basic MTRR settings to hybrid romstage
by Marshall Dawson (Code Review) 03 Apr '20

03 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35297 ) Change subject: soc/amd/picasso: Add basic MTRR settings to hybrid romstage ...................................................................... soc/amd/picasso: Add basic MTRR settings to hybrid romstage Program the system flash as WP to allow it to be cacheable. This was done during bootblock on previous systems. Since this code and its data are in DRAM, set them to WP. Prior to running ramstage, set its anticipated target location as WP also. Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/romstage.c 2 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35297/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 66e6650..15f319f 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -25,8 +25,18 @@ #define ROMSTAGE_SIZE (64 * KiB) /* Enforced by Makefile.inc for PSP info */ #define ROMSTAGE_TOP (CONFIG_ROMSTAGE_ADDR + ROMSTAGE_SIZE) +#define EARLYRAM_TOP (ROMSTAGE_TOP + CONFIG_EARLYRAM_SIZE) #if ROMSTAGE_TOP & 0xffff # error Top of the BIOS binary image must be 64KB aligned #endif +#define EARLY_DRAM_MTRR_BASE \ + ALIGN_DOWN(CONFIG_ROMSTAGE_ADDR, 32 * MiB) +#define EARLY_DRAM_MTRR_SIZE \ + ALIGN_UP(ROMSTAGE_SIZE + CONFIG_EARLYRAM_SIZE, 32 * MiB) +#define EARLY_DRAM_MTRR_TOP \ + (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) + +#define EARLY_RAMSTAGE_MTRR_SZ (16 * MiB) + #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 92361f9..b4c8013 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -21,8 +21,10 @@ #include <delay.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/x86/bist.h> +#include <cpu/amd/mtrr.h> #include <cpu/amd/msr.h> #include <cbmem.h> #include <console/console.h> @@ -56,10 +58,68 @@ fch_early_init(); } +static int set_early_mtrrs(void) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, EARLY_DRAM_MTRR_BASE, EARLY_DRAM_MTRR_SIZE, + MTRR_TYPE_WRBACK); + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); + return 0; +} + +static void set_mtrrs_for_ramstage(void) +{ + uintptr_t smm_base; + size_t smm_size; + uintptr_t smm_top; + uintptr_t mem_top; + uintptr_t ramstage_wb_base; + size_t ramstage_wb_size; + int mtrr; + + smm_region(&smm_base, &smm_size); + smm_top = smm_base + smm_size; + + mem_top = (uintptr_t)cbmem_top(); + + /* Cache anticipated ramstage location through the top of TSEG */ + ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_size = smm_top - ramstage_wb_base; + + /* Make sure MTRR base and size are usable */ + if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { + ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); + ramstage_wb_base = smm_top - ramstage_wb_size; + } + if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { + printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); + return; + } + + mtrr = get_free_var_mtrr(); + if (mtrr >= 0) + set_var_mtrr(mtrr, ramstage_wb_base, ramstage_wb_size, + MTRR_TYPE_WRBACK); + else + printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n"); +} + asmlinkage void soc_hybrid_romstage_entry(uint32_t bist, uint64_t early_tsc) { uintptr_t top_of_mem; int s3_resume; + int early_mtrr_err; post_code(0x40); if (CONFIG(COLLECT_TIMESTAMPS)) { @@ -70,6 +130,7 @@ /* Many of these tasks typically happen in bootblock, but execution * begins in romstage for this device. */ post_code(0x41); + early_mtrr_err = set_early_mtrrs(); post_code(0x42); romstage_soc_early_init(); @@ -96,6 +157,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + if (early_mtrr_err) + printk(BIOS_WARNING, "Early MTRRs were not set properly\n"); + post_code(0x48); if (!s3_resume && CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); @@ -111,6 +175,7 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x4b); + set_mtrrs_for_ramstage(); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Gerrit-Change-Number: 35297 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: security/vboot: Decouple measured boot from verified boot
by Bill XIE (Code Review) 31 Mar '20

31 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35077 ) Change subject: security/vboot: Decouple measured boot from verified boot ...................................................................... security/vboot: Decouple measured boot from verified boot As said in CB:34977, currently TPM and CRTM are initialized just before romstage loads a file within CBFS, or initialized in vboot_logic() if CONFIG_VBOOT is set. Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/lib/cbfs.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/misc.h M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 8 files changed, 136 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35077/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..246e741 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -327,6 +327,9 @@ * devices. */ const struct cbfs_locator __weak cbfs_master_header_locator = { .name = "Master Header Locator", +#if !CONFIG(VBOOT) && CONFIG(VBOOT_MEASURED_BOOT) + .prepare = measured_boot_init_crtm, +#endif .locate = cbfs_master_header_props, }; diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index a2d32cf..cb936cf 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -8,7 +8,10 @@ romstage-y += tss/tcg-1.2/tss.c verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c -postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tss/tcg-1.2/tss.c +endif ## TSPI @@ -16,7 +19,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c @@ -45,7 +51,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..36dd3dd 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -20,7 +20,7 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) #include <vb2_api.h> #include <vb2_sha.h> #include <assert.h> @@ -220,7 +220,7 @@ return TPM_SUCCESS; } -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, const char *rname) { @@ -279,4 +279,4 @@ printk(BIOS_DEBUG, "TPM: Measured %s into PCR %d\n", rname, pcr); return TPM_SUCCESS; } -#endif /* VBOOT */ +#endif /* VBOOT || VBOOT_MEASURED_BOOT */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c6..955e8a6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -menu "Verified Boot (vboot)" +menu "vboot functionalities" config VBOOT bool "Verify firmware with vboot." @@ -21,21 +21,17 @@ select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2 depends on !MISSING_BOARD_RESET help - Enabling VBOOT will use vboot to verify the components of the firmware + Enabling verified voot will use vboot to verify the components of the firmware (stages, payload, etc). -if VBOOT - -comment "Anti-Rollback Protection disabled because mocking secdata is enabled." - depends on VBOOT_MOCK_SECDATA - config VBOOT_MEASURED_BOOT - bool "Enable Measured Boot" + bool "Measure firmware components with vboot." default n depends on TPM1 || TPM2 depends on !VBOOT_RETURN_FROM_VERSTAGE help - Enables measured boot mode in vboot (experimental) + Enables measured boot will use vboot to measure the components of the firmware + (stages, payload, etc) to PCRs within TPM. (experimental) config VBOOT_MEASURED_BOOT_RUNTIME_DATA string "Runtime data whitelist" @@ -45,6 +41,13 @@ Runtime data whitelist of cbfs filenames. Needs to be a comma separated list +if VBOOT + +comment "Anti-Rollback Protection disabled because mocking secdata is enabled." + depends on VBOOT_MOCK_SECDATA + +comment "A non-trivial fmd file with sections required by vboot is needed." + config VBOOT_SLOTS_RW_A bool "Firmware RO + RW_A" help diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f10..0729d9f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -14,6 +14,58 @@ ## GNU General Public License for more details. ## +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) + +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c +endif + + +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $(filter-out -I$(obj),$(1)))) + +# call with $1 = stage name to create rules for building the library +# for the stage and adding it to the stage's set of object files. +define vboot-for-stage +VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) +VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) +VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes +VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG + +$$(VB2_LIB_$(1)): $(obj)/config.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ + CC="$$(CC_$(1))" \ + CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ + $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ + V=$(V) \ + fwlib20 + +$(1)-srcs += $$(VB2_LIB_$(1)) + +endef # vboot-for-stage + +CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include + +$(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) +$(eval $(call vboot-for-stage,ramstage)) +$(eval $(call vboot-for-stage,postcar)) + +endif # CONFIG_VBOOT_MEASURED_BOOT || CONFIG_VBOOT + +ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) +bootblock-y += vboot_crtm.c +verstage-y += vboot_crtm.c +romstage-y += vboot_crtm.c +ramstage-y += vboot_crtm.c +postcar-y += vboot_crtm.c +endif # CONFIG_VBOOT_MEASURED_BOOT + ifeq ($(CONFIG_VBOOT),y) bootblock-y += bootmode.c @@ -22,6 +74,12 @@ verstage-y += bootmode.c postcar-y += bootmode.c +bootblock-y += vboot_common.c +verstage-y += vboot_common.c +romstage-y += vboot_common.c +ramstage-y += vboot_common.c +postcar-y += vboot_common.c + # When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by # the time verstage runs. ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) @@ -63,19 +121,7 @@ verstage-y += vboot_loader.c postcar-y += vboot_loader.c -bootblock-y += vboot_common.c -verstage-y += vboot_common.c -romstage-y += vboot_common.c -ramstage-y += vboot_common.c -postcar-y += vboot_common.c -ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) -bootblock-y += vboot_crtm.c -verstage-y += vboot_crtm.c -romstage-y += vboot_crtm.c -ramstage-y += vboot_crtm.c -postcar-y += vboot_crtm.c -endif bootblock-y += common.c verstage-y += vboot_logic.c @@ -89,10 +135,6 @@ romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif -ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) -verstage-y += tpm_common.c -endif - romstage-y += vboot_logic.c romstage-y += common.c @@ -101,41 +143,6 @@ romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ - $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $(filter-out -I$(obj),$(1)))) - -# call with $1 = stage name to create rules for building the library -# for the stage and adding it to the stage's set of object files. -define vboot-for-stage -VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) -VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) -VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes -VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG - -$$(VB2_LIB_$(1)): $(obj)/config.h - printf " MAKE $(subst $(obj)/,,$(@))\n" - +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ - CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ - $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ - V=$(V) \ - fwlib20 - -$(1)-srcs += $$(VB2_LIB_$(1)) - -endef # vboot-for-stage - -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include - -$(eval $(call vboot-for-stage,bootblock)) -$(eval $(call vboot-for-stage,romstage)) -$(eval $(call vboot-for-stage,ramstage)) -$(eval $(call vboot-for-stage,postcar)) - ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) $(eval $(call vboot-for-stage,verstage)) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 725f5fd..8761b84 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -127,5 +127,21 @@ } } +static inline int vboot_crtm_is_set(void) +{ + extern int crtm_is_set; + if (CONFIG(VBOOT)) { + return vboot_logic_executed(); + } else if(ENV_ROMSTAGE) { + return car_get_var(crtm_is_set); + } else { +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } +} + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..92f05e5 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -19,11 +19,13 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/misc.h> #include <string.h> +#include <timestamp.h> /* * This functions sets the TCPA log namespace * for the cbfs file (region) lookup. */ + static int create_tcpa_metadata(const struct region_device *rdev, const char *cbfs_name, char log_string[TCPA_PCR_HASH_NAME]) { @@ -90,7 +92,8 @@ } } - if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE) || + CONFIG(VBOOT_MEASURED_BOOT)) { struct cbfsf romstage_data; /* measure romstage from RO */ if (cbfs_boot_locate(&romstage_data, @@ -164,7 +167,7 @@ struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; - if (!vboot_logic_executed()) + if (!vboot_crtm_is_set()) return 0; cbfsf_file_type(fh, &cbfs_type); @@ -193,3 +196,26 @@ return tpm_measure_region(&rdev, pcr_index, tcpa_metadata); } + +int crtm_is_set CAR_GLOBAL; + +void measured_boot_init_crtm(void) +{ + if (ENV_ROMSTAGE) { + timestamp_add_now(TS_START_TPMINIT); + int result = tpm_setup(vboot_platform_is_resuming()); + timestamp_add_now(TS_END_TPMINIT); + + if (result == TPM_SUCCESS) { + result = vboot_init_crtm(); + if(result != VB2_SUCCESS) { + printk(BIOS_INFO, + "Initializing CRTM failed!"); + } else { + car_set_var(crtm_is_set, 1); + } + } else { + printk(BIOS_INFO, "TPM setup failed!"); + } + } +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..87bfa2d 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -53,6 +53,10 @@ * return 0 if successful, else an error */ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +/* + * Initialize crtm without running vboot_logic() + */ +void measured_boot_init_crtm(void); #else #define vboot_measure_cbfs_hook(fh, name) 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Gerrit-Change-Number: 35077 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

12 184

Change in ...coreboot[master]: SKL: Add ACPI brightness control
by Matthew Garrett (Code Review) 28 Mar '20

28 Mar '20

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32549 Change subject: SKL: Add ACPI brightness control ...................................................................... SKL: Add ACPI brightness control Hook up the generic src/drivers/intel/gma ACPI backlight control for Skylake. Based on a patch by Matt DeVillier <matt.devillier(a)gmail.com>. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h 7 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32549/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..6489e8e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -33,6 +33,10 @@ pci_dev_init(dev); } +__weak void gma_ssdt(struct device *dev) +{ +} + static uintptr_t graphics_get_bar(unsigned long index) { struct device *dev = SA_DEV_IGD; @@ -104,6 +108,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt_generator = gma_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 6be7661..077f0db 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -51,4 +51,7 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask); uintptr_t graphics_get_memory_base(void); +void gma_ssdt(struct device *dev); +struct i915_gpu_controller_info *intel_igd_get_controller_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..6963f70 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + BRTL, 32, // 0x54 - 0x57 Brightness Level + CSTE, 16, // 0x58 - 0x59 Current display state + NSTE, 16, // 0x5a - 0x5b Next display state /* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..f0095bc 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -56,6 +56,9 @@ /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* Graphics */ +#include <drivers/intel/gma/acpi/pch.asl> + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e7..51bb740 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/i915.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -580,6 +581,8 @@ /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67a..1be5f9d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -122,3 +122,22 @@ printk(BIOS_DEBUG, "current = %lx\n", current); return current; } + +struct i915_gpu_controller_info *intel_igd_get_controller_info(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + if (!dev) + return NULL; + struct soc_intel_skylake_config *chip = dev->chip_info; + return &chip->gfx; +} + +void gma_ssdt(struct device *dev) +{ + struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(); + + if (!gfx) + return; + + drivers_intel_gma_displays_ssdt_generate(gfx); +} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..5a2ca38 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u32 brtl; /* 0x54 - 0x57 Brightness Level */ + u16 cste; /* 0x58 - 0x59 Current display state */ + u16 nste; /* 0x5a - 0x5b Next display state */ + u8 rsvd[88]; /* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Gerrit-Change-Number: 32549 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

8 23

Change in ...coreboot[master]: Disable SeaBIOS options not supported by hardware: scripts to apply t...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33885 Change subject: Disable SeaBIOS options not supported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options not supported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:33870 and CB:33871 to disable SeaBIOS options not supported by G505S and AM1I-A hardware. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/33870 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/33871 src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33885/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..c1212bf --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./0cd2b7a.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..5e4c1ef --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./053e2ea.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./0cd2b7a.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..0ce0113c --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +rm -f "./053e2ea.diff" +wget "https://review.coreboot.org/changes/33870/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +rm -f "./0cd2b7a.diff" +wget "https://review.coreboot.org/changes/33871/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./0cd2b7a.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..5135520 --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +ed3f92502e35897256e364e146ad7515414552c4e4e87031bfaae1f30ecdad1d ./053e2ea.diff +6c5fd1060ccf3b84687eb76594ed63a76472c573ea968d9efec40f4c3eccb53d ./0cd2b7a.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e Gerrit-Change-Number: 33885 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 11

Change in ...coreboot[master]: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by h...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33871 Change subject: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this motherboard. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33871/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbe..6d88992 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -54,4 +54,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 Gerrit-Change-Number: 33871 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mb/*/*/gpio: Remove null-initialized members
by Peter Lemenkov (Code Review) 27 Mar '20

27 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35900 ) Change subject: mb/*/*/gpio: Remove null-initialized members ...................................................................... mb/*/*/gpio: Remove null-initialized members Made with this oneliner: $ find src/mainboard/ -type f -name gpio.c -print -exec sed -i -e '/^\s*.gpio[0-9]\+\s*=\s*$GPIO_MODE_NATIVE\|GPIO_DIR_OUTPUT\|GPIO_NO_INVERT\|GPIO_LEVEL_LOW\|GPIO_NO_BLINK\|GPIO_RESET_PWROK$\s*$/d' {} \; It didn't touch lines with comments. Change-Id: I2799293585bcfcf41c93a9dbe358cd806f9374f5 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/apple/macbook21/gpio.c M src/mainboard/apple/macbookair4_2/gpio.c M src/mainboard/asrock/b75pro3-m/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c M src/mainboard/asrock/h81m-hds/gpio.c M src/mainboard/asus/h61m-cs/gpio.c M src/mainboard/asus/maximus_iv_gene-z/gpio.c M src/mainboard/asus/p5gc-mx/gpio.c M src/mainboard/asus/p5qc/gpio.c M src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c M src/mainboard/asus/p8h61-m_lx/gpio.c M src/mainboard/asus/p8h61-m_pro/gpio.c M src/mainboard/asus/p8z77-m_pro/gpio.c M src/mainboard/compulab/intense_pc/gpio.c M src/mainboard/foxconn/d41s/gpio.c M src/mainboard/foxconn/g41s-k/gpio.c M src/mainboard/getac/p470/gpio.c M src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c M src/mainboard/gigabyte/ga-g41m-es2l/gpio.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c M src/mainboard/google/link/gpio.c M src/mainboard/google/parrot/gpio.c M src/mainboard/google/stout/gpio.c M src/mainboard/hp/2570p/gpio.c M src/mainboard/hp/2760p/gpio.c M src/mainboard/hp/8460p/gpio.c M src/mainboard/hp/8470p/gpio.c M src/mainboard/hp/8770w/gpio.c M src/mainboard/hp/compaq_8200_elite_sff/gpio.c M src/mainboard/hp/folio_9470m/gpio.c M src/mainboard/hp/revolve_810_g1/gpio.c M src/mainboard/hp/z220_sff_workstation/gpio.c M src/mainboard/ibase/mb899/gpio.c M src/mainboard/intel/d510mo/gpio.c M src/mainboard/intel/d945gclf/gpio.c M src/mainboard/intel/dcp847ske/gpio.c M src/mainboard/intel/dg41wv/gpio.c M src/mainboard/intel/dg43gt/gpio.c M src/mainboard/kontron/986lcd-m/gpio.c M src/mainboard/lenovo/l520/gpio.c M src/mainboard/lenovo/s230u/gpio.c M src/mainboard/lenovo/t400/variants/r500/gpio.c M src/mainboard/lenovo/t400/variants/t400/gpio.c M src/mainboard/lenovo/t420/gpio.c M src/mainboard/lenovo/t420s/gpio.c M src/mainboard/lenovo/t430s/variants/t430s/gpio.c M src/mainboard/lenovo/t430s/variants/t431s/gpio.c M src/mainboard/lenovo/t520/variants/t520/gpio.c M src/mainboard/lenovo/t520/variants/w520/gpio.c M src/mainboard/lenovo/t530/variants/t530/gpio.c M src/mainboard/lenovo/t530/variants/w530/gpio.c M src/mainboard/lenovo/t60/gpio.c M src/mainboard/lenovo/thinkcentre_a58/gpio.c M src/mainboard/lenovo/x131e/gpio.c M src/mainboard/lenovo/x1_carbon_gen1/gpio.c M src/mainboard/lenovo/x200/gpio.c M src/mainboard/lenovo/x201/gpio.c M src/mainboard/lenovo/x220/variants/x1/gpio.c M src/mainboard/lenovo/x220/variants/x220/gpio.c M src/mainboard/lenovo/x230/gpio.c M src/mainboard/lenovo/x60/gpio.c M src/mainboard/msi/ms7707/gpio.c M src/mainboard/packardbell/ms2290/gpio.c M src/mainboard/roda/rk886ex/gpio.c M src/mainboard/roda/rk9/gpio.c M src/mainboard/roda/rv11/gpio.c M src/mainboard/samsung/lumpy/gpio.c M src/mainboard/samsung/stumpy/gpio.c M src/mainboard/sapphire/pureplatinumh61/gpio.c M src/mainboard/supermicro/x10slm-f/gpio.c 79 files changed, 0 insertions(+), 4,228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35900/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2799293585bcfcf41c93a9dbe358cd806f9374f5 Gerrit-Change-Number: 35900 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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