coreboot-gerrit October 2019

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Change in coreboot[master]: [WIP] arch/x86: Add linker script for early DRAM
by Kyösti Mälkki (Code Review) 29 Apr '20

29 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35035 ) Change subject: [WIP] arch/x86: Add linker script for early DRAM ...................................................................... [WIP] arch/x86: Add linker script for early DRAM Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/early_dram.ld 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35035/1 diff --git a/src/arch/x86/early_dram.ld b/src/arch/x86/early_dram.ld new file mode 100644 index 0000000..24b9551 --- /dev/null +++ b/src/arch/x86/early_dram.ld @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file is included inside a SECTIONS block */ +. = CONFIG_DCACHE_RAM_BASE; +.car.data . (NOLOAD) : { + _car_region_start = . ; + + /* Stack for CAR stages. Since it persists across all stages that + * use CAR it can be reused. The chipset/SoC is expected to provide + * the stack size. */ +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) + _car_stack_start = .; + . += CONFIG_DCACHE_BSP_STACK_SIZE; + _car_stack_end = .; +#endif + /* The pre-ram cbmem console as well as the timestamp region are fixed + * in size. Therefore place them above the car global section so that + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ + PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) + + TIMESTAMP(., 0x200) + + _car_ehci_dbg_info_start = .; + /* Reserve sizeof(struct ehci_dbg_info). */ + . += 80; + _car_ehci_dbg_info_end = .; + + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); +} + +_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); +#if !CONFIG(CAR_GLOBAL_MIGRATION) +_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Gerrit-Change-Number: 35035 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

10 109

Change in coreboot[master]: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
by Sridhar Siricilla (Code Review) 28 Apr '20

28 Apr '20

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35227 to review the following change. Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ...................................................................... src/soc/intel/common/block/cse: Add funtion to send CSE reset msg Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET. Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7697a4a..9585a09 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -69,10 +69,18 @@ #define HECI_OP_MODE_SEC_OVERRIDE 5 +/* Global Reset Command ID */ +#define MKHI_GLOBAL_RESET_REQ 0xb +#define MKHI_GROUP_ID_CBM 0 + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 2 + static struct cse_device { uintptr_t sec_bar; } g_cse; +/* HFSTS1 */ union me_hfs { u32 data; struct { @@ -595,6 +603,54 @@ return reg; } +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be GLOBAL_RESET/ + * HOST_RESET_ONLY/HOST_RESET_ONLY. + */ +int send_heci_reset_req_message(u8 rst_type) +{ + int status; + struct reset_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + } __packed reply; + struct reset_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u8 req_origin; + u8 reset_type; + } __packed; + struct reset_message msg = { + .group_id = MKHI_GROUP_ID_CBM, + .cmd = MKHI_GLOBAL_RESET_REQ, + .req_origin = GR_ORIGIN_BIOS_POST, + .reset_type = rst_type + }; + size_t reply_size; + + if (!((rst_type == GLOBAL_RESET) + || (rst_type == HOST_RESET_ONLY) + || (rst_type == CSE_RESET_ONLY))) { + return -1; + } + + heci_reset(); + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + printk(BIOS_ERR, "HECI Global Reset(type=%d) Command\n", rst_type); + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); + if (status != 1) + return -1; + + printk(BIOS_DEBUG, "HECI GBL RST success!\n"); + return 0; +} #if ENV_RAMSTAGE diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 82e07cf..ceeca88e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -70,6 +70,13 @@ */ int wait_cse_rec(void); +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be + * GLOBAL_RESET/HOST_RESET_ONLY/HOST_RESET_ONLY. + * Returns -1 on failure a 0 on success. + */ +int send_heci_reset_req_message(u8 rst_type); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 @@ -83,4 +90,11 @@ PCI_ME_HFSTS6 = 0x6C, }; + +/* Command GLOBAL_RESET_REQ Reset Types */ +#define GLOBAL_RESET 1 +#define HOST_RESET_ONLY 2 +#define CSE_RESET_ONLY 3 + + #endif // SOC_INTEL_COMMON_MSR_H -- To view, visit https://review.coreboot.org/c/coreboot/+/35227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Gerrit-Change-Number: 35227 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/lockdown: Write-protect WP_RO
by Patrick Rudolph (Code Review) 28 Apr '20

28 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32705 Change subject: security/lockdown: Write-protect WP_RO ...................................................................... security/lockdown: Write-protect WP_RO Add another choice to boot media protection and write-protect WP_RO in case VBOOT is enabled. Tested on Lenovo T520: The WP_RO region is write-protected. Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/bootmedia.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32705/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index bb4d072..1e982d8 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -15,6 +15,18 @@ config BOOTMEDIA_LOCK_NONE bool "Don't lock boot media sections" +config BOOTMEDIA_LOCK_VBOOT_RO + bool "Write-protect WP_RO region in boot media" + depends on VBOOT + help + Select this if you want to write-protect the WP_RO region as specified + in the VBOOT FMAP. You will only be able to write the regions + FW_MAIN_A/FW_MAIN_B, which are not write-protected using the internal + programmer. + The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + config BOOTMEDIA_LOCK_RO bool "Write-protect the whole boot media" help diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c index 8fb4ae9..6fa2de2 100644 --- a/src/security/lockdown/bootmedia.c +++ b/src/security/lockdown/bootmedia.c @@ -17,6 +17,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <bootstate.h> +#include <fmap.h> /* * Enable write protection on the WP_RO region of the bootmedia. @@ -47,8 +48,23 @@ "of whole bootmedia\n"); locked = true; } - } + } else if (CONFIG(BOOTMEDIA_LOCK_VBOOT_RO)) { + struct region_device dev; + if (fmap_locate_area_as_rdev("WP_RO", &dev) < 0) { + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); + } else { + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(&dev, wp_prot[i]) < 0) + continue; + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "WP_RO region\n"); + locked = true; + } + } + } if (!locked) printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Gerrit-Change-Number: 32705 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security: Add common boot media write protection
by Patrick Rudolph (Code Review) 28 Apr '20

28 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32704 Change subject: security: Add common boot media write protection ...................................................................... security: Add common boot media write protection Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Tested on Lenovo T520. The whole flash is protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/Kconfig M src/security/Makefile.inc A src/security/lockdown/Kconfig A src/security/lockdown/Makefile.inc A src/security/lockdown/bootmedia.c M src/soc/intel/common/block/fast_spi/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/finalize.c 8 files changed, 124 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32704/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..99cb054 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/lockdown/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..a74e498 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += lockdown diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig new file mode 100644 index 0000000..bb4d072 --- /dev/null +++ b/src/security/lockdown/Kconfig @@ -0,0 +1,46 @@ + +config SECURITY_BOOTMEDIA_LOCKDOWN + bool + default n + help + Platform support the locking of boot media. This can be for example + SPI controller protected regions or flash status register locking. + +if SECURITY_BOOTMEDIA_LOCKDOWN + +choice + prompt "Boot media protection" + default BOOTMEDIA_LOCK_NONE + +config BOOTMEDIA_LOCK_NONE + bool "Don't lock boot media sections" + +config BOOTMEDIA_LOCK_RO + bool "Write-protect the whole boot media" + help + Select this if you want to write-protect the whole firmware boot + media. The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the flash chip using the + internal programmer any more. + +config BOOTMEDIA_LOCK_NO_ACCESS + bool "Read- and write-protect the whole boot media" + help + Select this if you want to protect the firmware boot media against + all further accesses. On platforms that memory map a part of the + boot media the corresponding region is still readable. + The locking will take place during the chipset lockdown, which is + either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or + has to be triggered later (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the boot media using the + internal programmer any more. + +endchoice + +endif diff --git a/src/security/lockdown/Makefile.inc b/src/security/lockdown/Makefile.inc new file mode 100644 index 0000000..c287b9b --- /dev/null +++ b/src/security/lockdown/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SECURITY_BOOTMEDIA_LOCKDOWN) += bootmedia.c diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c new file mode 100644 index 0000000..8fb4ae9 --- /dev/null +++ b/src/security/lockdown/bootmedia.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <bootstate.h> + +/* + * Enable write protection on the WP_RO region of the bootmedia. + */ +static void security_lockdown_bootmedia(void *unused) +{ + static const int wp_prot[] = {MEDIA_WP, CTRLR_WP}; + const struct region_device *rdev; + bool locked = false; + + if (CONFIG(BOOTMEDIA_LOCK_RO)) { + rdev = boot_device_ro(); + + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(rdev, wp_prot[i]) < 0) + continue; + + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "whole bootmedia\n"); + locked = true; + } + } else if (CONFIG(BOOTMEDIA_LOCK_NO_ACCESS)) { + rdev = boot_device_ro(); + if (boot_device_wp_region(rdev, CTRLR_RWP) == 0) { + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled read- and write protection" + "of whole bootmedia\n"); + locked = true; + } + } + + if (!locked) + printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); +} + +/* BS_POST_DEVICE will lock the hardware */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, security_lockdown_bootmedia, + NULL); diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 4bd1f59..ff02844 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_FAST_SPI bool + select SECURITY_BOOTMEDIA_LOCKDOWN help Intel Processor common FAST_SPI support diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..39234a8 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI def_bool n select SPI_FLASH + select SECURITY_BOOTMEDIA_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n @@ -68,42 +69,3 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON - -if SOUTHBRIDGE_INTEL_COMMON_FINALIZE - -choice - prompt "Flash locking during chipset lockdown" - default LOCK_SPI_FLASH_NONE - -config LOCK_SPI_FLASH_NONE - bool "Don't lock flash sections" - -config LOCK_SPI_FLASH_RO - bool "Write-protect all flash sections" - help - Select this if you want to write-protect the whole firmware flash - chip. The locking will take place during the chipset lockdown, which - is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) - or has to be triggered later (e.g. by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -config LOCK_SPI_FLASH_NO_ACCESS - bool "Write-protect all flash sections and read-protect non-BIOS sections" - help - Select this if you want to protect the firmware flash against all - further accesses (with the exception of the memory mapped BIOS re- - gion which is always readable). The locking will take place during - the chipset lockdown, which is either triggered by coreboot (when - INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. - by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -endchoice - -endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 80c65bb..6f7934a 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -28,16 +28,6 @@ { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (CONFIG(LOCK_SPI_FLASH_RO) || - CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { - int i; - u32 lockmask = 1UL << 31; - if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) - lockmask |= 1 << 15; - for (i = 0; i < 20; i += 4) - RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; - } - /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Gerrit-Change-Number: 32704 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Force retraining memory if requested
by Hung-Te Lin (Code Review) 22 Apr '20

22 Apr '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36251 ) Change subject: soc/mediatek/mt8183: Force retraining memory if requested ...................................................................... soc/mediatek/mt8183: Force retraining memory if requested To allow retraining memory without hotkey (for example in manufacturing process), we want to enforce re-training when the recovery reason is set to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running "crossystem recovery_request=0xc4"). On x86 (MRC cache) this is primarily used for ensuring RO calibration data is filled; and on MT8183 we have only RW calibration, but it seems totally fine to extend that to RW. BRANCH=kukui BUG=None TEST=boots; crossystem recovery_reason=0xc4; reboot Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/36251/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 2a4ebbd..b9ed619 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -169,7 +169,8 @@ /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); - if (vboot_recovery_mode_memory_retrain()) { + if (vboot_recovery_mode_memory_retrain() || + vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { printk(BIOS_WARNING, "Retrain memory in next boot\n"); /* Use 0xFF as erased flash data. */ memset(dparam, 0xff, sizeof(*dparam)); -- To view, visit https://review.coreboot.org/c/coreboot/+/36251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9 Gerrit-Change-Number: 36251 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: Add chip.h setting for PCIe ASPM
by Thomas Heijligen (Code Review) 22 Apr '20

22 Apr '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31351 to review the following change. Change subject: soc/intel/apl: Add chip.h setting for PCIe ASPM ...................................................................... soc/intel/apl: Add chip.h setting for PCIe ASPM We don't use a direct mapping to the UPD values so we don't have to set it to the default `auto` in all devicetrees. Change-Id: I169722c3c63be66772cb57a429ec7b83230fa234 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31351/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3634509..cfe8d4a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -669,6 +669,7 @@ { FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; + int i; /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); @@ -693,6 +694,11 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + for (i = 0; i < ARRAY_SIZE(silconfig->PcieRpAspm); ++i) { + if (cfg->pcie_rp_aspm[i] != ASPM_IGNORE) + silconfig->PcieRpAspm[i] = cfg->pcie_rp_aspm[i] - 1; + } + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..b8f9f8c 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -57,6 +57,18 @@ /* De-emphasis enable configuration for each PCIe root port */ uint8_t pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; + /* ASPM enable setting for each PCIe root port */ + enum { + ASPM_IGNORE = 0, + /* Enumeration values below are off-by-one compared to the + UPD to have the default 0 ignore the devicetree setting: */ + ASPM_DISABLED, + ASPM_L0S, + ASPM_L1, + ASPM_L0SL1, + ASPM_AUTO, + } pcie_rp_aspm[MAX_PCIE_PORTS]; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I169722c3c63be66772cb57a429ec7b83230fa234 Gerrit-Change-Number: 31351 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: sc7180: Add SPI QUP driver
by mturney mturney (Code Review) 21 Apr '20

21 Apr '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36517 ) Change subject: sc7180: Add SPI QUP driver ...................................................................... sc7180: Add SPI QUP driver This implements the SPI driver for the QUP core. Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/trogdor/bootblock.c M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h M src/soc/qualcomm/sc7180/qcom_qup_se.c M src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/spi_qup.c 6 files changed, 310 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/36517/1 diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index c658093..a109a08 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -15,8 +15,12 @@ #include <bootblock_common.h> #include "board.h" +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> void bootblock_mainboard_init(void) { setup_chromeos_gpios(); + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* H1 SPI */ + qup_spi_init(QUPV3_1_SE4, 1010 * KHz); /* EC SPI */ } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 18f8ada..66cb35c 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += spi_qup.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c @@ -17,6 +18,7 @@ ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-y += spi_qup.c verstage-y += gpio.c verstage-y += clock.c verstage-y += qcom_qup_se.c @@ -32,6 +34,7 @@ romstage-y += mmu.c romstage-y += usb.c romstage-y += spi.c +romstage-y += spi_qup.c romstage-y += gpio.c romstage-y += clock.c romstage-y += qcom_qup_se.c @@ -43,6 +46,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-y += spi_qup.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += qupv3_fw_config.c diff --git a/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h b/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h new file mode 100644 index 0000000..4999422 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPI_QUP_QCOM_HEADER___ +#define __SPI_QUP_QCOM_HEADER___ + +#include <spi-generic.h> + +int qup_spi_claim_bus(const struct spi_slave *slave); +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in); +void qup_spi_release_bus(const struct spi_slave *slave); +void qup_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif /*__SPI_QUP_QCOM_HEADER___*/ diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index 1774a2c..d14a852 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -92,7 +92,6 @@ if (m_irq) break; } - write32(&regs->geni_m_irq_clear, m_irq); return m_irq; } @@ -147,17 +146,38 @@ void qup_handle_error(unsigned int bus) { struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int m_irq; write32(&regs->geni_tx_watermark_reg, 0); write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL); - if (!wait_us(100, qup_wait_for_irq(bus) & M_CMD_CANCEL_EN)) { + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(bus); + if (m_irq & M_CMD_CANCEL_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_CANCEL_EN)) { printk(BIOS_INFO, "%s:Cancel failed" ",Abort the operation\n", __func__); - write32(&regs->geni_m_cmd_ctrl_reg, - M_GENI_CMD_ABORT); - if (!wait_us(100, qup_wait_for_irq(bus) & M_CMD_ABORT_EN)) + write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(bus); + if (m_irq & M_CMD_ABORT_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_ABORT_EN)) printk(BIOS_INFO, "%s:Abort failed\n", __func__); } } @@ -168,6 +188,7 @@ struct stopwatch sw; unsigned int rx_rem_bytes = din ? size : 0; unsigned int tx_rem_bytes = dout ? size : 0; + struct qup_regs *regs = qup[bus].regs; stopwatch_init_msecs_expire(&sw, 1000); do { @@ -179,8 +200,11 @@ if (m_irq & M_TX_FIFO_WATERMARK_EN) tx_rem_bytes -= handle_tx(bus, dout + size - tx_rem_bytes, tx_rem_bytes); - if (m_irq & M_CMD_DONE_EN) + if (m_irq & M_CMD_DONE_EN) { + write32(&regs->geni_m_irq_clear, m_irq); break; + } + write32(&regs->geni_m_irq_clear, m_irq); } while (!stopwatch_expired(&sw)); if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) { diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index c6d4cb1..4146032 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -16,6 +16,7 @@ #include <spi-generic.h> #include <spi_flash.h> #include <soc/qspi.h> +#include <soc/spi_qup_qcom.h> static const struct spi_ctrlr qspi_ctrlr = { .claim_bus = sc7180_claim_bus, @@ -25,12 +26,24 @@ .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; +const struct spi_ctrlr spi_qup_ctrlr = { + .claim_bus = qup_spi_claim_bus, + .release_bus = qup_spi_release_bus, + .xfer = qup_spi_xfer, + .max_xfer_size = 65535, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, + { + .ctrlr = &spi_qup_ctrlr, + .bus_start = 0, + .bus_end = 11, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/spi_qup.c b/src/soc/qualcomm/sc7180/spi_qup.c new file mode 100644 index 0000000..6953c6a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi_qup.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <delay.h> +#include <lib.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> + +/* SE_SPI_LOOPBACK register fields */ +#define LOOPBACK_ENABLE 0x1 + +/* SE_SPI_WORD_LEN register fields */ +#define WORD_LEN_MSK GENMASK(9, 0) +#define MIN_WORD_LEN 4 + +/* SPI_TX/SPI_RX_TRANS_LEN fields */ +#define TRANS_LEN_MSK GENMASK(23, 0) + +/* M_CMD OP codes for SPI */ +#define SPI_TX_ONLY 1 +#define SPI_RX_ONLY 2 +#define SPI_FULL_DUPLEX 3 +#define SPI_TX_RX 7 +#define SPI_CS_ASSERT 8 +#define SPI_CS_DEASSERT 9 +#define SPI_SCK_ONLY 10 + +/* M_CMD params for SPI */ +/* If fragmentation bit is set then CS will not toggle after each transfer */ +#define M_CMD_FRAGMENTATION BIT(2) + +#define BITS_PER_BYTE 8 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +#define IRQ_TRIGGER (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN | \ + M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN | \ + M_CMD_CANCEL_EN | M_CMD_ABORT_EN) + +static void setup_fifo_params(const struct spi_slave *slave) +{ + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + u32 word_len = 0; + + /* Disable loopback mode */ + write32(&regs->proto_loopback_cfg, 0); + + write32(&regs->spi_demux_sel, slave->cs); + word_len = ((BITS_PER_WORD - MIN_WORD_LEN) & WORD_LEN_MSK); + write32(&regs->word_len.spi_word_len, word_len); + + /* FIFO PACKING CONFIGURATION */ + write32(&regs->geni_tx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_tx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_rx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_rx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_byte_granularity, (log2(BITS_PER_WORD) - 3)); +} + +static void qup_setup_m_cmd(unsigned int se_bus, u32 cmd, u32 params) +{ + struct qup_regs *regs = qup[se_bus].regs; + u32 m_cmd = (cmd << M_OPCODE_SHFT); + + m_cmd |= (params & M_PARAMS_MSK); + write32(&regs->geni_m_cmd0, m_cmd); +} + +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + u32 m_cmd = 0; + u32 m_param = M_CMD_FRAGMENTATION; + int size; + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + + if ((bytes_in == 0) && (bytes_out == 0)) + return 0; + + setup_fifo_params(slave); + + if (!bytes_out) { + size = bytes_in; + m_cmd = SPI_RX_ONLY; + dout = NULL; + } else if (!bytes_in) { + size = bytes_out; + m_cmd = SPI_TX_ONLY; + din = NULL; + } else { + size = MIN(bytes_in, bytes_out); + m_cmd = SPI_FULL_DUPLEX; + } + + /* Check for maximum permissible transfer length */ + assert(!(size & ~TRANS_LEN_MSK)); + + if (bytes_out) { + write32(&regs->tx_trans_len.spi_tx_trans_len, size); + write32(&regs->geni_tx_watermark_reg, TX_WATERMARK); + } + if (bytes_in) + write32(&regs->rx_trans_len.spi_rx_trans_len, size); + + qup_setup_m_cmd(se_bus, m_cmd, m_param); + + if (qup_handle_transfer(se_bus, dout, din, size)) + return -1; + + qup_spi_xfer(slave, dout + size, MAX((int)bytes_out - size, 0), + din + size, MAX((int)bytes_in - size, 0)); + + return 0; +} + +static int spi_qup_set_cs(const struct spi_slave *slave, bool enable) +{ + u32 m_cmd = 0; + u32 m_irq = 0; + unsigned int se_bus = slave->bus; + struct stopwatch sw; + + m_cmd = (enable) ? SPI_CS_ASSERT : SPI_CS_DEASSERT; + qup_setup_m_cmd(se_bus, m_cmd, 0); + + stopwatch_init_usecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(se_bus); + if (m_irq & M_CMD_DONE_EN) { + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + break; + } + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN)) { + printk(BIOS_INFO, "%s:Failed to %s chip\n", __func__, + (enable) ? "Assert" : "Deassert"); + qup_handle_error(se_bus); + return -1; + } + return 0; +} + +void qup_spi_init(unsigned int bus, unsigned int speed_hz) +{ + u32 m_clk_cfg = 0, div = DEFAULT_SE_CLK / speed_hz; + struct qup_regs *regs = qup[bus].regs; + + /* Make sure div can hit target frequency within +/- 1KHz range */ + assert(((DEFAULT_SE_CLK - speed_hz * div) <= div * KHz) && (div > 0)); + clock_enable_qup(bus); + m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); + write32(&regs->geni_ser_m_clk_cfg, m_clk_cfg); + /* Mode:0, cpha=0, cpol=0 */ + write32(&regs->spi_cpha, 0); + write32(&regs->spi_cpol, 0); + /* Disable DFS */ + clrbits_le32(&regs->geni_dfs_if_cfg, + GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + + /* Serial engine IO initialization */ + write32(&regs->geni_cgc_ctrl, DEFAULT_CGC_EN); + write32(&regs->dma_general_cfg, + (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON + | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON)); + write32(&regs->geni_output_ctrl, + DEFAULT_IO_OUTPUT_CTRL_MSK); + write32(&regs->geni_force_default_reg, FORCE_DEFAULT); + + /* Serial engine IO set mode */ + write32(&regs->se_irq_en, (GENI_M_IRQ_EN | + GENI_S_IRQ_EN | DMA_TX_IRQ_EN | DMA_RX_IRQ_EN)); + write32(&regs->se_gsi_event_en, 0); + + /* Set RX and RFR watermark */ + write32(&regs->geni_rx_watermark_reg, 0); + write32(&regs->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* GPIO Configuration */ + gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_NO_PULL, + GPIO_6MA, GPIO_INPUT); /* MISO */ + gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* MOSI */ + gpio_configure(qup[bus].pin[2], qup[bus].func[2], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CLK */ + gpio_configure(qup[bus].pin[3], qup[bus].func[3], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CS */ + + /* Select and setup FIFO mode */ + write32(&regs->geni_m_irq_clear, 0xFFFFFFFF); + write32(&regs->geni_s_irq_clear, 0xFFFFFFFF); + write32(&regs->dma_tx_irq_clr, 0xFFFFFFFF); + write32(&regs->dma_rx_irq_clr, 0xFFFFFFFF); + write32(&regs->geni_m_irq_enable, (M_COMMON_GENI_M_IRQ_EN | + M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)); + write32(&regs->geni_s_irq_enable, (S_COMMON_GENI_S_IRQ_EN + | S_CMD_DONE_EN)); + clrbits_le32(&regs->geni_dma_mode_en, GENI_DMA_MODE_EN); +} + +int qup_spi_claim_bus(const struct spi_slave *slave) +{ + return spi_qup_set_cs(slave, 1); +} + +void qup_spi_release_bus(const struct spi_slave *slave) +{ + spi_qup_set_cs(slave, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Gerrit-Change-Number: 36517 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 20

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFO...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33919 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33919/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index cba0894..98bc620 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -115,7 +115,7 @@ #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -- To view, visit https://review.coreboot.org/c/coreboot/+/33919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd Gerrit-Change-Number: 33919 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

7 13

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by C...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33916 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by CONFIG_GFXUMA ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by CONFIG_GFXUMA Seems this guard has been accidentally removed during the creation of this file. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33916/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 2a1f13d..dfd27cd 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -176,9 +176,11 @@ #define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 #define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO #define OPTION_GFX_INIT_SVIEW FALSE +#endif #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -- To view, visit https://review.coreboot.org/c/coreboot/+/33916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68 Gerrit-Change-Number: 33916 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33915 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments These comments exist in some other buildOpts.c files, but not in this one. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/33915/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 8ba5975..2a1f13d 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -43,8 +43,10 @@ #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h> #include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h> +/* Select the CPU family. */ #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -165,6 +167,8 @@ #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied #define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 #define BLDCFG_VRM_SLEW_RATE 10000 @@ -344,4 +348,5 @@ #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) +/* AGESA nonsense: this header depends on the definitions above */ #include <PlatformInstall.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5 Gerrit-Change-Number: 33915 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019