coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: mainboard/google: Split Hatch mainboard_memory_init_params() on spd path
by Edward O'Callaghan (Code Review) 19 Jun '20

19 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36495 ) Change subject: mainboard/google: Split Hatch mainboard_memory_init_params() on spd path ...................................................................... mainboard/google: Split Hatch mainboard_memory_init_params() on spd path The follow bifurcates mainboard_memory_init_params() in Hatch's romstage depending on if the SPD data path is either derived from CBFS or over SMBus. This restructure allows for variant boards that need to configure the SMBus path to do it via their own custom variant_memory_params() that implements the SMBus path. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I430853270bdc2a3d8916d23fb6f085a28890518a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/romstage.c 2 files changed, 28 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/36495/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..fbc41df 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -58,6 +58,10 @@ int default 512 +config ROMSTAGE_SPD_SMBUS + bool + default n + config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 07864e6..b264d66d 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -32,26 +32,33 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; - int is_single_ch_mem; variant_memory_params(&memcfg); - /* - * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single - * channel skus and 0 for dual channel skus. - */ - is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); - /* - * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. - * Dual-DIMM memory is not used in hatch family, so we only - * fill in spd_info for CH0D0 and CH1D0 here. - */ - int mem_sku = variant_memory_sku(); - memcfg.spd[0].read_type = READ_SPD_CBFS; - memcfg.spd[0].spd_spec.spd_index = mem_sku; - if (!is_single_ch_mem) { - memcfg.spd[2].read_type = READ_SPD_CBFS; - memcfg.spd[2].spd_spec.spd_index = mem_sku; + if (CONFIG(ROMSTAGE_SPD_SMBUS)) { + const FSPM_ARCH_UPD *arch_upd = &memupd->FspmArchUpd; + /* SPD was saved in S0/S5 path, skips it when resumes from S3 */ + if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME) + return; + } else { + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + int is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. + * Dual-DIMM memory is not used in hatch family, so we only + * fill in spd_info for CH0D0 and CH1D0 here. + */ + int mem_sku = variant_memory_sku(); + memcfg.spd[0].read_type = READ_SPD_CBFS; + memcfg.spd[0].spd_spec.spd_index = mem_sku; + if (!is_single_ch_mem) { + memcfg.spd[2].read_type = READ_SPD_CBFS; + memcfg.spd[2].spd_spec.spd_index = mem_sku; + } } cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/36495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I430853270bdc2a3d8916d23fb6f085a28890518a Gerrit-Change-Number: 36495 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mainboard/google: Move memory_variant_sku() call site
by Edward O'Callaghan (Code Review) 19 Jun '20

19 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36494 ) Change subject: mainboard/google: Move memory_variant_sku() call site ...................................................................... mainboard/google: Move memory_variant_sku() call site Move the call site down to be local to where it is needed. This makes it easier to split the function into two variants, one for handling the SPD data sourced from CBFS or from SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4b04fe392539e799f491ffc77d8a79a42724f052 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36494/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 50d9066..07864e6 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -32,11 +32,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; - int mem_sku; int is_single_ch_mem; variant_memory_params(&memcfg); - mem_sku = variant_memory_sku(); /* * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single * channel skus and 0 for dual channel skus. @@ -48,6 +46,7 @@ * Dual-DIMM memory is not used in hatch family, so we only * fill in spd_info for CH0D0 and CH1D0 here. */ + int mem_sku = variant_memory_sku(); memcfg.spd[0].read_type = READ_SPD_CBFS; memcfg.spd[0].spd_spec.spd_index = mem_sku; if (!is_single_ch_mem) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b04fe392539e799f491ffc77d8a79a42724f052 Gerrit-Change-Number: 36494 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mainboard/google: Move variant_memory_sku() to baseboard/
by Edward O'Callaghan (Code Review) 19 Jun '20

19 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36492 ) Change subject: mainboard/google: Move variant_memory_sku() to baseboard/ ...................................................................... mainboard/google: Move variant_memory_sku() to baseboard/ The variant_memory_sku() symbol within romstage.c unreasonably depends on pre-processor #define's in variants that may not define them. Provide a default symbol and configuration within the basebase in the form of a weak symbol and allow the two variants that differ to override using a strong symbol. In the case of variants that do not need this symbol they can override with a strong symbol that is a nop. Change-Id: I41532e3067a989db5776887fac0459a000d07ff0 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h M src/mainboard/google/hatch/variants/baseboard/memory.c M src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h A src/mainboard/google/hatch/variants/hatch/memory.c M src/mainboard/google/hatch/variants/helios/include/variant/gpio.h M src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h M src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h M src/mainboard/google/hatch/variants/kohaku/memory.c 11 files changed, 76 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36492/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index a94fab5..50d9066 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -29,18 +29,6 @@ */ #define GPIO_MEM_CH_SEL GPP_F2 -int __weak variant_memory_sku(void) -{ - const gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h index b257589..5d69eed 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index bcfc49f..ada20a8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -15,9 +15,28 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> +/* Default memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +int __weak variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + static const struct cnl_mb_cfg baseboard_memcfg = { /* Baseboard uses 121, 81 and 100 rcomp resistors */ .rcomp_resistor = {121, 81, 100}, diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h index 92f9d41..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5a..47ca158 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 +romstage-y += memory.c + ramstage-y += gpio.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h index e7d8a75..5d69eed 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 - #endif diff --git a/src/mainboard/google/hatch/variants/hatch/memory.c b/src/mainboard/google/hatch/variants/hatch/memory.c new file mode 100644 index 0000000..2712b24 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/memory.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h index 92f9d41..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h index 92f9d41..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h index 29e5904..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 - #endif diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c index 4901247..de33ead 100644 --- a/src/mainboard/google/hatch/variants/kohaku/memory.c +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -15,9 +15,28 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + static const struct cnl_mb_cfg baseboard_memcfg = { /* * The dqs_map arrays map the SoC pins to the lpddr3 pins -- To view, visit https://review.coreboot.org/c/coreboot/+/36492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41532e3067a989db5776887fac0459a000d07ff0 Gerrit-Change-Number: 36492 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: _WIP_ soc/amd/picasso: Update all remaining pci_devs
by Marshall Dawson (Code Review) 10 Jun '20

10 Jun '20

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34429 to review the following change. Change subject: _WIP_ soc/amd/picasso: Update all remaining pci_devs ...................................................................... _WIP_ soc/amd/picasso: Update all remaining pci_devs Unlike older products, many of the Family 17h PCI devices are not on bus 0, and therefore cannot be located using pcidev_on_root(). The PPR (PID #55570, NDA required) shows Bus A and Bus B devices, where 0:8.1 and 0:8.2 are the bridges to them. Also, unlike older products, the bridges are not hidden for the purpose of making devices appear to be on bus 0. Rework pci_devs.h and other files to account for the new topology. Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/pci_devs.h 1 file changed, 32 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34429/1 diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 28fa99f..de5e446 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -84,7 +84,6 @@ #define PCIE8_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) #define SOC_PCIE8_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) - /* Data Fabric functions */ #define DF_DEV 0x18 @@ -116,29 +115,6 @@ #define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) #define SOC_DF_F6_DEVFN _SOC_DEV(DF_DEV, 6) -/* USB 3.1 */ -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVID 0x15e0 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) -#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) - -/* USB 3.1 */ -#define XHCI1_DEV 0x0 -#define XHCI1_FUNC 4 -#define XHCI1_DEVID 0x15e1 -#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) -#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) -#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 @@ -153,25 +129,48 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) +/* + * Bus A devices + */ + /* Internal Graphics */ -#define GFX_DEV 0x1 +#define GFX_DEV 0x0 #define GFX_FUNC 0 #define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) /* HD Audio 0 */ -#define HDA0_DEV 0x1 +#define HDA0_DEV 0x0 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 +#define HDA0_DEVID 0x15de #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) -/* HD Audio 1 */ -#define HDA1_DEV 0x9 -#define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a -#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) -#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) + +/* + * Bus B devices + */ + +/* SATA */ +#define SATA_DEV 0x0 +#define SATA_FUNC 0 +#define AHCI_DEVID_MS 0x7901 +#define AHCI_DEVID_AMD 0x7904 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) #endif /* __PI_PICASSO_PCI_DEVS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Gerrit-Change-Number: 34429 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [WIP] mb/intel/cannonlake_rvp,coffeelake_rvp: Add LPC_TPM
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35103 ) Change subject: [WIP] mb/intel/cannonlake_rvp,coffeelake_rvp: Add LPC_TPM ...................................................................... [WIP] mb/intel/cannonlake_rvp,coffeelake_rvp: Add LPC_TPM Board devicetrees requests for drivers7pc80/tpm but that was not included for the build. Change-Id: Ia959ae9072e3fc709b779b1fc778eb82e10c2ee3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35103/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index d86e485..6d686c3 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -13,6 +13,7 @@ select SOC_INTEL_CANNONLAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 13e55b3..8bd2881 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -16,6 +16,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/35103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia959ae9072e3fc709b779b1fc778eb82e10c2ee3 Gerrit-Change-Number: 35103 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT
by Patrick Rudolph (Code Review) 28 May '20

28 May '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34453 ) Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ...................................................................... sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT Both fields are ignored if WBINVD is set, which is true for all processors since i486. Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34453/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8794602..e656a37 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -766,8 +766,9 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; fadt->duty_offset = 1; if (chip->p_cnt_throttling_supported) { fadt->duty_width = 3; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa1ca92..c829707 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -678,8 +678,9 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; fadt->duty_offset = 1; if (chip->p_cnt_throttling_supported) { fadt->duty_width = 3; -- To view, visit https://review.coreboot.org/c/coreboot/+/34453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Gerrit-Change-Number: 34453 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: vboot: Turn vboot_logic_executed() into a static inline
by Julius Werner (Code Review) 27 May '20

27 May '20

Hello Aaron Durbin, Frans Hendriks, Philipp Deppenwiese, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32716 to review the following change. Change subject: vboot: Turn vboot_logic_executed() into a static inline ...................................................................... vboot: Turn vboot_logic_executed() into a static inline This patch moves vboot_logic_executed() (and its dependencies) into a header and turns it into a static inline function. The function is used to guard larger amounts of code in several places, so this should allow us to safe some more space through compile-time elimination (and also makes it easier to avoid undefined reference issues in some cases). Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/misc.h M src/security/vboot/vboot_loader.c 2 files changed, 58 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32716/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index b4fae19..2a0523d 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -16,6 +16,8 @@ #ifndef __VBOOT_MISC_H__ #define __VBOOT_MISC_H__ +#include <assert.h> +#include <arch/early_variables.h> #include <security/vboot/vboot_common.h> struct vb2_context; @@ -66,13 +68,63 @@ void vboot_fill_handoff(void); /* - * Source: security/vboot/vboot_loader.c - */ -int vboot_logic_executed(void); - -/* * Source: security/vboot/bootmode.c */ void vboot_save_recovery_reason_vbnv(void); +/* + * The stage loading code is compiled and entered from multiple stages. The + * helper functions below attempt to provide more clarity on when certain + * code should be called. They are implemented inline for better compile-time + * code elimination. + */ + +static inline int verification_should_run(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_VERSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return ENV_ROMSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + return ENV_BOOTBLOCK; + else + dead_code(); +} + +static inline int verstage_should_load(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_BOOTBLOCK; + else + return 0; +} + +/* Only for use by functions in this header, do not access directly! */ +extern int vboot_executed; + +static inline int vboot_logic_executed(void) +{ + /* If we are in the stage that runs verification, or in the stage that + both loads the verstage and is returned to from it afterwards, we + need to check a global to see if verfication has run. */ + if (verification_should_run() || + (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) + return car_get_var(vboot_executed); + + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { + /* All other stages are "after the bootblock" */ + return !ENV_BOOTBLOCK; + } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + /* Post-RAM stages are "after the romstage" */ +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } else { + dead_code(); + } +} + + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 3bbb3da..1350307 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -36,55 +36,7 @@ CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); -/* The stage loading code is compiled and entered from multiple stages. The - * helper functions below attempt to provide more clarity on when certain - * code should be called. */ - -static int verification_should_run(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_VERSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) - return ENV_ROMSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - return ENV_BOOTBLOCK; - else - die("impossible!"); -} - -static int verstage_should_load(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_BOOTBLOCK; - else - return 0; -} - -static int vboot_executed CAR_GLOBAL; - -int vboot_logic_executed(void) -{ - /* If we are in the stage that runs verification, or in the stage that - both loads the verstage and is returned to from it afterwards, we - need to check a global to see if verfication has run. */ - if (verification_should_run() || - (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) - return car_get_var(vboot_executed); - - if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { - /* All other stages are "after the bootblock" */ - return !ENV_BOOTBLOCK; - } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif - } else { - die("impossible!"); - } -} +int vboot_executed CAR_GLOBAL; static void vboot_prepare(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Gerrit-Change-Number: 32716 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: mb/toshiba: Add A300-1ME
by Angel Pons (Code Review) 25 May '20

25 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34786 ) Change subject: mb/toshiba: Add A300-1ME ...................................................................... mb/toshiba: Add A300-1ME Mainboard real name (to find schematics) is Inventec Potomac 10G. Vendor firmware is InsydeH20 EFI Rev. 3.5 and shows postcodes on LPC. This thing is a PM45/ICH9M notebook with a WPCE775 EC. It usually boots from LPC via EC, but also has space for another flash chip, directly attached to SPI. Working: - usbdebug with FT2232H (left side, the non-eSATA USB port) - postcodes via LPC (debug card on WLAN card slot) with vendor firmware coreboot may not be printing any postcodes on this platform, so this may explain why postcodes don't show with coreboot. But the hw works. - running coreboot off the ICH SPI flash chip - fan runs at a high speed by default (no risk of overheating) Not working: - raminit: dies with: "DDR2 not supported at this time." - some watchdog trips after a few seconds (likely EC watchdog) (though coreboot currently dies first) Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/toshiba/Kconfig A src/mainboard/toshiba/Kconfig.name A src/mainboard/toshiba/a300-1me/Kconfig A src/mainboard/toshiba/a300-1me/Kconfig.name A src/mainboard/toshiba/a300-1me/Makefile.inc A src/mainboard/toshiba/a300-1me/acpi/battery.asl A src/mainboard/toshiba/a300-1me/acpi/ec.asl A src/mainboard/toshiba/a300-1me/acpi/ec2.asl A src/mainboard/toshiba/a300-1me/acpi/gpe.asl A src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl A src/mainboard/toshiba/a300-1me/acpi/mainboard.asl A src/mainboard/toshiba/a300-1me/acpi/platform.asl A src/mainboard/toshiba/a300-1me/acpi/superio.asl A src/mainboard/toshiba/a300-1me/acpi/thermal.asl A src/mainboard/toshiba/a300-1me/acpi_tables.c A src/mainboard/toshiba/a300-1me/blc.c A src/mainboard/toshiba/a300-1me/board_info.txt A src/mainboard/toshiba/a300-1me/cmos.layout A src/mainboard/toshiba/a300-1me/cstates.c A src/mainboard/toshiba/a300-1me/devicetree.cb A src/mainboard/toshiba/a300-1me/dsdt.asl A src/mainboard/toshiba/a300-1me/fadt.c A src/mainboard/toshiba/a300-1me/gpio.c A src/mainboard/toshiba/a300-1me/hda_verb.c A src/mainboard/toshiba/a300-1me/mainboard.c A src/mainboard/toshiba/a300-1me/romstage.c A src/mainboard/toshiba/a300-1me/smistuff.c 27 files changed, 1,899 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34786/1 diff --git a/src/mainboard/toshiba/Kconfig b/src/mainboard/toshiba/Kconfig new file mode 100644 index 0000000..609b15d --- /dev/null +++ b/src/mainboard/toshiba/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_TOSHIBA + +choice + prompt "Mainboard model" + +source "src/mainboard/toshiba/*/Kconfig.name" + +endchoice + +source "src/mainboard/toshiba/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "TOSHIBA" + +endif # VENDOR_TOSHIBA diff --git a/src/mainboard/toshiba/Kconfig.name b/src/mainboard/toshiba/Kconfig.name new file mode 100644 index 0000000..47dbb59 --- /dev/null +++ b/src/mainboard/toshiba/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_TOSHIBA + bool "TOSHIBA" diff --git a/src/mainboard/toshiba/a300-1me/Kconfig b/src/mainboard/toshiba/a300-1me/Kconfig new file mode 100644 index 0000000..8099b7b --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/Kconfig @@ -0,0 +1,33 @@ +if BOARD_TOSHIBA_A300_1ME + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_BGA956 + select NORTHBRIDGE_INTEL_GM45 + select SOUTHBRIDGE_INTEL_I82801IX + select BOARD_ROMSIZE_KB_2048 # FIXME: that's the size of my flash chip + #select DRIVERS_GENERIC_IOAPIC + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select EC_ACPI + select HAVE_OPTION_TABLE + select INTEL_INT15 + +config MAINBOARD_DIR + string + default toshiba/a300-1me + +config MAINBOARD_PART_NUMBER + string + default "A300-1ME" + +config MAX_CPUS + int + default 2 + +config CBFS_SIZE + hex + default ROM_SIZE + +endif # BOARD_TOSHIBA_A300_1ME diff --git a/src/mainboard/toshiba/a300-1me/Kconfig.name b/src/mainboard/toshiba/a300-1me/Kconfig.name new file mode 100644 index 0000000..8bc568d --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_TOSHIBA_A300_1ME + bool "A300-1ME" diff --git a/src/mainboard/toshiba/a300-1me/Makefile.inc b/src/mainboard/toshiba/a300-1me/Makefile.inc new file mode 100644 index 0000000..21bbe39 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y = gpio.c + +ramstage-y += cstates.c +ramstage-y += blc.c diff --git a/src/mainboard/toshiba/a300-1me/acpi/battery.asl b/src/mainboard/toshiba/a300-1me/acpi/battery.asl new file mode 100644 index 0000000..2f793d8 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/battery.asl @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(\CBA1, 0x60) +Name(\CBA2, 0x60) + +/* ACPI doesn't care if capacity is given in mWh or mAh, + but it has to be consistent */ + +Device (BAT1) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 1) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "001 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + If(\_SB.PCI0.LPCB.EC0.B1PR) { + If(\_SB.PCI0.LPCB.EC0.B1CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1)) + Store (\_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2)) + Store (\_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B1PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (\_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3)) + + Store (\_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2)) + + If (\_SB.PCI0.LPCB.EC0.ACCH) { + If (\_SB.PCI0.LPCB.EC0.B1CH) { + If (\_SB.PCI0.LPCB.EC0.B1CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (\_SB.PCI0.LPCB.EC0.B1LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (BAT2) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 2) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "002 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + If(\_SB.PCI0.LPCB.EC0.B2PR) { + If(\_SB.PCI0.LPCB.EC0.B2CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1)) + Store (\_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2)) + Store (\_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B2PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (\_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3)) + + Store (\_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2)) + + If (\_SB.PCI0.LPCB.EC0.ACCH) { + If (\_SB.PCI0.LPCB.EC0.B2CH) { + If (\_SB.PCI0.LPCB.EC0.B2CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (\_SB.PCI0.LPCB.EC0.B2LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Method (_PSR, 0) + { + Store (\_SB.PCI0.LPCB.EC0.ACCH, PWRS) + Stall (0x02) + Return (PWRS) + } + + Method (_PCL, 0) + { + Return (_SB) + } +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/ec.asl b/src/mainboard/toshiba/a300-1me/acpi/ec.asl new file mode 100644 index 0000000..48630b0 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/ec.asl @@ -0,0 +1 @@ +// dummy diff --git a/src/mainboard/toshiba/a300-1me/acpi/ec2.asl b/src/mainboard/toshiba/a300-1me/acpi/ec2.asl new file mode 100644 index 0000000..aef4d32 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/ec2.asl @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + Name (ECON, 0) + Name (QEVT, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xb1), + CPWR, 1, + ACCH, 1, // AC connected (charger present) + B1PR, 1, // battery 1 present + B2PR, 1, // battery 2 present + B1CH, 1, // battery 1 charged + B2CH, 1, // battery 2 charged + Offset(0xb2), + B1CG, 1, // battery 1 charging + B2CG, 1, // battery 2 charging + B1LO, 1, // battery 1 low + B2LO, 1, // battery 2 low + Offset(0xb3), + B1DW, 16, // battery 1 design capacity + B1FW, 16, // battery 1 last full charge capacity + B1DV, 16, // battery 1 design voltage + B1PW, 16, // battery 1 present capacity + Offset(0xbd), + B1PV, 16, // battery 1 present voltage + Offset(0xc1), + B2DW, 16, // battery 2 design capacity + B2FW, 16, // battery 2 last full charge capacity + B2DV, 16, // battery 2 design voltage + B2PW, 16, // battery 2 present capacity + Offset(0xcb), + B2PV, 16, // battery 2 present voltage + Offset(0xcf), + FDDI, 1, // floppy on lpt indicator? + LIDC, 1, // LID switch + Offset(0xd0), + TCPU, 8, // T_CPU in deg Celcius + Offset(0xd6), + /* exact purpose of these three is guessed, + but it's something about cooling */ + ALRL, 1, // active cooling low limit + ALRH, 1, // active cooling high limit + ALRC, 1, // active cooling clear + Offset(0xe8), + B1RW, 16, // battery 1 remaining capacity + B2RW, 16, // battery 2 remaining capacity + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 for + // EC initialization before a driver is loaded + + If (LEqual(Arg0, 0x03)) { + Store (Arg1, ECON) + } + } + + // EC Query methods + + Method (_Q11, 0) + { + Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Notify(SLPB, 0x80) + } + + Method (_Q30, 0) + { + Store("_Q30: AC In", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q31, 0) + { + Store("_Q31: AC Out", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q32, 0) + { + Store("_Q32: Bat1 In", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q33, 0) + { + Store("_Q33: Bat1 Out", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q34, 0) + { + Store("_Q34: Bat2 In", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q35, 0) + { + Store("_Q35: Bat2 Out", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q36, 0) + { + Store("_Q36: Bat1 Low Power", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q37, 0) + { + Store("_Q37: Bat1 Full Charge", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q38, 0) + { + Store("_Q38: Bat2 Low Power", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q39, 0) + { + Store("_Q39: Bat2 Full Charge", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q40, 0) + { + Store("_Q40: LID Open/Close", Debug) + Notify(LID0, 0x80) + } + + Method (_Q41, 0) + { + Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug) + } + + Method (_Q50, 0) + { + Store("_Q50: Processor is hot", Debug) + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q51, 0) + { + Store("_Q51: Processor is boiling", Debug) + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q52, 0) + { + Store("_Q52: Processor is burning", Debug) + Notify(\_TZ.THRM, 0x80) + } + +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/gpe.asl b/src/mainboard/toshiba/a300-1me/acpi/gpe.asl new file mode 100644 index 0000000..5ba3538 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/gpe.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_GPE) +{ + /* The event numbers correspond to the bit numbers in the + * GPE0_EN register PMBASE + 0x28. + */ + /* IMO we don't need empty Methods here. If we don't specify + one and don't set the GPE0_EN bit Linux won't neither enable + it. - Nico */ + + // Thermal Event - original BIOS doesn't have it + Method (_L00, 0) + { + /* FIXME: We should enable throttling here. */ + } + + // Hot Plug + Method (_L01, 0) + { + + } + + // USB1 + Method (_L03, 0) + { + + } + + // USB2 + Method (_L04, 0) + { + + } + + // USB5 + Method (_L05, 0) + { + + } + + // _L06 TCOSCI + + // SMBus Wake Status + Method (_L07, 0) + { + + } + + // COM1/COM2 (RI) + Method (_L08, 0) + { + + } + + // PCIe + Method (_L09, 0) + { + + } + + // _L0A BatLow / Quick Resume + + // PME + Method (_L0B, 0) + { + + } + + // USB3 + Method (_L0C, 0) + { + + } + + // PME B0 + Method (_L0D, 0) + { + + } + + // USB4 + Method (_L0E, 0) + { + + } + + // _L10 - _L1f: GPIn + + // GPI8 + Method (_L18, 0) + { + + } + + // USB6 + Method (_L20, 0) + { + + } +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl b/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl new file mode 100644 index 0000000..b206c2b --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH9 + */ + +/* TODO: which slots are actually relevant? */ +If (PICM) { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, 0, 16}, + Package() { 0x0000ffff, 1, 0, 17}, + Package() { 0x0000ffff, 2, 0, 18}, + Package() { 0x0000ffff, 3, 0, 19}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, 0, 17}, + Package() { 0x0001ffff, 1, 0, 18}, + Package() { 0x0001ffff, 2, 0, 19}, + Package() { 0x0001ffff, 3, 0, 16}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 16}, + Package() { 0x0002ffff, 3, 0, 17}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, 0, 16}, + Package() { 0x0003ffff, 1, 0, 17}, + Package() { 0x0003ffff, 2, 0, 18}, + Package() { 0x0003ffff, 3, 0, 19}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, 0, 16}, + Package() { 0x0004ffff, 1, 0, 17}, + Package() { 0x0004ffff, 2, 0, 18}, + Package() { 0x0004ffff, 3, 0, 19}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 19}, + Package() { 0x0005ffff, 3, 0, 16}, + + // FIXME: what's this supposed to mean? (adopted from ich7) + //Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + // FIXME + // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl b/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl new file mode 100644 index 0000000..2f0c927 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDC) + } +} + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x18, 0x04}) +} + +//#include "acpi/battery.asl" diff --git a/src/mainboard/toshiba/a300-1me/acpi/platform.asl b/src/mainboard/toshiba/a300-1me/acpi/platform.asl new file mode 100644 index 0000000..f9adffa --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/platform.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + + Return(Package(){0,0}) +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/superio.asl b/src/mainboard/toshiba/a300-1me/acpi/superio.asl new file mode 100644 index 0000000..48630b0 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/superio.asl @@ -0,0 +1 @@ +// dummy diff --git a/src/mainboard/toshiba/a300-1me/acpi/thermal.asl b/src/mainboard/toshiba/a300-1me/acpi/thermal.asl new file mode 100644 index 0000000..d7f8364 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/thermal.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + Method(C2dK, 1) { + Add (2732, Multiply (Arg0, 10), Local0) + Return (Local0) + } + + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x96) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (C2dK(120)) // Value for Rocky + } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (C2dK(155)) // Value for Rocky + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (C2dK(105)) // Value for Rocky + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + If (\_SB.PCI0.LPCB.EC0.ALRC) { + Store(0, \_SB.PCI0.LPCB.EC0.ALRC) + Return(_AC0()) + } + + If (\_SB.PCI0.LPCB.EC0.ALRL) { + Store(0, THRO) + Store(0, \_SB.PCI0.LPCB.EC0.ALRL) + } + + If (\_SB.PCI0.LPCB.EC0.ALRH) { + Store(1, THRO) + Store(0, \_SB.PCI0.LPCB.EC0.ALRH) + } + + /* vendor BIOS reports 0K if TCPU >= 128 deg C ?!? */ + Return (C2dK(\_SB.PCI0.LPCB.EC0.TCPU)) + } + + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CP00, \_PR.CP01}) + } + Return (Package() {\_PR.CP00}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} diff --git a/src/mainboard/toshiba/a300-1me/acpi_tables.c b/src/mainboard/toshiba/a300-1me/acpi_tables.c new file mode 100644 index 0000000..0716d2d --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/i82801ix/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + //gnvs->cmap = 0x01; + //gnvs->cmbp = 0x01; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} diff --git a/src/mainboard/toshiba/a300-1me/blc.c b/src/mainboard/toshiba/a300-1me/blc.c new file mode 100644 index 0000000..4b6104e --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/blc.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 arthur(a)aheymans.xyz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <northbridge/intel/gm45/gm45.h> + +int get_blc_values(const struct blc_pwm_t **entries) +{ + return 0; +} diff --git a/src/mainboard/toshiba/a300-1me/board_info.txt b/src/mainboard/toshiba/a300-1me/board_info.txt new file mode 100644 index 0000000..4ce92d3 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/board_info.txt @@ -0,0 +1 @@ +Category: laptop diff --git a/src/mainboard/toshiba/a300-1me/cmos.layout b/src/mainboard/toshiba/a300-1me/cmos.layout new file mode 100644 index 0000000..d794306 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/cmos.layout @@ -0,0 +1,119 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# 2012 secunet Security Networks AG +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 8 r 0 unused + +# coreboot config options: southbridge +408 1 e 9 sata_mode +#409 7 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +#937 7 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# coreboot config options: northbridge +1000 4 e 10 gfx_uma_size + +#1004 20 r 0 unused + +# RAM initialization internal data +1024 128 r 0 read_training_results + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 AHCI +9 1 Compatible +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/toshiba/a300-1me/cstates.c b/src/mainboard/toshiba/a300-1me/cstates.c new file mode 100644 index 0000000..fea9276 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/cstates.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> + +static acpi_cstate_t cst_entries[] = { + { + /* ACPI C1 / CPU C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0, 0 } + }, + { + /* ACPI C2 / CPU C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/toshiba/a300-1me/devicetree.cb b/src/mainboard/toshiba/a300-1me/devicetree.cb new file mode 100644 index 0000000..5936104 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/devicetree.cb @@ -0,0 +1,142 @@ +chip northbridge/intel/gm45 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + device cpu_cluster 0 on + chip cpu/intel/socket_BGA956 + device lapic 0 on end + end + chip cpu/intel/model_1067x + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Enable Super LFM + register "slfm" = "1" + + # Enable C5, C6 + register "c5" = "1" + register "c6" = "1" + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + subsystemid 0x1179 0xff1e inherit + device pci 00.0 on end # host bridge + device pci 01.0 on end # PEG + device pci 02.0 off # VGA + # ioapic_irq 2 INTA 0x10 + end + device pci 02.1 off end # Display + device pci 03.0 off end # ME + device pci 03.1 off end # ME + device pci 03.2 off end # ME + device pci 03.3 off end # ME + chip southbridge/intel/i82801ix + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + register "gpi8_routing" = "2" + register "gpi7_routing" = "2" + register "gpe0_en" = "0x01800042" + register "gpi1_routing" = "1" + register "alt_gp_smi_en" = "0x0002" + + # Set AHCI mode, enable ports 1 and 2. + register "sata_port_map" = "0x03" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Set c-state support + register "c4onc3_enable" = "0" + register "c5_enable" = "1" + register "c6_enable" = "1" + + # Set thermal throttling to 75%. + register "throttle_duty" = "THTL_75_0" + + # Enable PCIe ports 1 and 5 as slots (Mini * PCIe). + # register "pcie_slot_implemented" = "0x11" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + # register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" + + device pci 19.0 off end # LAN + device pci 1a.0 on # UHCI + #ioapic_irq 2 INTA 0x10 + end + device pci 1a.1 on # UHCI + #ioapic_irq 2 INTB 0x11 + end + device pci 1a.2 on # UHCI + #ioapic_irq 2 INTC 0x12 + end + device pci 1a.7 on # EHCI + #ioapic_irq 2 INTC 0x12 + end + device pci 1b.0 on # HD Audio + #ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on # PCIe Port #1 + #ioapic_irq 2 INTA 0x10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + #ioapic_irq 2 INTA 0x10 + #device pci 00.0 on end # Realtek 8168B + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on # UHCI + #ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # UHCI + #ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # UHCI + #ioapic_irq 2 INTC 0x12 + end + device pci 1d.7 on # EHCI + #ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on # PCI + #device pci 03.0 on # TI Cardbus + #ioapic_irq 2 INTA 0x10 + #end + #device pci 03.1 on # TI Cardbus + #ioapic_irq 2 INTB 0x11 + #end + #device pci 03.2 off end # TI FireWire OHC + #device pci 03.3 off end # unconnected FlashMedia + #device pci 03.4 off end # unconnected SD-Card + end + device pci 1f.0 on # LPC bridge + #chip drivers/generic/ioapic + #register "have_isa_interrupts" = "1" + #register "irq_on_fsb" = "1" + #register "enable_virtual_wire" = "1" + #register "base" = "(void *)0xfec00000" + #device ioapic 2 on end + #end + + # FIXME: WPCE775 support + end + device pci 1f.2 on # SATA/IDE 1 + #ioapic_irq 2 INTB 0x11 + end + device pci 1f.3 on # SMBus + #ioapic_irq 2 INTC 0x12 + end + device pci 1f.5 off end # SATA/IDE 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/toshiba/a300-1me/dsdt.asl b/src/mainboard/toshiba/a300-1me/dsdt.asl new file mode 100644 index 0000000..cf2479a --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801ix/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + //#include "acpi/mainboard.asl" + + #include <cpu/intel/speedstep/acpi/cpu.asl> + + // Thermal Zone + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/gm45/acpi/gm45.asl> + #include <southbridge/intel/i82801ix/acpi/ich9.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> +} diff --git a/src/mainboard/toshiba/a300-1me/fadt.c b/src/mainboard/toshiba/a300-1me/fadt.c new file mode 100644 index 0000000..f2b8559 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/fadt.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <version.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->reserved = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/toshiba/a300-1me/gpio.c b/src/mainboard/toshiba/a300-1me/gpio.c new file mode 100644 index 0000000..92454cb --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/gpio.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_NATIVE, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/toshiba/a300-1me/hda_verb.c b/src/mainboard/toshiba/a300-1me/hda_verb.c new file mode 100644 index 0000000..63f37b5 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/hda_verb.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */ + 0x43528986, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x11), S/PDIF-OUT2: not connected */ + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + /* Pin Complex (NID 0x14), LINE_OUT (port D): Speakers */ + AZALIA_PIN_CFG(0, 0x14, 0x99130110), + /* Pin Complex (NID 0x15), HP_OUT (port A): Head phones */ + AZALIA_PIN_CFG(0, 0x15, 0x0121411f), + /* Pin Complex (NID 0x16), MONO-OUT: not connected */ + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + /* Pin Complex (NID 0x18), MIC1 (port B): Microphone */ + AZALIA_PIN_CFG(0, 0x18, 0x01a19920), + /* Pin Complex (NID 0x19), MIC2 (port F): not connected */ + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + /* Pin Complex (NID 0x1a), LINE1 (port C): Line-In */ + AZALIA_PIN_CFG(0, 0x1a, 0x01813121), + /* Pin Complex (NID 0x1b), LINE2 (port E): MDC */ + AZALIA_PIN_CFG(0, 0x1b, 0x9983012f), + /* Pin Complex (NID 0x1c), CD_IN */ + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + /* Pin Complex (NID 0x1d), PCBEEP */ + AZALIA_PIN_CFG(0, 0x1d, 0x4014022d), + /* Pin Complex (NID 0x1e), S/PDIF-OUT: not connected */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Pin Complex (NID 0x1f), S/PDIF-IN: not connected */ + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) +}; + +const u32 pc_beep_verbs[] = { + //0x00170500, /* power up codec */ + //0x01470500, /* power up speakers */ + //0x01470100, /* select lout1 (input 0x0) for speakers */ + //0x01470740, /* enable speakers output */ + //0x00b37517, /* unmute beep (mixer's input 0x5), set amp 0dB */ + //0x00c37100, /* unmute mixer in lout1 (lout1 input 0x1) */ + //0x00c3b015, /* set lout1 output volume -15dB */ + //0x0143b000, /* unmute speakers */ +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/toshiba/a300-1me/mainboard.c b/src/mainboard/toshiba/a300-1me/mainboard.c new file mode 100644 index 0000000..eb1ae23 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/mainboard.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/io.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> + +static void ec_setup(void) +{ + /* Thermal limits? Values are from ectool's RAM dump. */ + //ec_write(0xd1, 0x57); /* CPUH */ + //ec_write(0xd2, 0xc9); /* CPUL */ + //ec_write(0xd4, 0x64); /* SYSH */ + //ec_write(0xd5, 0xc9); /* SYSL */ + + //send_ec_command(0x04); /* Set_SMI_Enable */ + //send_ec_command(0xab); /* Set_ACPI_Disable */ + //send_ec_command(0xac); /* Clr_SYS_Flag? well, why not? */ + //send_ec_command(0xad); /* Set_Thml_Value */ +} + +static void mainboard_enable(struct device *dev) +{ + ec_setup(); + /* LCD panel type is SIO GPIO40-43. + It's controlled by a DIP switch but was always + set to 4 while only values of 5 and 6 worked. */ + //install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, (inb(0x60f) & 0x0f) + 1); + + /* We have no driver for the embedded controller since the firmware + does most of the job. Hence, initialize keyboards here. */ + pc_keyboard_init(NO_AUX_DEVICE); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/toshiba/a300-1me/romstage.c b/src/mainboard/toshiba/a300-1me/romstage.c new file mode 100644 index 0000000..dc2b900 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/romstage.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <device/pci_ops.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <northbridge/intel/gm45/gm45.h> + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_setup_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); + /* Map COMa on 0x3f8, COMb on 0x2f8. */ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */ + pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); +} + +void mb_setup_superio(void) +{ + // #FIXME: WPCE775 support +} + +void get_mb_spd_addrmap(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +} diff --git a/src/mainboard/toshiba/a300-1me/smistuff.c b/src/mainboard/toshiba/a300-1me/smistuff.c new file mode 100644 index 0000000..72f1d35 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/smistuff.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801ix/nvs.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <ec/acpi/ec.h> + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 1)) { + printk(BIOS_DEBUG, "EC/SMI\n"); + /* TODO */ + } +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(0x05); /* Set_SMI_Disable */ + send_ec_command(0xaa); /* Set_ACPI_Enable */ + break; + + case APM_CNT_ACPI_DISABLE: + send_ec_command(0x04); /* Set_SMI_Enable */ + send_ec_command(0xab); /* Set_ACPI_Disable */ + break; + } + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d Gerrit-Change-Number: 34786 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: arch/x86: Move stack with CAR_GLOBAL_MIGRATION
by Kyösti Mälkki (Code Review) 24 May '20

24 May '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34882 ) Change subject: arch/x86: Move stack with CAR_GLOBAL_MIGRATION ...................................................................... arch/x86: Move stack with CAR_GLOBAL_MIGRATION With the combination of CAR_GLOBAL_MIGRATION=n and POSTCAR_STAGE=n it is expected that ramstage decompression will run in romstage. Due the way MAYBE_STATIC was defined the scratchpad of ulzman() would remain on the stack. This would conflict with the small allocation made for the stack when we have C_ENVIRONMENT_BOOTBLOCK=y. Expand the definition of MAYBE_STATIC to cover the cases that have zero-initialisation or no initialisation. These can be located in .bss. As the large stack requirement now only applies to CAR_GLOBAL_MIGRATION=y case, stack location within CAR region can be based on that instead. Change-Id: I58d50c6f8f922c9e8664698d77836cac2c13b126 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/cpu/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/device/device_const.c M src/include/stddef.h M src/lib/lzma.c M src/lib/timestamp.c M src/northbridge/intel/haswell/Kconfig M src/security/tpm/tspi/log.c M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig 14 files changed, 20 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34882/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5351fc7..6911505 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -40,7 +40,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(CAR_GLOBAL_MIGRATION) _car_stack_start = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _car_stack_end = .; @@ -91,7 +91,7 @@ _car_global_end = .; _car_relocatable_data_end = .; -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(CAR_GLOBAL_MIGRATION) _car_stack_start = .; _car_stack_end = _car_region_end; #endif diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 3c0bf89..7982569 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -21,7 +21,12 @@ hex config DCACHE_BSP_STACK_SIZE + depends on !CAR_GLOBAL_MIGRATION hex + default 0x2000 + help + The amount of anticipated stack usage by bootblock and + other pre-ram stages. config SMP bool diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index d3af4ca..b1b310d 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -21,11 +21,4 @@ hex default 0x4000 -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - endif diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 1453f99..65ac777 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -28,8 +28,4 @@ hex default 0x4000 -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - endif # CPU_INTEL_SOCKET_MPGA604 diff --git a/src/device/device_const.c b/src/device/device_const.c index c472aea..ef16d4b 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -204,7 +204,7 @@ DEVTREE_CONST struct bus *pci_root_bus(void) { DEVTREE_CONST struct device *pci_domain; - MAYBE_STATIC DEVTREE_CONST struct bus *pci_root = NULL; + DECLARE_MAYBE_STATIC_ZERO(DEVTREE_CONST struct bus *pci_root); if (pci_root) return pci_root; diff --git a/src/include/stddef.h b/src/include/stddef.h index 7cae2e6..26b9ef6 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -42,6 +42,14 @@ #define MAYBE_STATIC static #endif +#if defined(__PRE_RAM__) && CONFIG(CAR_GLOBAL_MIGRATION) +#define MAYBE_STATIC_NOINIT +#define DECLARE_MAYBE_STATIC_ZERO(x) x = 0 +#else +#define MAYBE_STATIC_NOINIT static +#define DECLARE_MAYBE_STATIC_ZERO(x) static x +#endif + #ifndef __ROMCC__ /* Provide a pointer to address 0 that thwarts any "accessing this is * undefined behaviour and do whatever" trickery in compilers. diff --git a/src/lib/lzma.c b/src/lib/lzma.c index eecbb26..7700380 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -26,7 +26,7 @@ int res; CLzmaDecoderState state; SizeT mallocneeds; - MAYBE_STATIC unsigned char scratchpad[15980]; + MAYBE_STATIC_NOINIT unsigned char scratchpad[15980]; const unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 1319b86..931da3f 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -128,7 +128,7 @@ static struct timestamp_table *timestamp_table_get(void) { - MAYBE_STATIC struct timestamp_table *ts_table = NULL; + DECLARE_MAYBE_STATIC_ZERO(struct timestamp_table *ts_table); struct timestamp_cache *ts_cache; if (ts_table != NULL) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index aad2674..847cc69 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -70,13 +70,6 @@ help The amount of cache-as-ram region required by the reference code. -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 4019962..a513860 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -26,7 +26,7 @@ static struct tcpa_table *tcpa_cbmem_init(void) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + DECLARE_MAYBE_STATIC_ZERO(struct tcpa_table *tclt); if (tclt) return tclt; @@ -47,7 +47,7 @@ static struct tcpa_table *tcpa_log_init(void) { - MAYBE_STATIC struct tcpa_table *tclt = NULL; + DECLARE_MAYBE_STATIC_ZERO(struct tcpa_table *tclt); /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 26b2ec4..9f2bc06 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -87,7 +87,6 @@ default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index f1d08c0..b494166 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -103,7 +103,6 @@ default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d6438f..7b41f0c 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -50,13 +50,6 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select C_ENVIRONMENT_BOOTBLOCK -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5856ef1..dc4dd44 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -119,13 +119,6 @@ help The amount of cache-as-ram region required by the reference code. -config DCACHE_BSP_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage in CAR by bootblock and - other stages. - config HAVE_MRC bool "Add a Memory Reference Code binary" help -- To view, visit https://review.coreboot.org/c/coreboot/+/34882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58d50c6f8f922c9e8664698d77836cac2c13b126 Gerrit-Change-Number: 34882 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 20

Change in ...coreboot[master]: src/mainboard: Add dell/inspiron_n5110
by Angel Pons (Code Review) 23 May '20

23 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30996 Change subject: src/mainboard: Add dell/inspiron_n5110 ...................................................................... src/mainboard: Add dell/inspiron_n5110 Run autoport and clean up. It has Nvidia Optimus, a NPCE795 EC, a PCIe xHCI controller and who knows what else. The 4MB flash is shared with the EC, apparently. Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/inspiron_n5110/Kconfig A src/mainboard/dell/inspiron_n5110/Kconfig.name A src/mainboard/dell/inspiron_n5110/Makefile.inc A src/mainboard/dell/inspiron_n5110/acpi/ec.asl A src/mainboard/dell/inspiron_n5110/acpi/platform.asl A src/mainboard/dell/inspiron_n5110/acpi/superio.asl A src/mainboard/dell/inspiron_n5110/acpi_tables.c A src/mainboard/dell/inspiron_n5110/board_info.txt A src/mainboard/dell/inspiron_n5110/devicetree.cb A src/mainboard/dell/inspiron_n5110/dsdt.asl A src/mainboard/dell/inspiron_n5110/gma-mainboard.ads A src/mainboard/dell/inspiron_n5110/gpio.c A src/mainboard/dell/inspiron_n5110/hda_verb.c A src/mainboard/dell/inspiron_n5110/mainboard.c A src/mainboard/dell/inspiron_n5110/romstage.c 17 files changed, 685 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30996/1 diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig b/src/mainboard/dell/inspiron_n5110/Kconfig new file mode 100644 index 0000000..1a12055 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/Kconfig @@ -0,0 +1,54 @@ +if BOARD_DELL_INSPIRON_N5110 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select GFX_GMA_INTERNAL_IS_LVDS + select SERIRQ_CONTINUOUS_MODE + select NO_UART_ON_SUPERIO + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + +config MAINBOARD_DIR + string + default dell/inspiron_n5110 + +config MAINBOARD_PART_NUMBER + string + default "Inspiron N5110" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x4b0 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1028 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/inspiron_n5110/Kconfig.name b/src/mainboard/dell/inspiron_n5110/Kconfig.name new file mode 100644 index 0000000..06334cd --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_INSPIRON_N5110 + bool "Inspiron N5110" diff --git a/src/mainboard/dell/inspiron_n5110/Makefile.inc b/src/mainboard/dell/inspiron_n5110/Makefile.inc new file mode 100644 index 0000000..ea035d3 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/inspiron_n5110/acpi/ec.asl b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi/ec.asl diff --git a/src/mainboard/dell/inspiron_n5110/acpi/platform.asl b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl new file mode 100644 index 0000000..cf5d74f --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/dell/inspiron_n5110/acpi/superio.asl b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi/superio.asl diff --git a/src/mainboard/dell/inspiron_n5110/acpi_tables.c b/src/mainboard/dell/inspiron_n5110/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/inspiron_n5110/board_info.txt b/src/mainboard/dell/inspiron_n5110/board_info.txt new file mode 100644 index 0000000..f48c92b --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/dell/inspiron_n5110/devicetree.cb b/src/mainboard/dell/inspiron_n5110/devicetree.cb new file mode 100644 index 0000000..be4f590 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/devicetree.cb @@ -0,0 +1,73 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x0000035e" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "3000" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x1028 0x04b0 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen2_dec" = "0x0004006d" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 1 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x21" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/inspiron_n5110/dsdt.asl b/src/mainboard/dell/inspiron_n5110/dsdt.asl new file mode 100644 index 0000000..1b0cae2 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/inspiron_n5110/gpio.c b/src/mainboard/dell/inspiron_n5110/gpio.c new file mode 100644 index 0000000..7926ee1 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/inspiron_n5110/hda_verb.c b/src/mainboard/dell/inspiron_n5110/hda_verb.c new file mode 100644 index 0000000..a70733b --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76d1, /* Codec Vendor / Device ID: IDT */ + 0x102804b0, /* Subsystem ID */ + + 0x00000007, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x102804b0), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x04a11020), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f2), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30160), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/inspiron_n5110/mainboard.c b/src/mainboard/dell/inspiron_n5110/mainboard.c new file mode 100644 index 0000000..02fe3a5 --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/inspiron_n5110/romstage.c b/src/mainboard/dell/inspiron_n5110/romstage.c new file mode 100644 index 0000000..fd2f79f --- /dev/null +++ b/src/mainboard/dell/inspiron_n5110/romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004006d); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Assumed completely. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7dba0e4e7e80c51c5f5c0e8a2f1a2ac23451b9 Gerrit-Change-Number: 30996 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019