Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32531
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal Coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc A configs/config.51nb_x210 M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 31 files changed, 2,530 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/1
diff --git a/Makefile.inc b/Makefile.inc index fc04a16..6e379dd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -88,7 +88,7 @@ ####################################################################### # root source directories of coreboot subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi -subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) +subdirs-y += src/ec/acpi src/ec/51nb $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) diff --git a/configs/config.51nb_x210 b/configs/config.51nb_x210 new file mode 100644 index 0000000..6217eb6 --- /dev/null +++ b/configs/config.51nb_x210 @@ -0,0 +1,838 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="1" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +CONFIG_BOOTSPLASH_IMAGE=y +CONFIG_BOOTSPLASH_FILE="" + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +CONFIG_VENDOR_51NB=y +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_51NB_X210=y +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="51nb" +CONFIG_MAINBOARD_FAMILY="X210" +CONFIG_MAINBOARD_PART_NUMBER="X210" +CONFIG_MAINBOARD_VERSION="2.0" +CONFIG_MAINBOARD_DIR="51nb/x210" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_MAX_CPUS=8 +# CONFIG_NO_POST is not set +CONFIG_VGA_BIOS_ID="8086,5917" +CONFIG_DIMM_MAX=2 +CONFIG_DIMM_SPD_SIZE=512 +CONFIG_CPU_MICROCODE_CBFS_LEN=0x18000 +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFE115A0 +CONFIG_CBFS_SIZE=0x5c0000 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="Unknown Serial Number" +CONFIG_VGA_BIOS_FILE="vgabios.bin" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="51nb" +CONFIG_INTEL_GMA_VBT_FILE="vbt.bin" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +# CONFIG_POST_IO is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_VBOOT is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="X210" +CONFIG_IFD_BIN_PATH="descriptor.bin" +CONFIG_ME_BIN_PATH="me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_HEAP_SIZE=0x80000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +# CONFIG_CONSOLE_CBMEM is not set +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_SKYLAKE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +# CONFIG_SKYLAKE_SOC_PCH_H is not set +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y + +# +# Multiple Processor (MP) Initialization Options +# +CONFIG_USE_COREBOOT_NATIVE_MP_INIT=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_51NB=y + +# +# Please select the following otherwise your laptop cannot be powered on. +# +CONFIG_51NB_EC_FIRMWARE=y +CONFIG_51NB_EC_FW="ec.bin" +CONFIG_51NB_EC_FW_OFFSET="0x00200000" +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_CHECK_ME is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SMMSTORE=y +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SMMSTORE_REGION="SMMSTORE" +CONFIG_SMMSTORE_FILENAME="smm_store" +CONFIG_SMMSTORE_SIZE=0x40000 +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +CONFIG_SPI_FLASH_SMM=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_TPM_INIT=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_FSP_CAR is not set +CONFIG_FSP_M_XIP=y +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +# CONFIG_USER_NO_TPM is not set +# CONFIG_USER_TPM1 is not set +CONFIG_USER_TPM2=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_PAYLOAD_FILE="payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_TIANOCORE_STABLE=y +# CONFIG_TIANOCORE_REVISION is not set +# CONFIG_TIANOCORE_TARGET_IA32 is not set +CONFIG_TIANOCORE_TARGET_X64=y +# CONFIG_TIANOCORE_DEBUG is not set +CONFIG_TIANOCORE_RELEASE=y +# CONFIG_TIANOCORE_USE_8254_TIMER is not set +# CONFIG_TIANOCORE_BOOTSPLASH_IMAGE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set +CONFIG_MEMTEST_STABLE=y +# CONFIG_MEMTEST_MASTER is not set +# CONFIG_MEMTEST_REVISION is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_SPD_READ_BY_WORD=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/src/Kconfig b/src/Kconfig index 90c724e..4688fd3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -369,6 +369,7 @@ source "src/superio/*/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" +source "src/ec/51nb/Kconfig" source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" diff --git a/src/ec/51nb/51nb.c b/src/ec/51nb/51nb.c new file mode 100644 index 0000000..2559176 --- /dev/null +++ b/src/ec/51nb/51nb.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> + +#include "ec.h" + +static void ec_51nb_ops_enable(struct device *dev) +{ + /* Enable function 5 (PS/2 AUX) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x05, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); + + /* Enable function 6 (PS/2 KB) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x06, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); + + /* Enable funcion 17 (EC) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x11, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); +} + +struct chip_operations ec_51nb_ops = { + CHIP_NAME("51NB EC") + .enable_dev = ec_51nb_ops_enable, +}; diff --git a/src/ec/51nb/Kconfig b/src/ec/51nb/Kconfig new file mode 100644 index 0000000..ca93a7e --- /dev/null +++ b/src/ec/51nb/Kconfig @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config EC_51NB + bool + help + Support for the 51NB EC + +if EC_51NB + +comment "Please select the following otherwise your laptop cannot be powered on." + +config 51NB_EC_FIRMWARE + bool "Add firmware images for 51NB EC" + depends on EC_51NB + default y + help + Select this option to add the firmware blob for the 51NB EC. + You need this blob to power on your machine. + +config 51NB_EC_FW + string "51NB EC firmware path" + depends on 51NB_EC_FIRMWARE + default "ec.bin" + help + The path and filename of the file to use as 51NB firmware. + +config 51NB_EC_FW_OFFSET + string + depends on 51NB_EC_FIRMWARE + default "0x00200000" + +endif diff --git a/src/ec/51nb/Makefile.inc b/src/ec/51nb/Makefile.inc new file mode 100644 index 0000000..b41febb --- /dev/null +++ b/src/ec/51nb/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_EC_51NB),y) +51NB_EC_INSERT:=$(top)/util/51nb/51nb_ec_insert +INTERMEDIATE+=51nb_ec_insert + +51nb_ec_insert: $(obj)/coreboot.pre +ifeq ($(CONFIG_51NB_EC_FIRMWARE),y) + printf " Building 51nb_ec_insert.\n" + $(MAKE) -C util/51nb + printf " Inserting EC firmware blobs.\n" + $(51NB_EC_INSERT) $(obj)/coreboot.pre \ + $(CONFIG_51NB_EC_FW) $(CONFIG_51NB_EC_FW_OFFSET) +endif + +PHONY+=51nb_ec_insert + +build_complete:: +ifeq ($(CONFIG_51NB_EC_FIRMWARE),) + printf "\n** WARNING **\n" + printf "You haven't added the firmware blobs for 51NB EC.\n" + printf "You may be unable to power on your laptop without these blobs.\n" + printf "Please select the following option to add them:\n\n" + printf " Chipset --->\n" + printf " [*] Add firmware images for 51NB EC\n\n" +endif + +ramstage-y += 51nb.c + +endif diff --git a/src/ec/51nb/ec.h b/src/ec/51nb/ec.h new file mode 100644 index 0000000..831514c --- /dev/null +++ b/src/ec/51nb/ec.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _EC_51NB_H +#define _EC_51NB_H + +#define SETUP_COMMAND 0x4e +#define SETUP_DATA 0x4f +#define LDN_SEL 0x07 +#define LDN_ENABLE 0x30 + +#endif /* _EC_51NB_H */ diff --git a/src/mainboard/51nb/Kconfig b/src/mainboard/51nb/Kconfig new file mode 100644 index 0000000..12d2c0d --- /dev/null +++ b/src/mainboard/51nb/Kconfig @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if VENDOR_51NB + +choice + prompt "Mainboard model" + +source "src/mainboard/51nb/*/Kconfig.name" + +endchoice + +source "src/mainboard/51nb/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "51NB" + +endif # VENDOR_51NB diff --git a/src/mainboard/51nb/Kconfig.name b/src/mainboard/51nb/Kconfig.name new file mode 100644 index 0000000..6f99514 --- /dev/null +++ b/src/mainboard/51nb/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_51NB + bool "51NB" diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig new file mode 100644 index 0000000..d5dd278 --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig @@ -0,0 +1,76 @@ +config BOARD_51NB_X210 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select EC_51NB + +if BOARD_51NB_X210 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "51NB" + +config MAINBOARD_FAMILY + string + default "X210" + +config MAINBOARD_PART_NUMBER + string + default "X210" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "51nb/x210" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 8 + +config NO_POST + def_bool y + help + This platform does not have any way to see POST codes + so disable them by default. + +config VGA_BIOS_ID + string + default "8086,5917" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/51nb/x210/Kconfig.name b/src/mainboard/51nb/x210/Kconfig.name new file mode 100644 index 0000000..1cae5dd --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_51NB_X210 + bool "51NB X210" diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc new file mode 100644 index 0000000..5d44e9b --- /dev/null +++ b/src/mainboard/51nb/x210/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += pei_data.c + +ramstage-y += pei_data.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl new file mode 100644 index 0000000..1b0d6c2 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 0x4F) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x50), + CTMP, 8, + CFAN, 8, + B1SS, 1, + BSTS, 2, + ACIN, 1, + Offset (0x53), + BKLG, 8, + TOUP, 1, + WIRE, 1, + BLTH, 1, + LIDC, 1, + APFG, 1, + WRST, 1, + BTST, 1, + ACEB, 1, + CAME, 1, + Offset (0x60), + DGCP, 16, + FLCP, 16, + DGVO, 16, + BDW, 16, + BDL, 16, + BPR, 16, + BRC, 16, + BPV, 16 + } + + Method (_REG, 2, NotSerialized) + { + /* Initialize AC power state */ + Store (ACIN, \PWRS) + + /* Initialize LID switch state */ + Store (LIDC, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q04) + { + Notify(_SB.PCI0.GFX0.LCD, 0x86) + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q05) + { + Notify(_SB.PCI0.GFX0.LCD, 0x87) + } + + /* Battery Information Event */ + Method (_Q0C) + { + Notify (BAT, 0x81) + } + + /* AC event */ + Method (_Q0D) + { + Store (ACIN, \PWRS) + Notify (AC, 0x80) + } + + /* Lid event */ + Method (_Q0E) + { + Store (LIDC, \LIDS) + Notify (LID0, 0x80) + } + + /* Battery Information Event */ + Method (_Q13) + { + Notify (BAT, 0x81) + } + + /* Battery Status Event */ + Method (_Q14) + { + Notify (BAT, 0x80) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { _SB }) + + Method (_STA) + { + Return (0x0F) + } + Method (_PSR) + { + Return (\PWRS) + } + } + + Device (BAT) + { + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { _SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B1SS) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "Y91", /* 0x09: Model Number */ + "", /* 0x0a: Serial Number */ + "LION", /* 0x0b: Battery Type */ + "CJOYIN" /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, Serialized) + { + /* Design Capacity */ + Store (DGCP, Index (PBIF, 1)) + + /* Last Full Charge Capacity */ + Store (FLCP, Index (PBIF, 2)) + + /* Design Voltage */ + Store (DGVO, Index (PBIF, 4)) + + /* Design Capacity of Warning */ + Store (BDW, Index (PBIF, 5)) + + /* Design Capacity of Low */ + Store (BDL, Index (PBIF, 6)) + + Return (PBIF) + } + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + /* + * 0: BATTERY STATE + * + * bit 0 = discharging + * bit 1 = charging + * bit 2 = critical level + */ + Store (BSTS, Index (PBST, 0)) + + /* + * 1: BATTERY PRESENT RATE + */ + Store (BPR, Index (PBST, 1)) + + /* + * 2: BATTERY REMAINING CAPACITY + */ + Store (BRC, Index (PBST, 2)) + + /* + * 3: BATTERY PRESENT VOLTAGE + */ + Store (BPV, Index (PBST, 3)) + + Return (PBST) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl new file mode 100644 index 0000000..ce9fb04 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0.GFX0) +{ + Device (LCD) + { + Method (_ADR, 0, Serialized) + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) + { + Return (Package (0x12) + { + 0x0A, + 0x0F, + 0x00, + 0x01, + 0x02, + 0x03, + 0x04, + 0x05, + 0x06, + 0x07, + 0x08, + 0x09, + 0x0A, + 0x0B, + 0x0C, + 0x0D, + 0x0E, + 0x0F + }) + } + Method (_BCM, 1, NotSerialized) + { + _SB.PCI0.LPCB.EC.BKLG = Arg0 + } + Method (_BQC, 0, NotSerialized) + { + Return (_SB.PCI0.LPCB.EC.BKLG) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl new file mode 100644 index 0000000..efe0e8d --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) + { + Return (0xF) + } + + Method (_LID) + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl new file mode 100644 index 0000000..7ea85b6 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014-2019 Google LLC + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Store(_SB.PCI0.LPCB.EC.LIDC, \LIDS) + Store(_SB.PCI0.LPCB.EC.ACIN, \PWRS) + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/51nb/x210/acpi_tables.c b/src/mainboard/51nb/x210/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi_tables.c diff --git a/src/mainboard/51nb/x210/board_info.txt b/src/mainboard/51nb/x210/board_info.txt new file mode 100644 index 0000000..65c4608 --- /dev/null +++ b/src/mainboard/51nb/x210/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: 51NB +Board name: Thinkpad X210 +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb new file mode 100644 index 0000000..9463470 --- /dev/null +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -0,0 +1,222 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable Root Ports 1, 4 and 9 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/51nb + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl new file mode 100644 index 0000000..f651532 --- /dev/null +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015-2019 Google LLC + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h new file mode 100644 index 0000000..2a00d54 --- /dev/null +++ b/src/mainboard/51nb/x210/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +}; + +#endif + +#endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c new file mode 100644 index 0000000..e8eecdf --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/51nb/x210/hda_verb.h b/src/mainboard/51nb/x210/hda_verb.h new file mode 100644 index 0000000..c721c25 --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2019 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa2155, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa2155 */ + AZALIA_SUBVENDOR(0x0, 0x17aa2155), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x042140f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a190f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a190f0), + + /* Pin Complex (NID 0x1C) */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x612140f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x601700f0), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + + /* Pin Complex (NID 0x1F) */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x901701f0), + + /* Pin Complex (NID 0x20) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x40f001f0), + + /* Pin Complex (NID 0x22) */ + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + + /* Pin Complex (NID 0x23) */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a601f0), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c new file mode 100644 index 0000000..8e9266d --- /dev/null +++ b/src/mainboard/51nb/x210/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <device/device.h> +#include <intelblocks/lpc_lib.h> +#include <string.h> +#include <smbios.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} + +static void mainboard_enable(struct device *dev) +{ + /* Route 0x4e/4f to LPC */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/51nb/x210/pei_data.c b/src/mainboard/51nb/x210/pei_data.c new file mode 100644 index 0000000..0be917d --- /dev/null +++ b/src/mainboard/51nb/x210/pei_data.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "pei_data.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/51nb/x210/pei_data.h b/src/mainboard/51nb/x210/pei_data.h new file mode 100644 index 0000000..320d980 --- /dev/null +++ b/src/mainboard/51nb/x210/pei_data.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_PEI_DATA_H_ +#define _MAINBOARD_PEI_DATA_H_ + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/51nb/x210/ramstage.c b/src/mainboard/51nb/x210/ramstage.c new file mode 100644 index 0000000..7888c39 --- /dev/null +++ b/src/mainboard/51nb/x210/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015-2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c new file mode 100644 index 0000000..98270f0 --- /dev/null +++ b/src/mainboard/51nb/x210/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015-2019 Google LLC + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <arch/io.h> +#include "pei_data.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} diff --git a/util/51nb/51nb_ec_insert.c b/util/51nb/51nb_ec_insert.c new file mode 100644 index 0000000..0f5e204 --- /dev/null +++ b/util/51nb/51nb_ec_insert.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai mytbk920423@gmail.com + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> + +static void usage(const char *s) +{ + printf("insert firmware blobs:\n\t" + "%s <rom file> <fw> <fw offset>\n\n", + s); + exit(1); +} + +static void FseekEnd(FILE *fp, long o) +{ + if (fseek(fp, o, SEEK_END) != 0) { + puts("fseek() error!\n"); + exit(1); + } +} + +static long negoffset(long a, long romsz) +{ + if (a > 0) { + if (a & 0x80000000) /* the address in memory, and sizeof(long) + is 8 */ + return a - 0x100000000; + else /* the file offset */ + return a - romsz; + } else { + return a; + } +} + +int main(int argc, char *argv[]) +{ + FILE *fp, *fw; + long offset; + + if (argc != 4) + usage(argv[0]); + + fp = fopen(argv[1], "rb+"); + if (fp == NULL) { + puts("Error opening firmware image!"); + exit(1); + } + + fw = fopen(argv[2], "rb"); + offset = strtoul(argv[3], NULL, 0); + if (fw == NULL) { + puts("Error opening file!"); + exit(1); + } + + if (offset & 0xf) { + puts("The offsets must be aligned to 0x100"); + exit(1); + } + + long romsz; + FseekEnd(fp, -1); + romsz = ftell(fp) + 1; + printf("size of %s: 0x%lx\n", argv[1], romsz); + + if (romsz & 0xff) { + puts("The ROM size must be multiple of 0x100"); + exit(1); + } + + offset = negoffset(offset, romsz); + + puts(""); + + /* write fw1 and fw2 */ + char c; + FseekEnd(fp, offset); + printf("writing to 0x%lx\n", ftell(fp)); + while (fread(&c, 1, 1, fw) == 1) { + fwrite(&c, 1, 1, fp); + } + fclose(fw); + fclose(fp); + return 0; +} diff --git a/util/51nb/Makefile b/util/51nb/Makefile new file mode 100644 index 0000000..b6c13d6 --- /dev/null +++ b/util/51nb/Makefile @@ -0,0 +1,12 @@ +obj = 51nb_ec_insert +HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) + +all: $(obj) + +%: %.c + $(HOSTCC) -Wall -o $@ $< + +clean: + rm -f 51nb_ec_insert + +.PHONY: all clean
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 1:
(31 comments)
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@23 PS1, Line 23: /* Enable function 5 (PS/2 AUX) */ code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@24 PS1, Line 24: outb(LDN_SEL, SETUP_COMMAND); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@24 PS1, Line 24: outb(LDN_SEL, SETUP_COMMAND); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@25 PS1, Line 25: outb(0x05, SETUP_DATA); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@25 PS1, Line 25: outb(0x05, SETUP_DATA); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@26 PS1, Line 26: outb(LDN_ENABLE, SETUP_COMMAND); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@26 PS1, Line 26: outb(LDN_ENABLE, SETUP_COMMAND); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@27 PS1, Line 27: outb(0x01, SETUP_DATA); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@27 PS1, Line 27: outb(0x01, SETUP_DATA); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@29 PS1, Line 29: /* Enable function 6 (PS/2 KB) */ code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@30 PS1, Line 30: outb(LDN_SEL, SETUP_COMMAND); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@30 PS1, Line 30: outb(LDN_SEL, SETUP_COMMAND); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@31 PS1, Line 31: outb(0x06, SETUP_DATA); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@31 PS1, Line 31: outb(0x06, SETUP_DATA); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@32 PS1, Line 32: outb(LDN_ENABLE, SETUP_COMMAND); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@32 PS1, Line 32: outb(LDN_ENABLE, SETUP_COMMAND); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@33 PS1, Line 33: outb(0x01, SETUP_DATA); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@33 PS1, Line 33: outb(0x01, SETUP_DATA); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@35 PS1, Line 35: /* Enable funcion 17 (EC) */ 'funcion' may be misspelled - perhaps 'function'?
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@35 PS1, Line 35: /* Enable funcion 17 (EC) */ code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@36 PS1, Line 36: outb(LDN_SEL, SETUP_COMMAND); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@36 PS1, Line 36: outb(LDN_SEL, SETUP_COMMAND); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@37 PS1, Line 37: outb(0x11, SETUP_DATA); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@37 PS1, Line 37: outb(0x11, SETUP_DATA); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@38 PS1, Line 38: outb(LDN_ENABLE, SETUP_COMMAND); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@38 PS1, Line 38: outb(LDN_ENABLE, SETUP_COMMAND); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@39 PS1, Line 39: outb(0x01, SETUP_DATA); code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/src/ec/51nb/51nb.c@39 PS1, Line 39: outb(0x01, SETUP_DATA); please, no spaces at the start of a line
https://review.coreboot.org/#/c/32531/1/src/mainboard/51nb/x210/mainboard.c File src/mainboard/51nb/x210/mainboard.c:
https://review.coreboot.org/#/c/32531/1/src/mainboard/51nb/x210/mainboard.c@... PS1, Line 57: /* Route 0x4e/4f to LPC */ code indent should use tabs where possible
https://review.coreboot.org/#/c/32531/1/util/51nb/51nb_ec_insert.c File util/51nb/51nb_ec_insert.c:
https://review.coreboot.org/#/c/32531/1/util/51nb/51nb_ec_insert.c@65 PS1, Line 65: if (fw == NULL) { suspect code indent for conditional statements (8, 24)
https://review.coreboot.org/#/c/32531/1/util/51nb/51nb_ec_insert.c@93 PS1, Line 93: while (fread(&c, 1, 1, fw) == 1) { braces {} are not necessary for single statement blocks
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#2).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal Coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc A configs/config.51nb_x210 M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 31 files changed, 2,529 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32531/2/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/2/src/ec/51nb/51nb.c@35 PS2, Line 35: /* Enable funcion 17 (EC) */ 'funcion' may be misspelled - perhaps 'function'?
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32531/3/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/3/src/ec/51nb/51nb.c@35 PS3, Line 35: /* Enable funcion 17 (EC) */ 'funcion' may be misspelled - perhaps 'function'?
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/32531/4/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/4/src/ec/51nb/51nb.c@35 PS4, Line 35: /* Enable funcion 17 (EC) */ 'funcion' may be misspelled - perhaps 'function'?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#5).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal Coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc A configs/config.51nb_x210 M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 31 files changed, 2,529 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/5
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#6).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 30 files changed, 1,692 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/6
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#8).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 30 files changed, 1,692 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/8
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 8: Code-Review-1
(5 comments)
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c@23 PS8, Line 23: /* Enable function 5 (PS/2 AUX) */ looks like superio stuff and should be moved to src/superio/51nb/ Is it a common superio, like ITE?
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig File src/ec/51nb/Kconfig:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig@43 PS8, Line 43: 0x00200000 is that the offset of the IFD ec region?
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Makefile.inc File src/ec/51nb/Makefile.inc:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Makefile.inc@25 PS8, Line 25: $(51NB_EC_INSERT) $(obj)/coreboot.pre \ is the IFD ec region in use?
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h File src/ec/51nb/ec.h:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h@20 PS8, Line 20: #define SETUP_COMMAND 0x4e probably mainboard specific
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/hda_verb.c File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/hda_verb.c@2... PS8, Line 25: no need for this file. use soc/intel/common/block/hda/hda.c instead
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 8:
(5 comments)
Patch Set 8: Code-Review-1
(5 comments)
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c@23 PS8, Line 23: /* Enable function 5 (PS/2 AUX) */
looks like superio stuff and should be moved to src/superio/51nb/ […]
I'm not sure? There's no superio on the board, just the EC, and the EC also handles PS/2. It's using the same LDN functions as the Nuvoton SuperIOs for this purpose, but I can't see any other similarities.
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig File src/ec/51nb/Kconfig:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig@43 PS8, Line 43: 0x00200000
is that the offset of the IFD ec region?
No
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Makefile.inc File src/ec/51nb/Makefile.inc:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Makefile.inc@25 PS8, Line 25: $(51NB_EC_INSERT) $(obj)/coreboot.pre \
is the IFD ec region in use?
No, vendor firmware doesn't use the IFD ec region.
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h File src/ec/51nb/ec.h:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h@20 PS8, Line 20: #define SETUP_COMMAND 0x4e
probably mainboard specific
No, this is (as far as I can tell) specific to the EC part.
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/hda_verb.c File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/hda_verb.c@2... PS8, Line 25:
no need for this file. use soc/intel/common/block/hda/hda. […]
Will do.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 8:
(9 comments)
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG@10 PS8, Line 10: firmware protection What does this refer to? Is the IFD fully unlocked? Are all protected ranges unset? Does it not use Boot Guard?
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG@15 PS8, Line 15: EC firmware is contained within the system SPI flash, and so a blob of : EC firmware must be injected to a defined location during image build. I would suggest using a fmap to define this location. I was suggested the same for a laptop with the same problem.
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG@27 PS8, Line 27: I'd suggest listing what works/does not work/is untested.
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c@23 PS8, Line 23: /* Enable function 5 (PS/2 AUX) */
I'm not sure? There's no superio on the board, just the EC, and the EC also handles PS/2. […]
Some ECs have a SuperIO-like part. See ec/roda/it8518 for an example.
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/51nb.c@43 PS8, Line 43: CHIP_NAME("51NB EC") Not sure if all the 51nb devices use the same EC. I'd suggest specifying the EC model (NPCE9...) so that there isn't a name conflict if a 2nd 51nb EC were to be added.
Yes, this would imply moving everything in a subfolder and updating all the paths.
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig File src/ec/51nb/Kconfig:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig@43 PS8, Line 43: 0x00200000
No
Is that the beginning of the BIOS region? Some other different Nuvoton EC I have has the firmware at the same location.
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h File src/ec/51nb/ec.h:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h@20 PS8, Line 20: #define SETUP_COMMAND 0x4e
No, this is (as far as I can tell) specific to the EC part.
I recall seeing 0x4e/0x4f somewhere else... These are the IO addresses the SuperIO part of the EC uses. These are sometimes selectable (most SuperIOs use 0x2e/0x2f).
I'd say this is mainboard-specific.
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/acpi/ec.asl File src/mainboard/51nb/x210/acpi/ec.asl:
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/acpi/ec.asl@... PS8, Line 126: Device (BAT) Maybe this could go in acpi/battery.asl
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/mainboard.c File src/mainboard/51nb/x210/mainboard.c:
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/mainboard.c@... PS8, Line 57: /* Route 0x4e/4f to LPC */ Ah, this is what I recall 0x4e/0x4f from.
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#9).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 29 files changed, 1,591 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/9
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#10).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc M src/Kconfig A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/ec.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 30 files changed, 1,517 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/10
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 10:
(7 comments)
Reworked based on comments, EC is now in a subdirectory, io port addresses are provided in devicetree, using an fmap to reserve space for the EC firmware (and copying it in using cbfstool rather than using a separate utility), using generic HDA code. Tested as working.
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG@10 PS8, Line 10: firmware protection
What does this refer to? Is the IFD fully unlocked? Are all protected ranges unset? Does it not use […]
Done
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG@15 PS8, Line 15: EC firmware is contained within the system SPI flash, and so a blob of : EC firmware must be injected to a defined location during image build.
I would suggest using a fmap to define this location. […]
Done
https://review.coreboot.org/#/c/32531/8//COMMIT_MSG@27 PS8, Line 27:
I'd suggest listing what works/does not work/is untested.
Done
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig File src/ec/51nb/Kconfig:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/Kconfig@43 PS8, Line 43: 0x00200000
Is that the beginning of the BIOS region? Some other different Nuvoton EC I have has the firmware at […]
Done
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h File src/ec/51nb/ec.h:
https://review.coreboot.org/#/c/32531/8/src/ec/51nb/ec.h@20 PS8, Line 20: #define SETUP_COMMAND 0x4e
I recall seeing 0x4e/0x4f somewhere else... […]
Done
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/acpi/ec.asl File src/mainboard/51nb/x210/acpi/ec.asl:
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/acpi/ec.asl@... PS8, Line 126: Device (BAT)
Maybe this could go in acpi/battery. […]
Done
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/mainboard.c File src/mainboard/51nb/x210/mainboard.c:
https://review.coreboot.org/#/c/32531/8/src/mainboard/51nb/x210/mainboard.c@... PS8, Line 57: /* Route 0x4e/4f to LPC */
Ah, this is what I recall 0x4e/0x4f from.
Done
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#11).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/ec.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,515 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/11
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#12).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,513 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/12
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 12: Code-Review+1
(3 comments)
Please add to Documentation: * What's working and what is not, and possible TODOs, like libgfxinit. * How to extract EC firmware from vendor bios * Position of flash IC and possible flash headers * Recommend one of the external flashing methods
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/Kconfig File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/Kconfig@14 PS12, Line 14: select MAINBOARD_HAS_LPC_TPM either select MAINBOARD_HAS_TPM1 or select MAINBOARD_HAS_TPM2, too
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/devicetree.... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/devicetree.... PS12, Line 198: device pci 1c.3 on end # PCI Express Port 4 what's behind those PCIe ports?
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/hda_verb.c File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/hda_verb.c@... PS12, Line 1: #include "hda_verb.h" no need for hda_verb.h, just place the contents in this file
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#13).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,536 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/13
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#14).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,536 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/14
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 13:
(3 comments)
Patch Set 12: Code-Review+1
(3 comments)
Please add to Documentation:
- What's working and what is not, and possible TODOs, like libgfxinit.
- How to extract EC firmware from vendor bios
- Position of flash IC and possible flash headers
- Recommend one of the external flashing methods
Docs added and other issues addressed.
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/Kconfig File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/Kconfig@14 PS12, Line 14: select MAINBOARD_HAS_LPC_TPM
either select MAINBOARD_HAS_TPM1 or select MAINBOARD_HAS_TPM2, too
Done - removed MAINBOARD_HAS_LPC_TPM as it doesn't actually have one
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/devicetree.... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/devicetree.... PS12, Line 198: device pci 1c.3 on end # PCI Express Port 4
what's behind those PCIe ports?
Done
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/hda_verb.c File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/#/c/32531/12/src/mainboard/51nb/x210/hda_verb.c@... PS12, Line 1: #include "hda_verb.h"
no need for hda_verb. […]
Done
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#15).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,551 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/15
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#16).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,555 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/16
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#17).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,556 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/17
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#19).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,557 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/19
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#20).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,552 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/20
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#21).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/chip.h A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c 28 files changed, 1,551 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/21
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 21:
(11 comments)
Nice port!
https://review.coreboot.org/#/c/32531/21/src/ec/51nb/npce985la0dx/npce985la0... File src/ec/51nb/npce985la0dx/npce985la0dx.c:
PS21: Using our pnp infrastructure this should be something like
static struct pnp_info dev_infos[] = { { NULL, 0x05 }, { NULL, 0x06 }, { NULL, 0x11 } }; static void ec_51nb_npce985la0dx_ops_enable(struct device *dev) { pnp_enabled_devices(dev, &pnp_ops, ARRAY_SIZE(dev_infos), dev_infos); }
plus in the devicetree
device pnp 4e.5 on end device pnp 4e.6 on end device pnp 4e.11 on end
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig@13 PS21, Line 13: select MAINBOARD_USES_FSP2_0 indent, please
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig@18 PS21, Line 18: default 18 Not useful (unless you want to write PIRQ tables)
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig@70 PS21, Line 70: default 0x59fe00 I'm not sure if this is meaningful in combination with a custom FMD.
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/devicetree.... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/devicetree.... PS21, Line 149: register "PcieRpEnable[2]" = "1" # Ethernet controller : register "PcieRpLtrEnable[2]" = "1" This is not RP1?
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/dsdt.asl File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/dsdt.asl@41 PS21, Line 41: #include <drivers/intel/gma/acpi/pch.asl> This is supposed to be used when the Intel gfx controls the backlight, but from your ASL code it looks like the EC is doing that?
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/mainboard.c File src/mainboard/51nb/x210/mainboard.c:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/mainboard.c... PS21, Line 53: } This seems like Purisms idea of how to store a serial number. You don't have to follow it. But if you want, it would be nice to put it somewhere in `src/lib/`.
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c File src/mainboard/51nb/x210/pei_data.c:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c@... PS21, Line 24: void mainboard_fill_dq_map_data(void *dq_map_ptr) : { : /* DQ byte map */ : const u8 dq_map[2][12] = { : { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, : 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, : { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, : 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; : memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); : } : : void mainboard_fill_dqs_map_data(void *dqs_map_ptr) : { : /* DQS CPU<>DRAM map */ : const u8 dqs_map[2][8] = { : { 0, 1, 3, 2, 4, 5, 6, 7 }, : { 1, 0, 4, 5, 2, 3, 6, 7 } }; : memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); : } : This is for memory-down configurations only.
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c@... PS21, Line 59: void mainboard_fill_pei_data(struct pei_data *pei_data) : { : mainboard_fill_dq_map_data(&pei_data->dq_map); : mainboard_fill_dqs_map_data(&pei_data->dqs_map); : mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); : mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); : } `pei_data` is a remnant from pre-FSP times. IIRC, the code of some Google boards use this to talk to itself, but otherwise implementing this function should be a no-op.
Probably worth to merge the two r-comp thingies into `romstage.c`.
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/ramstage.c File src/mainboard/51nb/x210/ramstage.c:
PS21: This would usually go into `mainboard.c`. It's a convention to have one default .c file for the main (ram) stage named after the entity (chip/board).
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/ramstage.c@... PS21, Line 5: * Copyright (C) 2015-2019 Google LLC I don't know how one function call can have 6 different dates of first publication, but I understand the urge to copy these lines.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c File src/mainboard/51nb/x210/pei_data.c:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c@... PS21, Line 59: void mainboard_fill_pei_data(struct pei_data *pei_data) : { : mainboard_fill_dq_map_data(&pei_data->dq_map); : mainboard_fill_dqs_map_data(&pei_data->dqs_map); : mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); : mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); : }
`pei_data` is a remnant from pre-FSP times. IIRC, the code of […]
Are these functions really used? I just searched the coreboot tree after them, but haven't found any calls except from the mainboard directory. Same with rcomp.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 21:
(1 comment)
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c File src/mainboard/51nb/x210/pei_data.c:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c@... PS21, Line 59: void mainboard_fill_pei_data(struct pei_data *pei_data) : { : mainboard_fill_dq_map_data(&pei_data->dq_map); : mainboard_fill_dqs_map_data(&pei_data->dqs_map); : mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); : mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); : }
Are these functions really used? I just searched the coreboot tree after them, but haven't found any […]
Not sure what you mean. The implementations above are only used in the mainboard code, yes. But also in `romstage.c` where FSP is effectively configured.
If you meant the mainboard_fill_pei_data() implementations, they are called from SoC level, but only to pass the data to mainboard_memory_ init_params() back later. That's what I called code talking to itself (via somebody else' struct). It's too weird, I try to get rid of it: topic:no_pei_data_hoops let's see if something compiles ^^
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 21:
(8 comments)
https://review.coreboot.org/#/c/32531/21/src/ec/51nb/npce985la0dx/npce985la0... File src/ec/51nb/npce985la0dx/npce985la0dx.c:
PS21:
Using our pnp infrastructure this should be something like […]
Ack
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig@13 PS21, Line 13: select MAINBOARD_USES_FSP2_0
indent, please
Ack
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig@18 PS21, Line 18: default 18
Not useful (unless you want to write PIRQ tables)
Ack
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/Kconfig@70 PS21, Line 70: default 0x59fe00
I'm not sure if this is meaningful in combination with a custom FMD.
Ack
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/dsdt.asl File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/dsdt.asl@41 PS21, Line 41: #include <drivers/intel/gma/acpi/pch.asl>
This is supposed to be used when the Intel gfx controls the […]
Fixed - removed the opregion support and just implemented enough code for Linux to bind to the device.
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c File src/mainboard/51nb/x210/pei_data.c:
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c@... PS21, Line 24: void mainboard_fill_dq_map_data(void *dq_map_ptr) : { : /* DQ byte map */ : const u8 dq_map[2][12] = { : { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, : 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, : { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, : 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; : memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); : } : : void mainboard_fill_dqs_map_data(void *dqs_map_ptr) : { : /* DQS CPU<>DRAM map */ : const u8 dqs_map[2][8] = { : { 0, 1, 3, 2, 4, 5, 6, 7 }, : { 1, 0, 4, 5, 2, 3, 6, 7 } }; : memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); : } :
This is for memory-down configurations only.
Ack
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/pei_data.c@... PS21, Line 59: void mainboard_fill_pei_data(struct pei_data *pei_data) : { : mainboard_fill_dq_map_data(&pei_data->dq_map); : mainboard_fill_dqs_map_data(&pei_data->dqs_map); : mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); : mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); : }
Not sure what you mean. The implementations above are only used in the […]
Ack
https://review.coreboot.org/#/c/32531/21/src/mainboard/51nb/x210/ramstage.c File src/mainboard/51nb/x210/ramstage.c:
PS21:
This would usually go into `mainboard.c`. It's a convention to have one […]
Ack
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#22).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 24 files changed, 1,373 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/22
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 22:
Resolved Nico's feedback and have something that looks much nicer now - thanks! All appears to be working fine on my system.
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#23).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 24 files changed, 1,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/23
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 23:
Jenkins is failing because the EC firmware can't be found and isn't included. Is there a way to override the config for that to just point it at a dummy file? I'd rather not default the EC build to off.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 23:
(1 comment)
I think it's fine if you don't include the BLOB by default as the user will see the warning at the end of the build log.
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... File src/ec/51nb/npce985la0dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... PS23, Line 29: default y the default should be n as the EC firmware is not part of the repository
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#24).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 24 files changed, 1,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/24
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... File src/ec/51nb/npce985la0dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... PS23, Line 29: default y
the default should be n as the EC firmware is not part of the repository
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 24: Code-Review+1
(3 comments)
Looks pretty good.
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.md:
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 13: # I would suggest explaining how to flash internally using a layout/fmap, for images built without EC firmware. With that, one just needs to build coreboot without IFD/ME/GBE/EC blobs (just FSP and VBIOS, I think? probably worth explaining as well), then flash coreboot to the fmap space for it (fmap region called COREBOOT?) without overwriting what is already on the flash chip.
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... File src/ec/51nb/npce985la0dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... PS23, Line 27: images Minor: there's just one image, so this should be singular
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... PS23, Line 29: default y
Ack
Since you're using a fmap in coreboot, you can use it with flashrom to flash only to the FMAP's BIOS region, without overwriting the EC firmware. AFAIUI, it should work after the initial flash (and for the initial flash, I'd just use a layout).
However, having the option doesn't hurt.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 24: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.md:
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 1: # 51NB X210 file needs to be referenced by index.md
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 19: is located on the upper side of the motherboard, below the keyboard can you provide a picture? Note: pictures should not be bigger than 800px and use 70% compression to keep size small.
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 31: Use libgfxinit once Kaby Lake is supported. isn't that supported by now?
https://review.coreboot.org/c/coreboot/+/32531/24/src/ec/51nb/npce985la0dx/n... File src/ec/51nb/npce985la0dx/npce985la0dx.c:
https://review.coreboot.org/c/coreboot/+/32531/24/src/ec/51nb/npce985la0dx/n... PS24, Line 19: { NULL, 0x05 }, { NULL, 0x06 }, { NULL, 0x11 } what are those LDNs used for? Do you need to set additional registers in the superio space?
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#25).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,412 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/25
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 25:
(6 comments)
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.md:
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 1: # 51NB X210
file needs to be referenced by index. […]
Ack
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 13: #
I would suggest explaining how to flash internally using a layout/fmap, for images built without EC […]
Ack
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 19: is located on the upper side of the motherboard, below the keyboard
can you provide a picture? […]
Ack
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... File src/ec/51nb/npce985la0dx/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... PS23, Line 27: images
Minor: there's just one image, so this should be singular
Ack
https://review.coreboot.org/c/coreboot/+/32531/23/src/ec/51nb/npce985la0dx/K... PS23, Line 29: default y
Since you're using a fmap in coreboot, you can use it with flashrom to flash only to the FMAP's BIOS […]
Ack
https://review.coreboot.org/c/coreboot/+/32531/24/src/ec/51nb/npce985la0dx/n... File src/ec/51nb/npce985la0dx/npce985la0dx.c:
https://review.coreboot.org/c/coreboot/+/32531/24/src/ec/51nb/npce985la0dx/n... PS24, Line 19: { NULL, 0x05 }, { NULL, 0x06 }, { NULL, 0x11 }
what are those LDNs used for? Do you need to set additional registers in the superio space?
Ack
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.md:
https://review.coreboot.org/c/coreboot/+/32531/24/Documentation/mainboard/51... PS24, Line 31: Use libgfxinit once Kaby Lake is supported.
isn't that supported by now?
Not yet.
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#26).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,412 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/26
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#27).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,418 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/27
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32531
to look at the new patch set (#28).
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,418 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/28
Matthew Garrett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 28:
Added some additional devicetree config, but only other meaningful difference is a change to build the EC code by default but not include the firmware - this way it'll generate the warning during build.
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 28:
(2 comments)
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... PS28, Line 28: /* Rcomp resistor */ Null check?
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... PS28, Line 36: /* Rcomp target */ See above
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 28: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... PS28, Line 28: /* Rcomp resistor */
Null check?
Not strictly required as the function is static and called in a way that it can't be NULL
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... PS28, Line 36: /* Rcomp target */
See above
Not strictly required as the function is static and called in a way that it can't be NULL
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 28:
(3 comments)
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 12: select MAINBOARD_USES_FSP2_0 Not needed, since this is selected by the SOC
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 16: config MAINBOARD_VENDOR : string : default "51NB" Not needed, since it is set by `src/mainboard/51nb/Kconfig`
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 36: config DEVICETREE : string : default "devicetree.cb" Not needed, since this is the default name
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 28:
(3 comments)
A few nits...
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 56: config CPU_MICROCODE_CBFS_LEN : hex : default 0x18000 : : config CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0 only needed if using FSP-T, which may be discouraged if not tested.
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/bo... File src/mainboard/51nb/x210/board.fmd:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/bo... PS28, Line 12: CONSOLE@0x60200 0x20000 Afaik there is no alignment requirements on this region, but for simplicity of erasing this region it might be better to place it above the FMAP region to make it aligned to common erase blocks like 64K?
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/bo... PS28, Line 8: EC@0x0 0x10000 : RW_MRC_CACHE@0x10000 0x10000 : SMMSTORE@0x20000 0x40000 : FMAP@0x60000 0x200 : CONSOLE@0x60200 0x20000 : COREBOOT(CBFS)@0x80200 0x57FE00 You can skip specifying offsets of most of the regions and also the size of the COREBOOT region if you want.
Matt DeVillier has uploaded a new patch set (#29) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,418 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/29
Matt DeVillier has uploaded a new patch set (#30) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,404 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/30
Matt DeVillier has uploaded a new patch set (#31) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,404 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/31
Matt DeVillier has uploaded a new patch set (#32) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,404 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/32
Matt DeVillier has uploaded a new patch set (#33) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 26 files changed, 1,404 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/33
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 33:
(8 comments)
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... File src/mainboard/51nb/x210/Kconfig:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 12: select MAINBOARD_USES_FSP2_0
Not needed, since this is selected by the SOC
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 16: config MAINBOARD_VENDOR : string : default "51NB"
Not needed, since it is set by `src/mainboard/51nb/Kconfig`
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 36: config DEVICETREE : string : default "devicetree.cb"
Not needed, since this is the default name
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/Kc... PS28, Line 56: config CPU_MICROCODE_CBFS_LEN : hex : default 0x18000 : : config CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0
only needed if using FSP-T, which may be discouraged if not tested.
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/bo... File src/mainboard/51nb/x210/board.fmd:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/bo... PS28, Line 12: CONSOLE@0x60200 0x20000
Afaik there is no alignment requirements on this region, but for simplicity of erasing this region i […]
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/bo... PS28, Line 8: EC@0x0 0x10000 : RW_MRC_CACHE@0x10000 0x10000 : SMMSTORE@0x20000 0x40000 : FMAP@0x60000 0x200 : CONSOLE@0x60200 0x20000 : COREBOOT(CBFS)@0x80200 0x57FE00
You can skip specifying offsets of most of the regions and also the size of the COREBOOT region if y […]
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... PS28, Line 28: /* Rcomp resistor */
Not strictly required as the function is static and called in a way that it can't be NULL
Done
https://review.coreboot.org/c/coreboot/+/32531/28/src/mainboard/51nb/x210/ro... PS28, Line 36: /* Rcomp target */
Not strictly required as the function is static and called in a way that it can't be NULL
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 33: Code-Review+1
(19 comments)
https://review.coreboot.org/c/coreboot/+/32531/33/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.jpg:
PS33: Maybe crop this image a bit, so that it is under 50 KiB?
https://review.coreboot.org/c/coreboot/+/32531/33/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.md:
https://review.coreboot.org/c/coreboot/+/32531/33/Documentation/mainboard/51... PS33, Line 48: Use libgfxinit once Kaby Lake is supported. Done, I guess?
https://review.coreboot.org/c/coreboot/+/32531/8/src/ec/51nb/51nb.c File src/ec/51nb/51nb.c:
https://review.coreboot.org/c/coreboot/+/32531/8/src/ec/51nb/51nb.c@23 PS8, Line 23: /* Enable function 5 (PS/2 AUX) */
Some ECs have a SuperIO-like part. See ec/roda/it8518 for an example.
Ack
https://review.coreboot.org/c/coreboot/+/32531/8/src/ec/51nb/51nb.c@43 PS8, Line 43: CHIP_NAME("51NB EC")
Not sure if all the 51nb devices use the same EC. I'd suggest specifying the EC model (NPCE9... […]
Done
https://review.coreboot.org/c/coreboot/+/32531/8/src/ec/51nb/Makefile.inc File src/ec/51nb/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/32531/8/src/ec/51nb/Makefile.inc@25 PS8, Line 25: $(51NB_EC_INSERT) $(obj)/coreboot.pre \
No, vendor firmware doesn't use the IFD ec region.
Ack
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ac... File src/mainboard/51nb/x210/acpi_tables.c:
PS33: This file shouldn't be needed anymore
https://review.coreboot.org/c/coreboot/+/32531/21/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/21/src/mainboard/51nb/x210/de... PS21, Line 149: register "PcieRpEnable[2]" = "1" # Ethernet controller : register "PcieRpLtrEnable[2]" = "1"
This is not RP1?
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/de... PS33, Line 167: register "PcieRpHotPlug[3]" = "1" Hmmmmm... Why do we want hotplug for Wi-Fi only?
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/de... PS33, Line 179: webcam Please capitalize: `Webcam`
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... PS33, Line 33: // CPU This comment does not add much value. I would drop it
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... PS33, Line 43: Unnecessary blank line
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... PS33, Line 46: // Chipset specific sleep states This comment was dropped not too long ago
https://review.coreboot.org/c/coreboot/+/32531/8/src/mainboard/51nb/x210/hda... File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/32531/8/src/mainboard/51nb/x210/hda... PS8, Line 25:
Will do.
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 22: 0x0000000c 12
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 34: 0x17aa2155 This value in the comment might rot away.
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 35: 0x0 0 here and on AZALIA_PIN_CFG macros
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 39: /* Pin Complex (NID 0x19) */ I would drop these as they don't add much info.
https://review.coreboot.org/c/coreboot/+/32531/21/src/mainboard/51nb/x210/ma... File src/mainboard/51nb/x210/mainboard.c:
https://review.coreboot.org/c/coreboot/+/32531/21/src/mainboard/51nb/x210/ma... PS21, Line 53: }
This seems like Purisms idea of how to store a serial number. […]
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ro... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ro... PS33, Line 31: sizeof(RcompResistor)); Fits on the previous line
Matt DeVillier has uploaded a new patch set (#34) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 25 files changed, 1,399 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/34
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 34:
(12 comments)
https://review.coreboot.org/c/coreboot/+/32531/33/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.jpg:
PS33:
Maybe crop this image a bit, so that it is under 50 KiB?
Done
https://review.coreboot.org/c/coreboot/+/32531/33/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.md:
https://review.coreboot.org/c/coreboot/+/32531/33/Documentation/mainboard/51... PS33, Line 48: Use libgfxinit once Kaby Lake is supported.
Done, I guess?
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ac... File src/mainboard/51nb/x210/acpi_tables.c:
PS33:
This file shouldn't be needed anymore
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/de... PS33, Line 167: register "PcieRpHotPlug[3]" = "1"
Hmmmmm... […]
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/de... PS33, Line 179: webcam
Please capitalize: `Webcam`
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... PS33, Line 33: // CPU
This comment does not add much value. […]
same as every other SKL/KBL board though
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... PS33, Line 46: // Chipset specific sleep states
This comment was dropped not too long ago
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 22: 0x0000000c
12
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 34: 0x17aa2155
This value in the comment might rot away.
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 35: 0x0
0 here and on AZALIA_PIN_CFG macros
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 39: /* Pin Complex (NID 0x19) */
I would drop these as they don't add much info.
ideally someone would add which pin is what, as with other boards
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ro... File src/mainboard/51nb/x210/romstage.c:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ro... PS33, Line 31: sizeof(RcompResistor));
Fits on the previous line
Done
Matt DeVillier has uploaded a new patch set (#35) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 25 files changed, 1,398 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/35
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/ds... PS33, Line 43:
Unnecessary blank line
Done
Matt DeVillier has uploaded a new patch set (#36) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 25 files changed, 1,398 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/36
Matt DeVillier has uploaded a new patch set (#37) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/ec/51nb/npce985la0dx/Kconfig A src/ec/51nb/npce985la0dx/Makefile.inc A src/ec/51nb/npce985la0dx/npce985la0dx.c A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 25 files changed, 1,397 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/37
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 37: Code-Review+1
(11 comments)
https://review.coreboot.org/c/coreboot/+/32531/37/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.jpg:
PS37: Please put this image into https://tinyjpg.com/ for space savings of 26%
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ac... File src/mainboard/51nb/x210/acpi/battery.asl:
PS37: Is this file using spaces? The other ACPI files seem affected as well
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/bo... File src/mainboard/51nb/x210/board.fmd:
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/bo... PS37, Line 6: FLASH@0xff800000 0x800000 FLASH 8M
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... PS37, Line 59: 3 SaGv_Enabled
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... PS37, Line 98: 0x0 Just 0 (apply everywhere)
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... PS37, Line 229: nit: align the "on" keywords?
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 17: Should be making use of arch/acpi.h
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 30: global Either drop the comment, or capitalize `Global`
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 33: // CPU This comment provides little value
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 36: Scope (_SB) { : Device (PCI0) Device (_SB.PCI0)
This also solves the inconsistency of the opening braces
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 39: /* Pin Complex (NID 0x19) */
ideally someone would add which pin is what, as with other boards
Ideally, I've yet to see that happen, though... One could also use higher-level macros as well.
In any case, this can be done later, so I would remove the comments for now.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: Add support for the 51nb X210 ......................................................................
Patch Set 37:
please split adding the EC from adding the mainboard
Matt DeVillier has uploaded a new patch set (#38) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 1,265 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/38
Matt DeVillier has uploaded a new patch set (#39) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 1,265 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/39
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 39:
(11 comments)
Patch Set 37:
please split adding the EC from adding the mainboard
done
https://review.coreboot.org/c/coreboot/+/32531/37/Documentation/mainboard/51... File Documentation/mainboard/51nb/x210.jpg:
PS37:
Please put this image into https://tinyjpg. […]
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ac... File src/mainboard/51nb/x210/acpi/battery.asl:
PS37:
Is this file using spaces? The other ACPI files seem affected as well
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/bo... File src/mainboard/51nb/x210/board.fmd:
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/bo... PS37, Line 6: FLASH@0xff800000 0x800000
FLASH 8M
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... PS37, Line 59: 3
SaGv_Enabled
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... PS37, Line 98: 0x0
Just 0 (apply everywhere)
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/de... PS37, Line 229:
nit: align the "on" keywords?
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 17:
Should be making use of arch/acpi. […]
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 30: global
Either drop the comment, or capitalize `Global`
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 33: // CPU
This comment provides little value
Done
https://review.coreboot.org/c/coreboot/+/32531/37/src/mainboard/51nb/x210/ds... PS37, Line 36: Scope (_SB) { : Device (PCI0)
Device (_SB.PCI0) […]
Done
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... File src/mainboard/51nb/x210/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/32531/33/src/mainboard/51nb/x210/hd... PS33, Line 39: /* Pin Complex (NID 0x19) */
Ideally, I've yet to see that happen, though... One could also use higher-level macros as well. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 39:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32531/39/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/39/src/mainboard/51nb/x210/ds... PS39, Line 31: #include "acpi/platform.asl" Replace with: #include <soc/intel/skylake/acpi/platform.asl>
Matt DeVillier has uploaded a new patch set (#40) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 1,265 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/40
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 40: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/32531/39/src/mainboard/51nb/x210/ds... File src/mainboard/51nb/x210/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/32531/39/src/mainboard/51nb/x210/ds... PS39, Line 31: #include "acpi/platform.asl"
Replace with: #include <soc/intel/skylake/acpi/platform. […]
Unrelated
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 40:
(1 comment)
the SMI I/O Trap looks a bit suspicious to me; smells like some leftover from vendor firmware. what is that needed for and is the SMI handler for this even in place?
https://review.coreboot.org/c/coreboot/+/32531/40/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/40/src/mainboard/51nb/x210/de... PS40, Line 77: # VR Settings Configuration for 4 Domains do the voltage regulator settings need to be in the devicetree? at least for some platforms there were patches to have the defaults in the platform code
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 40:
(1 comment)
Patch Set 40:
(1 comment)
the SMI I/O Trap looks a bit suspicious to me; smells like some leftover from vendor firmware. what is that needed for and is the SMI handler for this even in place?
not sure, suspect it may be related to the Apple SMC emulation / Hackintosh support that mjg59 was also working on at the time. I can pull it, just need to find a tester to validate before merging
https://review.coreboot.org/c/coreboot/+/32531/40/src/mainboard/51nb/x210/de... File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/32531/40/src/mainboard/51nb/x210/de... PS40, Line 77: # VR Settings Configuration for 4 Domains
do the voltage regulator settings need to be in the devicetree? at least for some platforms there we […]
you're right, it's just using the defaults for KBL-R, I'll remove
Matt DeVillier has uploaded a new patch set (#41) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 1,191 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/41
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 41:
not sure, suspect it may be related to the Apple SMC emulation / Hackintosh support that mjg59 was also working on at the time. I can pull it, just need to find a tester to validate before merging
yeah, that might be the case here. i'd like to not have this in this patch, since i'm not sure if the smi handler really exists or if it just crashes/misbehaves/... if you've checked that that won't cause any issues, i'd also be ok with it still in this patch, but i'd prefer if it wasn't
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 41: Code-Review+2
Matt DeVillier has uploaded a new patch set (#42) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 1,156 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/42
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 42:
Patch Set 41:
yeah, that might be the case here. i'd like to not have this in this patch, since i'm not sure if the smi handler really exists or if it just crashes/misbehaves/... if you've checked that that won't cause any issues, i'd also be ok with it still in this patch, but i'd prefer if it wasn't
removed after discussion with mjg59 on IRC
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 42: Code-Review+2
Matt DeVillier has uploaded a new patch set (#43) to the change originally created by Matthew Garrett. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 993 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/43
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 43: Code-Review+2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
Patch Set 43: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/32531 )
Change subject: mb/51nb: Add support for the 51nb X210 ......................................................................
mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, (IFD is fully unlocked, no protected regions are set, no Bootguard), making it an ideal coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes:
* EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different
All hardware appears to work as expected, although the SD reader is untested.
Signed-off-by: Matthew Garrett mjg59@google.com Signed-off-by: Matt DeVillier matt.devillier@gmail.com Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Felix Held felix-coreboot@felixheld.de --- A Documentation/mainboard/51nb/x210.jpg A Documentation/mainboard/51nb/x210.md M Documentation/mainboard/index.md A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/battery.asl A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/board.fmd A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/romstage.c 22 files changed, 993 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/51nb/x210.jpg b/Documentation/mainboard/51nb/x210.jpg new file mode 100644 index 0000000..66fb7e3 --- /dev/null +++ b/Documentation/mainboard/51nb/x210.jpg Binary files differ diff --git a/Documentation/mainboard/51nb/x210.md b/Documentation/mainboard/51nb/x210.md new file mode 100644 index 0000000..645c3ba --- /dev/null +++ b/Documentation/mainboard/51nb/x210.md @@ -0,0 +1,45 @@ +# 51NB X210 + +## Extracting vendor EC firmware + +EC firmware is included in the SPI image. To extract it, run: + +`` +dd bs=64K skip=32 count=1 if=bios.rom of=ec.bin +`` + +and ensure that you have a file that includes the string "Insyde Software Corp" + +## Flashing instructions + +This can be performed using the internal SPI controller, even when flashing +from stock firmware. Use flashrom -p internal and follow the appropriate +flashrom instructions to force it. Alternatively, external flashing has been +tested with Dediprog SF100 and SF600 and using a Beaglebone Black. The flash +is located on the upper side of the motherboard, below the keyboard +connector. It is circled in red here: + + +## Flashing a subset of the ROM + +If you want to flash coreboot without extracting firmware blobs, you can +flash coreboot without overwriting those blobs. After building coreboot, +create a layout file with the following content: + +``` +00000000:001fffff me +00200000:0020ffff ec +00210000:007fffff main +``` + +and run flashrom with the "--layout rom.layout --image main" arguments. This +will flash the main firmware without overwriting the existing EC or ME +firmware. + +## Working + +All hardware features are believed to be working, although the SD reader is +untested. Note that certain hotkeys don't work (including the Thinkvantage +button) - this is a limitation of the EC firmware, and these keys also +generate no events under the stock vendor firmware. + diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 8cb3670..f319edb 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -2,6 +2,10 @@
This section contains documentation about coreboot on specific mainboards.
+## 51NB + +- [X210](51nb/x210.md) + ## AMD - [padmelon](amd/padmelon/padmelon.md)
diff --git a/src/mainboard/51nb/Kconfig b/src/mainboard/51nb/Kconfig new file mode 100644 index 0000000..2b3a493 --- /dev/null +++ b/src/mainboard/51nb/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. + +if VENDOR_51NB + +choice + prompt "Mainboard model" + +source "src/mainboard/51nb/*/Kconfig.name" + +endchoice + +source "src/mainboard/51nb/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "51NB" + +endif # VENDOR_51NB diff --git a/src/mainboard/51nb/Kconfig.name b/src/mainboard/51nb/Kconfig.name new file mode 100644 index 0000000..6f99514 --- /dev/null +++ b/src/mainboard/51nb/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_51NB + bool "51NB" diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig new file mode 100644 index 0000000..70b3da8 --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig @@ -0,0 +1,53 @@ +if BOARD_51NB_X210 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_51NB_NPCE985LA0DX + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_FAMILY + string + default "X210" + +config MAINBOARD_PART_NUMBER + string + default "X210" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "51nb/x210" + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,5917" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config NO_POST + default y + +endif diff --git a/src/mainboard/51nb/x210/Kconfig.name b/src/mainboard/51nb/x210/Kconfig.name new file mode 100644 index 0000000..1cae5dd --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_51NB_X210 + bool "51NB X210" diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc new file mode 100644 index 0000000..6555e99 --- /dev/null +++ b/src/mainboard/51nb/x210/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl new file mode 100644 index 0000000..9064ad5 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Device (BAT) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { _SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B1SS) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "Y91", /* 0x09: Model Number */ + "", /* 0x0a: Serial Number */ + "LION", /* 0x0b: Battery Type */ + "CJOYIN" /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, Serialized) + { + /* Design Capacity */ + Store (DGCP, Index (PBIF, 1)) + + /* Last Full Charge Capacity */ + Store (FLCP, Index (PBIF, 2)) + + /* Design Voltage */ + Store (DGVO, Index (PBIF, 4)) + + /* Design Capacity of Warning */ + Store (BDW, Index (PBIF, 5)) + + /* Design Capacity of Low */ + Store (BDL, Index (PBIF, 6)) + + Return (PBIF) + } + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + /* + * 0: BATTERY STATE + * + * bit 0 = discharging + * bit 1 = charging + * bit 2 = critical level + */ + Store (BSTS, Index (PBST, 0)) + + /* + * 1: BATTERY PRESENT RATE + */ + Store (BPR, Index (PBST, 1)) + + /* + * 2: BATTERY REMAINING CAPACITY + */ + Store (BRC, Index (PBST, 2)) + + /* + * 3: BATTERY PRESENT VOLTAGE + */ + Store (BPV, Index (PBST, 3)) + + Return (PBST) + } +} diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl new file mode 100644 index 0000000..5ebc0ac --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 0x4F) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x50), + CTMP, 8, + CFAN, 8, + B1SS, 1, + BSTS, 2, + ACIN, 1, + Offset (0x53), + BKLG, 8, + TOUP, 1, + WIRE, 1, + BLTH, 1, + LIDC, 1, + APFG, 1, + WRST, 1, + BTST, 1, + ACEB, 1, + CAME, 1, + Offset (0x60), + DGCP, 16, + FLCP, 16, + DGVO, 16, + BDW, 16, + BDL, 16, + BPR, 16, + BRC, 16, + BPV, 16 + } + + Method (_REG, 2, NotSerialized) + { + /* Initialize AC power state */ + Store (ACIN, \PWRS) + + /* Initialize LID switch state */ + Store (LIDC, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q04) + { + Notify(_SB.PCI0.GFX0.LCD, 0x86) + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q05) + { + Notify(_SB.PCI0.GFX0.LCD, 0x87) + } + + /* Battery Information Event */ + Method (_Q0C) + { + Notify (BAT, 0x81) + } + + /* AC event */ + Method (_Q0D) + { + Store (ACIN, \PWRS) + Notify (AC, 0x80) + } + + /* Lid event */ + Method (_Q0E) + { + Store (LIDC, \LIDS) + Notify (LID0, 0x80) + } + + /* Battery Information Event */ + Method (_Q13) + { + Notify (BAT, 0x81) + } + + /* Battery Status Event */ + Method (_Q14) + { + Notify (BAT, 0x80) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { _SB }) + + Method (_STA) + { + Return (0x0F) + } + Method (_PSR) + { + Return (\PWRS) + } + } + + #include "battery.asl" +} diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl new file mode 100644 index 0000000..218b957 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + Method (_DOS, 1, NotSerialized) + { + /* We never do anything in firmware, so _DOS is a noop */ + } + Method (_DOD, 0, NotSerialized) + { + return (Package (0x03) + { + 0x80000410, /* LCD */ + 0x80000120, /* VGA */ + 0x80000330 /* DP */ + }) + } + Device (LCD) + { + Method (_ADR, 0, Serialized) + { + Return (0x800000410) + } + + Method (_BCL, 0, NotSerialized) + { + Return (Package (0x12) + { + 0x0A, + 0x0F, + 0x00, + 0x01, + 0x02, + 0x03, + 0x04, + 0x05, + 0x06, + 0x07, + 0x08, + 0x09, + 0x0A, + 0x0B, + 0x0C, + 0x0D, + 0x0E, + 0x0F + }) + } + Method (_BCM, 1, NotSerialized) + { + _SB.PCI0.LPCB.EC.BKLG = Arg0 + } + Method (_BQC, 0, NotSerialized) + { + Return (_SB.PCI0.LPCB.EC.BKLG) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl new file mode 100644 index 0000000..fb389a4 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Scope (_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) + { + Return (0xF) + } + + Method (_LID) + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl new file mode 100644 index 0000000..d0e34b6 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Store(_SB.PCI0.LPCB.EC.LIDC, \LIDS) + Store(_SB.PCI0.LPCB.EC.ACIN, \PWRS) + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl new file mode 100644 index 0000000..cb77a3c --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/51nb/x210/board.fmd b/src/mainboard/51nb/x210/board.fmd new file mode 100644 index 0000000..1955a05 --- /dev/null +++ b/src/mainboard/51nb/x210/board.fmd @@ -0,0 +1,15 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the base of the BIOS region. +# + +FLASH 8M { + BIOS@0x200000 0x600000 { + EC@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + SMMSTORE@0x20000 0x40000 + CONSOLE@0x60000 0x20000 + FMAP@0x80000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/51nb/x210/board_info.txt b/src/mainboard/51nb/x210/board_info.txt new file mode 100644 index 0000000..65c4608 --- /dev/null +++ b/src/mainboard/51nb/x210/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: 51NB +Board name: Thinkpad X210 +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb new file mode 100644 index 0000000..7ee3b2c --- /dev/null +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -0,0 +1,167 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "1" + register "deep_s3_enable_dc" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[2]" = "1" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + register "PmConfigPciClockRun" = "1" + + # Enable Root Ports 3, 4 and 9 + register "PcieRpEnable[2]" = "1" # Ethernet controller + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "0" + register "PcieRpClkSrcNumber[2]" = "0" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + + register "PcieRpEnable[3]" = "1" # Wireless controller + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + + register "PcieRpEnable[8]" = "1" # NVMe controller + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/51nb/npce985la0dx + device pnp 0c09.0 on end + device pnp 4e.5 on end + device pnp 4e.6 on end + device pnp 4e.11 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl new file mode 100644 index 0000000..441a80d --- /dev/null +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + Name(\DSEN, 1) + + #include "acpi/platform.asl" + + #include <soc/intel/skylake/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + #include "acpi/graphics.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h new file mode 100644 index 0000000..3e22dde --- /dev/null +++ b/src/mainboard/51nb/x210/gpio.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +}; + +#endif + +#endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c new file mode 100644 index 0000000..973024a --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa2155, /* Subsystem ID */ + 12, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x17aa2155), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x19, 0x042140f0), + AZALIA_PIN_CFG(0, 0x1a, 0x61a190f0), + AZALIA_PIN_CFG(0, 0x1b, 0x04a190f0), + AZALIA_PIN_CFG(0, 0x1c, 0x612140f0), + AZALIA_PIN_CFG(0, 0x1d, 0x601700f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x901701f0), + AZALIA_PIN_CFG(0, 0x1B, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a601f0), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c new file mode 100644 index 0000000..4364dd1 --- /dev/null +++ b/src/mainboard/51nb/x210/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void mainboard_enable(struct device *dev) +{ + /* Route 0x4e/4f to LPC */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c new file mode 100644 index 0000000..4ef1024 --- /dev/null +++ b/src/mainboard/51nb/x210/romstage.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <string.h> +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <arch/io.h> +#include <string.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +}
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