coreboot-gerrit September 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: include/cper.h: Add max of enum
by Marshall Dawson (Code Review) 06 Sep '18

06 Sep '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28533 Change subject: include/cper.h: Add max of enum ...................................................................... include/cper.h: Add max of enum Define the maximum value of the cper_x86_check_type enum, for use later in determining a legal function argument. Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/cper.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28533/1 diff --git a/src/include/cper.h b/src/include/cper.h index 88c7cba..1604041 100644 --- a/src/include/cper.h +++ b/src/include/cper.h @@ -216,6 +216,7 @@ X86_PROCESSOR_BUS_CHK, /* X86_PROCESSOR_BUS_CHK_ERROR_GUID */ X86_PROCESSOR_MS_CHK /* X86_PROCESSOR_MS_CHK_ERROR_GUID */ }; +#define X86_PROCESSOR_CHK_MAX X86_PROCESSOR_MS_CHK /* IA32/X64 Processor Error Information Structure, Validation Bits (Tbl 256) */ #define I32X64ERRINFO_VALID_CHECK BIT(0) -- To view, visit https://review.coreboot.org/28533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f Gerrit-Change-Number: 28533 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: qemu-q35: Use the TSC for udelay
by Philipp Deppenwiese (Code Review) 06 Sep '18

06 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28526 ) Change subject: qemu-q35: Use the TSC for udelay ...................................................................... qemu-q35: Use the TSC for udelay Use the TSC for delays on q35, ensuring that the TSC delay code is included in the correct stages when selected. Tested on qemu-35 and wedge-100s (for no regressions). Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed Signed-off-by: Michael van der Westhuizen <rmikey(a)fb.com> Reviewed-on: https://review.coreboot.org/28526 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ea2bc46..ab8e1a9 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,3 +20,4 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP + select UDELAY_TSC diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index b5f8369..288eea6 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -16,3 +16,4 @@ subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic subdirs-y += ../x86/smm +subdirs-y += ../x86/tsc -- To view, visit https://review.coreboot.org/28526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed Gerrit-Change-Number: 28526 Gerrit-PatchSet: 2 Gerrit-Owner: Michael van der Westhuizen (1002100) Gerrit-Reviewer: Michael van der Westhuizen (1002100) Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com>

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Change in coreboot[master]: qemu-q35: Use the TSC for udelay
by Philipp Deppenwiese (Code Review) 06 Sep '18

06 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28526 ) Change subject: qemu-q35: Use the TSC for udelay ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed Gerrit-Change-Number: 28526 Gerrit-PatchSet: 1 Gerrit-Owner: Michael van der Westhuizen (1002100) Gerrit-Reviewer: Michael van der Westhuizen (1002100) Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Sep 2018 16:31:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: fsp_broadwell_de: enable spi console
by Philipp Deppenwiese (Code Review) 06 Sep '18

06 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28528 ) Change subject: fsp_broadwell_de: enable spi console ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/28528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Gerrit-Change-Number: 28528 Gerrit-PatchSet: 3 Gerrit-Owner: Okash Khawaja <okash.khawaja(a)gmail.com> Gerrit-Reviewer: Okash Khawaja <okash.khawaja(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Sep 2018 16:30:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: wedge100s: enable mrc cache in fmap
by Philipp Deppenwiese (Code Review) 06 Sep '18

06 Sep '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28527 ) Change subject: wedge100s: enable mrc cache in fmap ...................................................................... wedge100s: enable mrc cache in fmap this enables mrc cache in fmap for wedge100s and always enable it in Kconfig. Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Signed-off-by: Okash Khawaja <okash.khawaja(a)gmail.com> Reviewed-on: https://review.coreboot.org/28527 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/board.fmd 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 6a33edb..56bd2bb 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -11,6 +11,8 @@ select SERIRQ_CONTINUOUS_MODE select SUPERIO_ITE_COMMON_ROMSTAGE select FSP_EHCI1_ENABLE + select MRC_CACHE_FMAP + select ENABLE_FSP_FAST_BOOT config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/wedge100s/board.fmd b/src/mainboard/ocp/wedge100s/board.fmd index e89b2aa..da6e3e3 100644 --- a/src/mainboard/ocp/wedge100s/board.fmd +++ b/src/mainboard/ocp/wedge100s/board.fmd @@ -20,6 +20,7 @@ # specifically look for RO_VPD. RO_VPD@0x0 0x1000 } - COREBOOT(CBFS)@0x10000 0x7f0000 + RW_MRC_CACHE@0x10000 0x10000 + COREBOOT(CBFS)@0x20000 0x7e0000 } } -- To view, visit https://review.coreboot.org/28527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Gerrit-Change-Number: 28527 Gerrit-PatchSet: 5 Gerrit-Owner: Okash Khawaja <okash.khawaja(a)gmail.com> Gerrit-Reviewer: Okash Khawaja <okash.khawaja(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>

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Change in coreboot[master]: wedge100s: enable mrc cache in fmap
by Philipp Deppenwiese (Code Review) 06 Sep '18

06 Sep '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28527 ) Change subject: wedge100s: enable mrc cache in fmap ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/28527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Gerrit-Change-Number: 28527 Gerrit-PatchSet: 4 Gerrit-Owner: Okash Khawaja <okash.khawaja(a)gmail.com> Gerrit-Reviewer: Okash Khawaja <okash.khawaja(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 06 Sep 2018 16:30:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: smmstore: Add a key/val store facility in flash, mediated through SMM
by build bot (Jenkins) (Code Review) 06 Sep '18

06 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25182 ) Change subject: smmstore: Add a key/val store facility in flash, mediated through SMM ...................................................................... Patch Set 12: (5 comments) https://review.coreboot.org/#/c/25182/12/src/drivers/smmstore/store.c File src/drivers/smmstore/store.c: https://review.coreboot.org/#/c/25182/12/src/drivers/smmstore/store.c@180 PS12, Line 180: if (rdev_writeat(&store, &key_sz, end, 4) != 4) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/12/src/drivers/smmstore/store.c@184 PS12, Line 184: if (rdev_writeat(&store, &value_sz, end, 4) != 4) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/12/src/drivers/smmstore/store.c@188 PS12, Line 188: if (rdev_writeat(&store, key, end, key_sz) != key_sz) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/12/src/drivers/smmstore/store.c@192 PS12, Line 192: if (rdev_writeat(&store, value, end, value_sz) != value_sz) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/12/src/drivers/smmstore/store.c@197 PS12, Line 197: if (rdev_writeat(&store, &nul, end, 1) != 1) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/25182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5 Gerrit-Change-Number: 25182 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 06 Sep 2018 16:23:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboards: Add SMMSTORE region in chromeos configs
by Patrick Georgi (Code Review) 06 Sep '18

06 Sep '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/28532 Change subject: mainboards: Add SMMSTORE region in chromeos configs ...................................................................... mainboards: Add SMMSTORE region in chromeos configs Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/auron/chromeos.fmd M src/mainboard/google/beltino/chromeos.fmd M src/mainboard/google/butterfly/chromeos.fmd M src/mainboard/google/cyan/chromeos.fmd M src/mainboard/google/eve/chromeos.fmd M src/mainboard/google/fizz/chromeos.fmd M src/mainboard/google/glados/chromeos.fmd M src/mainboard/google/jecht/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/kukui/chromeos.fmd M src/mainboard/google/link/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/parrot/chromeos.fmd M src/mainboard/google/poppy/chromeos.fmd M src/mainboard/google/rambi/chromeos.fmd M src/mainboard/google/reef/chromeos.fmd M src/mainboard/google/slippy/chromeos.fmd M src/mainboard/google/stout/chromeos.fmd M src/mainboard/google/zoombini/chromeos.fmd M src/mainboard/intel/cannonlake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos.fmd M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/galileo/vboot.fmd M src/mainboard/intel/glkrvp/chromeos.fmd M src/mainboard/intel/kblrvp/chromeos.fmd M src/mainboard/intel/kunimitsu/chromeos.fmd M src/mainboard/intel/strago/chromeos.fmd 27 files changed, 54 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28532/1 diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/google/auron/chromeos.fmd +++ b/src/mainboard/google/auron/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/google/beltino/chromeos.fmd +++ b/src/mainboard/google/beltino/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd index 0071533..14c91d7 100644 --- a/src/mainboard/google/butterfly/chromeos.fmd +++ b/src/mainboard/google/butterfly/chromeos.fmd @@ -23,7 +23,8 @@ RW_ENVIRONMENT@0x1f8000 0x4000 RW_VPD@0x1fc000 0x2000 RW_UNUSED@0x1fe000 0x2000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index bdadcf7..145fc7b 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -27,7 +27,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x800000 0x200000 + SMMSTORE@0x800000 0x40000 + RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd index bdadcf7..145fc7b 100644 --- a/src/mainboard/google/fizz/chromeos.fmd +++ b/src/mainboard/google/fizz/chromeos.fmd @@ -27,7 +27,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x800000 0x200000 + SMMSTORE@0x800000 0x40000 + RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd index 58b6127..78c6ab1 100644 --- a/src/mainboard/google/glados/chromeos.fmd +++ b/src/mainboard/google/glados/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x7f8000 0x2000 RW_NVRAM@0x7fa000 0x6000 - RW_LEGACY(CBFS)@0x800000 0x200000 + SMMSTORE@0x800000 0x40000 + RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/google/jecht/chromeos.fmd +++ b/src/mainboard/google/jecht/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index 336aced..f84ed01 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -24,7 +24,8 @@ RW_VPD@0x465000 0x2000 RW_NVRAM@0x467000 0x5000 RW_UNUSED@0x46C000 0x14000 - RW_LEGACY@0x480000 0x780000 + SMMSTORE@0x480000 0x20000 + RW_LEGACY@0x4a0000 0x760000 WP_RO@0xC00000 0x400000 { RO_VPD@0x0 0x4000 diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index a521b0c..1602f80 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -25,5 +25,6 @@ RW_FWID_B@0x77f00 0x100 } RW_VPD@0x2f8000 0x8000 - RW_LEGACY(CBFS)@0x300000 0x100000 + SMMSTORE@0x300000 0x20000 + RW_LEGACY(CBFS)@0x320000 0xe0000 } diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd index 113fba6..8a06dc2 100644 --- a/src/mainboard/google/link/chromeos.fmd +++ b/src/mainboard/google/link/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 5572930..f601adc 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -36,7 +36,8 @@ FW_MAIN_B(CBFS)@0x10000 0x46ffc0 RW_FWID_B@0x47ffc0 0x40 } - RW_LEGACY(CBFS)@0xd30000 0x200000 + SMMSTORE@0xd30000 0x40000 + RW_LEGACY(CBFS)@0xd70000 0x1c0000 BIOS_UNUSABLE@0xf30000 0x4f000 DEVICE_EXTENSION@0xf7f000 0x80000 # Currently, it is required that the BIOS region be a multiple of 8KiB. diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd index 524399b..5f98229 100644 --- a/src/mainboard/google/parrot/chromeos.fmd +++ b/src/mainboard/google/parrot/chromeos.fmd @@ -23,7 +23,8 @@ RW_ENVIRONMENT@0x1f8000 0x4000 RW_VPD@0x1fc000 0x2000 RW_UNUSED@0x1fe000 0x2000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index bdadcf7..145fc7b 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -27,7 +27,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x800000 0x200000 + SMMSTORE@0x800000 0x40000 + RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/google/rambi/chromeos.fmd +++ b/src/mainboard/google/rambi/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index e5cda78..768d322 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -37,7 +37,8 @@ FW_MAIN_B(CBFS)@0x10000 0x46ffc0 RW_FWID_B@0x47ffc0 0x40 } - RW_LEGACY(CBFS)@0xd30000 0x200000 + SMMSTORE@0xd30000 0x40000 + RW_LEGACY(CBFS)@0xd70000 0x1c0000 BIOS_UNUSABLE@0xf30000 0x4f000 DEVICE_EXTENSION@0xf7f000 0x80000 # Currently, it is required that the BIOS region be a multiple of 8KiB. diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/google/slippy/chromeos.fmd +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd index 0071533..14c91d7 100644 --- a/src/mainboard/google/stout/chromeos.fmd +++ b/src/mainboard/google/stout/chromeos.fmd @@ -23,7 +23,8 @@ RW_ENVIRONMENT@0x1f8000 0x4000 RW_VPD@0x1fc000 0x2000 RW_UNUSED@0x1fe000 0x2000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/google/zoombini/chromeos.fmd b/src/mainboard/google/zoombini/chromeos.fmd index 4e23bbf..7123a5f 100644 --- a/src/mainboard/google/zoombini/chromeos.fmd +++ b/src/mainboard/google/zoombini/chromeos.fmd @@ -27,7 +27,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x700000 0x200000 + SMMSTORE@0x700000 0x40000 + RW_LEGACY(CBFS)@0x740000 0x1c0000 WP_RO@0x900000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd index cca80ab..65d22c3 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.fmd @@ -28,7 +28,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x700000 0x200000 + SMMSTORE@0x700000 0x40000 + RW_LEGACY(CBFS)@0x740000 0x1c0000 WP_RO@0x900000 0x380000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index cca80ab..65d22c3 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -28,7 +28,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x700000 0x200000 + SMMSTORE@0x700000 0x40000 + RW_LEGACY(CBFS)@0x740000 0x1c0000 WP_RO@0x900000 0x380000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index be6bfc0..bfbd304 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -28,7 +28,8 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x200000 + SMMSTORE@0x5d0000 0x40000 + RW_LEGACY(CBFS)@0x610000 0x1c0000 WP_RO@0x7d0000 0x430000 { RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd index 55e41e56..efc4a75 100644 --- a/src/mainboard/intel/galileo/vboot.fmd +++ b/src/mainboard/intel/galileo/vboot.fmd @@ -36,7 +36,8 @@ } RW_VPD@0x1f8000 0x2000 RW_NVRAM@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/glkrvp/chromeos.fmd b/src/mainboard/intel/glkrvp/chromeos.fmd index 84808ab..e513f7c 100644 --- a/src/mainboard/intel/glkrvp/chromeos.fmd +++ b/src/mainboard/intel/glkrvp/chromeos.fmd @@ -38,7 +38,8 @@ RW_FWID_B@0x4777c0 0x40 } RW_NVRAM@0xd39000 0x6000 - RW_LEGACY(CBFS)@0xd3f000 0x200000 + SMMSTORE@0xd40000 0x40000 + RW_LEGACY(CBFS)@0xd80000 0x1b0000 BIOS_UNUSABLE@0xf3f000 0x40000 DEVICE_EXTENSION@0xf7f000 0x80000 # Currently, it is required that the BIOS region be a multiple of 8KiB. diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd index 58b6127..78c6ab1 100644 --- a/src/mainboard/intel/kblrvp/chromeos.fmd +++ b/src/mainboard/intel/kblrvp/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x7f8000 0x2000 RW_NVRAM@0x7fa000 0x6000 - RW_LEGACY(CBFS)@0x800000 0x200000 + SMMSTORE@0x800000 0x40000 + RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/kunimitsu/chromeos.fmd b/src/mainboard/intel/kunimitsu/chromeos.fmd index 58b6127..78c6ab1 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.fmd +++ b/src/mainboard/intel/kunimitsu/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x7f8000 0x2000 RW_NVRAM@0x7fa000 0x6000 - RW_LEGACY(CBFS)@0x800000 0x200000 + SMMSTORE@0x800000 0x40000 + RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/strago/chromeos.fmd b/src/mainboard/intel/strago/chromeos.fmd index 0c05ce9..215247f 100644 --- a/src/mainboard/intel/strago/chromeos.fmd +++ b/src/mainboard/intel/strago/chromeos.fmd @@ -22,7 +22,8 @@ } RW_VPD@0x1f8000 0x2000 RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 + SMMSTORE@0x200000 0x40000 + RW_LEGACY(CBFS)@0x240000 0x1c0000 WP_RO@0x400000 0x200000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 -- To view, visit https://review.coreboot.org/28532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I12addb137604f003d1296f34f555dae219330b18 Gerrit-Change-Number: 28532 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Change in coreboot[master]: mb/google/octopus/variants/fleex: Update DPTF parameters
by Sumeet R Pawnikar (Code Review) 06 Sep '18

06 Sep '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28530 Change subject: mb/google/octopus/variants/fleex: Update DPTF parameters ...................................................................... mb/google/octopus/variants/fleex: Update DPTF parameters Update Power Limit1 and Power Limit2 values along with stepsize. Correct the charger effect for Temperature sensor2. Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28530/1 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl index a60ad1c..d72b4d0 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl @@ -39,14 +39,14 @@ Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 500, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, #ifdef DPTF_ENABLE_CHARGER /* Charger Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 500, 10, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, #endif }) @@ -56,18 +56,18 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 4500, /* PowerLimitMaximum */ + 10000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ - 500 /* StepSize */ + 200 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ + 10000, /* PowerLimitMinimum */ 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ - 500 /* StepSize */ + 1000 /* StepSize */ } }) -- To view, visit https://review.coreboot.org/28530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716 Gerrit-Change-Number: 28530 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

1 0

Change in coreboot[master]: wedge100s: Add TPM support
by Mikołaj Walczak (Code Review) 06 Sep '18

06 Sep '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28529 to look at the new patch set (#3). Change subject: wedge100s: Add TPM support ...................................................................... wedge100s: Add TPM support Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81 Signed-off-by: Mikolaj Walczak <mwalczak(a)fb.com> --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/28529/3 -- To view, visit https://review.coreboot.org/28529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81 Gerrit-Change-Number: 28529 Gerrit-PatchSet: 3 Gerrit-Owner: Mikołaj Walczak (1002108) Gerrit-Assignee: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrea Barberio <insomniac(a)slackware.it>

1 0

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coreboot-gerrit September 2018