coreboot-gerrit September 2018

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Change in coreboot[master]: mainboard/google/poppy/variants/rammus: Enable DA7219
by Furquan Shaikh (Code Review) 07 Sep '18

07 Sep '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28537 ) Change subject: mainboard/google/poppy/variants/rammus: Enable DA7219 ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28537/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28537/1//COMMIT_MSG@13 PS1, Line 13: Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 No Signed-off-by line. https://review.coreboot.org/#/c/28537/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/rammus/devicetree.cb: https://review.coreboot.org/#/c/28537/1/src/mainboard/google/poppy/variants… PS1, Line 295: Please use tabs instead of spaces like other entries in this file. Applies to all the lines below as well. -- To view, visit https://review.coreboot.org/28537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Gerrit-Change-Number: 28537 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 07 Sep 2018 06:28:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by build bot (Jenkins) (Code Review) 07 Sep '18

07 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27358 ) Change subject: riscv: temporarily block multiple-threads ...................................................................... Patch Set 21: (2 comments) https://review.coreboot.org/#/c/27358/21/src/arch/riscv/include/arch/smp/sm… File src/arch/riscv/include/arch/smp/smp.h: https://review.coreboot.org/#/c/27358/21/src/arch/riscv/include/arch/smp/sm… PS21, Line 36: static inline void SMP_SYNC() Bad function definition - void SMP_SYNC() should probably be void SMP_SYNC(void) https://review.coreboot.org/#/c/27358/21/src/arch/riscv/include/arch/smp/sm… PS21, Line 42: } while(atomic_read(&counter) < CONFIG_HART_NUM); space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/27358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia0eeed51e0952c66a9a9f25a90105fe471ffa70e Gerrit-Change-Number: 27358 Gerrit-PatchSet: 21 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 07 Sep 2018 05:58:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/poppy/variants/rammus: Enable DA7219
by Marx Wang (Code Review) 07 Sep '18

07 Sep '18

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/28537 Change subject: mainboard/google/poppy/variants/rammus: Enable DA7219 ...................................................................... mainboard/google/poppy/variants/rammus: Enable DA7219 On rammus, headset uses DA7219 so that we need to enable it. TEST=to check in kernel to see if DA7219 is up. Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 --- M src/mainboard/google/poppy/variants/rammus/devicetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28537/1 diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 0e8ce4d..21e96a3 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -292,6 +292,23 @@ register "name" = ""MAXL"" device i2c 3A on end end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1A on end + end end # I2C #5 device pci 19.2 off end # I2C #4 device pci 1c.0 on -- To view, visit https://review.coreboot.org/28537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Gerrit-Change-Number: 28537 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: add memory parts
by Ren Kuo (Code Review) 07 Sep '18

07 Sep '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/28536 ) Change subject: mb/google/poppy/variants/nami: add memory parts ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Gerrit-Change-Number: 28536 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 Sep 2018 05:42:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: add memory parts
by Ren Kuo (Code Review) 07 Sep '18

07 Sep '18

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/28536 Change subject: mb/google/poppy/variants/nami: add memory parts ...................................................................... mb/google/poppy/variants/nami: add memory parts add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a --- A src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex A src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex M src/mainboard/google/poppy/variants/nami/Makefile.inc 3 files changed, 68 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28536/1 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex new file mode 100644 index 0000000..2b461d0 --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5ANAG6NCMR-VKC +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 +4E 43 4D 52 2D 56 4B 43 20 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex new file mode 100644 index 0000000..231598b --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex @@ -0,0 +1,33 @@ +# MT40A1G16KNR-075:E +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 60 8D +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 8fc0264..b02b7d4 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -6,7 +6,7 @@ SPD_SOURCES += samsung_dimm_K4A8G165WB-BCRC # 0b0010 SPD_SOURCES += hynix_dimm_H5AN4G6NBJR-UHC # 0b0011 SPD_SOURCES += hynix_dimm_H5ANAG6NAMR-UHC # 0b0100 -SPD_SOURCES += empty_ddr4 # 0b0101 +SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b0101 SPD_SOURCES += hynix_dimm_H5AN8G6NAFR-UHC # 0b0110 SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000 @@ -14,7 +14,7 @@ SPD_SOURCES += empty_ddr4 # 0b1010 SPD_SOURCES += empty_ddr4 # 0b1011 SPD_SOURCES += empty_ddr4 # 0b1100 -SPD_SOURCES += empty_ddr4 # 0b1101 +SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101 SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b1110 SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b1111 -- To view, visit https://review.coreboot.org/28536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Gerrit-Change-Number: 28536 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: mb/google/poppy/variants/atlas: enable NVMe
by Caveh Jalali (Code Review) 07 Sep '18

07 Sep '18

Hello caveh jalali, I'd like you to do a code review. Please visit https://review.coreboot.org/28535 to review the following change. Change subject: mb/google/poppy/variants/atlas: enable NVMe ...................................................................... mb/google/poppy/variants/atlas: enable NVMe This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/atlas/gpio.c 2 files changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28535/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index c96081c..968faef 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -147,7 +147,7 @@ .dc_loadline = 441, }" - # PCIe Root port 1 with SRCCLKREQ1# + # PCIe Root port 1 with SRCCLKREQ1# (WLAN) register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" @@ -155,6 +155,20 @@ register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" + # PCIe Root port 5 (NVMe) + # PcieRpEnable: Enable root port + # PcieRpClkReqSupport: Enable CLKREQ# + # PcieRpClkReqNumber: Uses SRCCLKREQ4# + # PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4 + # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting + # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty @@ -329,7 +343,7 @@ device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.4 on end # PCI Express Port 5 (NVMe) device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 5f1a1f5..f82976e 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -78,8 +78,8 @@ PAD_CFG_NC(GPP_B7), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), - /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + /* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : SRCCLKREQ5# ==> NC */ PAD_CFG_NC(GPP_B10), /* B11 : EXT_PWR_GATE# ==> NC */ -- To view, visit https://review.coreboot.org/28535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Gerrit-Change-Number: 28535 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: soc/amd/common/block/psp/psp.c: Remove use of PspBaseLib
by build bot (Jenkins) (Code Review) 06 Sep '18

06 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27619 ) Change subject: soc/amd/common/block/psp/psp.c: Remove use of PspBaseLib ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/27619/7/src/soc/amd/common/block/psp/psp.c File src/soc/amd/common/block/psp/psp.c: https://review.coreboot.org/#/c/27619/7/src/soc/amd/common/block/psp/psp.c@… PS7, Line 93: value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG); line over 80 characters -- To view, visit https://review.coreboot.org/27619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a Gerrit-Change-Number: 27619 Gerrit-PatchSet: 7 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)se-eng.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 06 Sep 2018 21:01:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: NOT_FOR_MERGE: Add code to dump BERT region contents
by build bot (Jenkins) (Code Review) 06 Sep '18

06 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28480 ) Change subject: NOT_FOR_MERGE: Add code to dump BERT region contents ...................................................................... Patch Set 4: (150 comments) https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c File src/soc/amd/stoneyridge/bertdump.c: https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 46: static const char *acpi_severity[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 65: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 68: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 71: check & X86_PROC_CHK_OPERATION_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 74: check & X86_PROC_CHK_LEVEL_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 76: printk(0, " e Context Corrupt = %x %s\n", !!(check & X86_PROC_CHK_CTX_CORRUPT), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 77: check & X86_PROC_CHK_CONTEXT_CORPT_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 79: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 80: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 82: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 83: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 85: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 86: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 88: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 89: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 92: check & X86_PROC_CHK_PART_TYPE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 94: printk(0, " e Time Out = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 95: check & X86_PROC_CHK_TIMEOUT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 98: check & X86_PROC_CHK_ADDR_SPACE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 104: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 107: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 109: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_MS_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 110: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 112: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_MS_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 113: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 115: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_MS_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 116: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 118: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_MS_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 119: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 122: static const char *check_guid_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 147: printk(0, " ___ CPER IA32/x64 Processor Error (Check) Information @0x%p - 0x%p (size 0x%zx) ___\n", err, err + 1, sizeof(*err)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 148: printk(0, " e Structure Type GUID = %s\n", check_guid_name(err->type)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 151: printk(0, " e Validation Bits = %llx\n", err->validation); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 153: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 154: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 155: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 156: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 158: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 159: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 160: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 161: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 163: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 164: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 165: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 166: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 167: | X86_PROC_CHK_PART_TYPE_VALID | X86_PROC_CHK_TIMEOUT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 168: | X86_PROC_CHK_ADDR_SPACE_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 170: x86_mschkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 171: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 172: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 179: static const char *context_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 210: printk(0, " ___ CPER IA32/x64 Processor Context Information @0x%p - 0x%p (size 0x%zx) ___\n", ctx, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 211: (u8 *)ctx + ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 212: ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 213: printk(0, " t Context Type = %x %s\n", ctx->type, context_name(ctx->type)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 214: printk(0, " t Array Size = %x\n", ctx->array_size); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 216: printk(0, " t MM Address = %llx\n", ctx->mmap_addr); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 224: printk(0, " t %08x_%08x\n", (u32)(*(array + i) >> 32), (u32)*(array + i)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 233: int errs = (ia32->validation & I32X64SEC_VALID_ERRNUM_MASK) >> I32X64SEC_VALID_ERRNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 234: int ctxs = (ia32->validation & I32X64SEC_VALID_CTXNUM_MASK) >> I32X64SEC_VALID_CTXNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 236: printk(0, " ___ CPER IA32/x64 Processor Error @0x%p sizeof(proc error section struct) is 0x%zx/%zd) ___\n", ia32, sizeof(*ia32), sizeof(*ia32)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 237: printk(0, " x Validation Bits = %llx\n", ia32->validation); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 240: printk(0, " x Processor APIC ID = %llx %s\n", ia32->apicid, ia32->validation & I32X64SEC_VALID_LAPIC ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 241: printk(0, " x Processor CPUID = EAX = %x %s\n", (u32)ia32->cpuid[0], ia32->validation & I32X64SEC_VALID_CPUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 242: printk(0, " x EBX = %x\n", (u32)ia32->cpuid[1]); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 243: printk(0, " x ECX = %x\n", (u32)ia32->cpuid[2]); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 244: printk(0, " x EDX = %x\n", (u32)ia32->cpuid[3]); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 248: adder += parse_x86_error_info((cper_ia32x64_proc_error_info_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 251: adder += parse_x86_context_info((cper_ia32x64_context_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 256: static size_t parse_cper_structure_generic(cper_proc_generic_error_section_t *gen) line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 258: printk(0, " ___ CPER Generic Processor Error @0x%p sizeof(generic error struct) is 0x%zx/%zd\n", gen, sizeof(*gen), sizeof(*gen)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 259: printk(0, " c Validation Bits = %llx\n", gen->validation); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 260: printk(0, " c Processor Type = %x %s\n", gen->proc_type, gen->validation & GENPROC_VALID_PROC_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 261: printk(0, " c Processor ISA = %x %s\n", gen->proc_isa, gen->validation & GENPROC_VALID_PROC_ISA ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 262: printk(0, " c Processor Error Type = %x %s\n", gen->error_type, gen->validation & GENPROC_VALID_PROC_ERR_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 263: printk(0, " c Operation = %x %s\n", gen->operation, gen->validation & GENPROC_VALID_OPERATION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 264: printk(0, " c Flags = %x %s\n", gen->flags, gen->validation & GENPROC_VALID_FLAGS ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 265: printk(0, " c Level = %x %s\n", gen->level, gen->validation & GENPROC_VALID_LEVEL ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 266: printk(0, " c CPU Version Info = %llx %s\n", gen->cpu_version, gen->validation & GENPROC_VALID_CPU_VERSION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 267: printk(0, " c CPU Brand String = %s %s\n", gen->cpu_brand_string, gen->validation & GENPROC_VALID_CPU_BRAND ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 268: printk(0, " c Processor ID = %llx %s\n", gen->proc_id, gen->validation & GENPROC_VALID_CPU_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 269: printk(0, " c Target Address = %llx %s\n", gen->target_addr, gen->validation & GENPROC_VALID_TGT_ADDR ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 270: printk(0, " c Requestor Identifier = %llx %s\n", gen->requestor_id, gen->validation & GENPROC_VALID_REQR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 271: printk(0, " c Responder Identifier = %llx %s\n", gen->responder_id, gen->validation & GENPROC_VALID_RSPR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 272: printk(0, " c Instruction IP = %llx %s\n", gen->instruction_ip, gen->validation & GENPROC_VALID_INSTR_IP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 296: return sizeof(acpi_hest_generic_data_v300_t) + entry->data_length; line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 301: static const char *guids382[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 319: if(!guidcmp(&guid, &CPER_SEC_PROC_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 321: if(!guidcmp(&guid, &CPER_SEC_PROC_IA32X64_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 323: if(!guidcmp(&guid, &CPER_SEC_PROC_ARM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 325: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 327: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM2_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 329: if(!guidcmp(&guid, &CPER_SEC_PCIE_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 331: if(!guidcmp(&guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 333: if(!guidcmp(&guid, &CPER_SEC_PCI_X_BUS_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 335: if(!guidcmp(&guid, &CPER_SEC_PCI_DEV_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 337: if(!guidcmp(&guid, &CPER_SEC_DMAR_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 339: if(!guidcmp(&guid, &CPER_SEC_DMAR_VT_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 341: if(!guidcmp(&guid, &CPER_SEC_DMAR_IOMMU_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 351: printk(0, " ___ 382 found @0x%p sizeof(%s) = 0x%zx/%zd ___\n", entry, entry->revision == 0x300 ? "v3" : "old-type", line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 352: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t), line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 353: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 354: printk(0, " 3 Section Type GUID = %s\n", guid382_name(entry->section_type)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 357: printk(0, " 3 Severity = %x: %s\n", entry->error_severity, acpi_sev(entry->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 358: printk(0, " 3 Revision = %x\n", entry->revision); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 359: printk(0, " 3 Validation = %x\n", entry->validation_bits); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 361: printk(0, " 3 Error Data Length = %x\n", entry->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 362: printk(0, " 3 FRU ID = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 363: printk(0, " 3 FRU text = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID_TEXT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 365: /* I can cheat on x300 because I know only diff is timestamp */ line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 370: entry->timestamp.hour, entry->timestamp.min, entry->timestamp.sec, line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 371: entry->validation_bits & ACPI_GENERROR_VALID_TIMESTAMP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 375: /* each table-382 entry should contain 0 or 1 cper structure at its end */ line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 378: parse_cper_structure((void *)(entry + 1), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 380: parse_cper_structure((void *)((u8 *)entry + sizeof(acpi_hest_generic_data_t)), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 384: entry = (acpi_hest_generic_data_v300_t *)((u8 *)entry + entry382_size(entry)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 400: static acpi_hest_generic_data_v300_t *ptr382_from_bert_entry(acpi_generic_error_status_t *bert_data) line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 403: return (acpi_hest_generic_data_v300_t *)((u8 *)bert_data + sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 429: printk(0, "***** BERT storage at 0x%p - 0x%p (%zd) *****\n", bert_base, (u8 *)bert_base + size, size); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 431: while(offset < size) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 432: entries = (bert_data->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) >> GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 433: printk(0, " ___ BERT entry @0x%p - (sizeof(status)=0x%zx/%zd) ___\n", bert_data, sizeof(*bert_data), sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 434: printk(0, " b Block Status = %x\n", bert_data->block_status); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 436: bert_data->block_status & BIT(0) ? " uncorrectable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 437: bert_data->block_status & BIT(1) ? " correctable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 438: bert_data->block_status & BIT(2) ? " mult-uncorrected" : "", line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 439: bert_data->block_status & BIT(3) ? " mult-corrected" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 441: printk(0, " b Raw Data Offset = %x\n", bert_data->raw_data_offset); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 442: printk(0, " b Raw Data Length = %x\n", bert_data->raw_data_length); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 443: printk(0, " b Data Length = %x\n", bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 444: printk(0, " b Error Severity = %x: %s\n", bert_data->error_severity, acpi_sev(bert_data->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 445: if (bert_data->data_length && bert_data->data_length < sizeof(acpi_hest_generic_data_v300_t)) line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 447: bert_data->data_length, sizeof(acpi_hest_generic_data_v300_t)); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 448: if (bert_data->raw_data_length && bert_data->raw_data_offset < sizeof(*bert_data) + bert_data->data_length) line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 450: bert_data->raw_data_offset, sizeof(*bert_data), bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 453: /* can have zero or more data entries, of type 382 and/or of raw */ line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 454: gen382 = ptr382_from_bert_entry(bert_data); // todo: this only handles a single 382 entry line over 80 characters https://review.coreboot.org/#/c/28480/4/src/soc/amd/stoneyridge/bertdump.c@… PS4, Line 463: bert_data = (acpi_generic_error_status_t *)((u8 *)bert_data + offset); line over 80 characters -- To view, visit https://review.coreboot.org/28480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ecf920499a662db34a332e9df05e4ee2383b6d4 Gerrit-Change-Number: 28480 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Sep 2018 19:23:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: include/cper.h: Add max of enum
by Martin Roth (Code Review) 06 Sep '18

06 Sep '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28533 ) Change subject: include/cper.h: Add max of enum ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f Gerrit-Change-Number: 28533 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 06 Sep 2018 18:27:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: NOT_FOR_MERGE: Add code to dump BERT region contents
by build bot (Jenkins) (Code Review) 06 Sep '18

06 Sep '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28480 ) Change subject: NOT_FOR_MERGE: Add code to dump BERT region contents ...................................................................... Patch Set 3: (150 comments) https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c File src/soc/amd/stoneyridge/bertdump.c: https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 46: static const char *acpi_severity[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 65: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 67: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_CHK_XACT_MASK >> X86_PROC_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 68: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 70: printk(0, " e Operation = %llx %s\n", check & X86_PROC_CHK_OPER_MASK >> X86_PROC_CHK_OPER_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 71: check & X86_PROC_CHK_OPERATION_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 73: printk(0, " e Cache Level = %llx %s\n", check & X86_PROC_CHK_LEVEL_MASK >> X86_PROC_CHK_LEVEL_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 74: check & X86_PROC_CHK_LEVEL_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 76: printk(0, " e Context Corrupt = %x %s\n", !!(check & X86_PROC_CHK_CTX_CORRUPT), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 77: check & X86_PROC_CHK_CONTEXT_CORPT_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 79: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 80: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 82: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 83: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 85: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 86: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 88: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 89: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 91: printk(0, " e Participation Type = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 92: check & X86_PROC_CHK_PART_TYPE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 94: printk(0, " e Time Out = %x %s\n", !!(check & X86_PROC_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 95: check & X86_PROC_CHK_TIMEOUT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 97: printk(0, " e Address Space = %llx %s\n", check & X86_PROC_CHK_PARTIC_MASK >> X86_PROC_CHK_PARTIC_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 98: check & X86_PROC_CHK_ADDR_SPACE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 104: printk(0, " e * Invalid bits %llx\n", check & ~valid); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 106: printk(0, " e Transaction Type = %llx %s\n", check & X86_PROC_MS_CHK_XACT_MASK >> X86_PROC_MS_CHK_XACT_SH, Possible precedence defect with mask then right shift - may need parentheses https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 107: check & X86_PROC_CHK_XACT_MASK ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 109: printk(0, " e Uncorrected = %x %s\n", !!(check & X86_PROC_MS_CHK_UNCORRECTED), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 110: check & X86_PROC_CHK_UNCORRECTED_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 112: printk(0, " e Precise IP = %x %s\n", !!(check & X86_PROC_MS_CHK_PRECISE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 113: check & X86_PROC_CHK_PRECISE_IP_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 115: printk(0, " e Restartable IP = %x %s\n", !!(check & X86_PROC_MS_CHK_RESTARTABLE_IP), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 116: check & X86_PROC_CHK_RESTARTABLE_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 118: printk(0, " e Overflow = %x %s\n", !!(check & X86_PROC_MS_CHK_OVERFLOW), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 119: check & X86_PROC_CHK_OVERFLOW_VALID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 122: static const char *check_guid_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 147: printk(0, " ___ CPER IA32/x64 Processor Error (Check) Information @0x%p - 0x%p (size 0x%zx) ___\n", err, err + 1, sizeof(*err)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 148: printk(0, " e Structure Type GUID = %s\n", check_guid_name(err->type)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 151: printk(0, " e Validation Bits = %llx\n", err->validation); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 153: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 154: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 155: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 156: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 158: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 159: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 160: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 161: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 163: x86_chkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 164: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 165: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 166: | X86_PROC_CHK_RESTARTABLE_VALID | X86_PROC_CHK_OVERFLOW_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 167: | X86_PROC_CHK_PART_TYPE_VALID | X86_PROC_CHK_TIMEOUT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 168: | X86_PROC_CHK_ADDR_SPACE_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 170: x86_mschkprint_with_valid(err->check_info, X86_PROC_CHK_XACT_TYPE_VALID | X86_PROC_CHK_OPERATION_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 171: | X86_PROC_CHK_LEVEL_VALID | X86_PROC_CHK_CONTEXT_CORPT_VALID line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 172: | X86_PROC_CHK_UNCORRECTED_VALID | X86_PROC_CHK_PRECISE_IP_VALID); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 179: static const char *context_names[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 210: printk(0, " ___ CPER IA32/x64 Processor Context Information @0x%p - 0x%p (size 0x%zx) ___\n", ctx, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 211: (u8 *)ctx + ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 212: ALIGN_UP(sizeof(*ctx) + ctx->array_size, 16)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 213: printk(0, " t Context Type = %x %s\n", ctx->type, context_name(ctx->type)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 214: printk(0, " t Array Size = %x\n", ctx->array_size); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 216: printk(0, " t MM Address = %llx\n", ctx->mmap_addr); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 224: printk(0, " t %08x_%08x\n", (u32)(*(array + i) >> 32), (u32)*(array + i)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 233: int errs = (ia32->validation & I32X64SEC_VALID_ERRNUM_MASK) >> I32X64SEC_VALID_ERRNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 234: int ctxs = (ia32->validation & I32X64SEC_VALID_CTXNUM_MASK) >> I32X64SEC_VALID_CTXNUM_SH; line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 236: printk(0, " ___ CPER IA32/x64 Processor Error @0x%p sizeof(proc error section struct) is 0x%zx/%zd) ___\n", ia32, sizeof(*ia32), sizeof(*ia32)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 237: printk(0, " x Validation Bits = %llx\n", ia32->validation); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 240: printk(0, " x Processor APIC ID = %llx %s\n", ia32->apicid, ia32->validation & I32X64SEC_VALID_LAPIC ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 241: printk(0, " x Processor CPUID = EAX = %x %s\n", (u32)ia32->cpuid[0], ia32->validation & I32X64SEC_VALID_CPUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 242: printk(0, " x EBX = %x\n", (u32)ia32->cpuid[1]); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 243: printk(0, " x ECX = %x\n", (u32)ia32->cpuid[2]); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 244: printk(0, " x EDX = %x\n", (u32)ia32->cpuid[3]); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 248: adder += parse_x86_error_info((cper_ia32x64_proc_error_info_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 251: adder += parse_x86_context_info((cper_ia32x64_context_t *)((u8 *)ia32 + adder)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 256: static size_t parse_cper_structure_generic(cper_proc_generic_error_section_t *gen) line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 258: printk(0, " ___ CPER Generic Processor Error @0x%p sizeof(generic error struct) is 0x%zx/%zd\n", gen, sizeof(*gen), sizeof(*gen)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 259: printk(0, " c Validation Bits = %llx\n", gen->validation); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 260: printk(0, " c Processor Type = %x %s\n", gen->proc_type, gen->validation & GENPROC_VALID_PROC_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 261: printk(0, " c Processor ISA = %x %s\n", gen->proc_isa, gen->validation & GENPROC_VALID_PROC_ISA ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 262: printk(0, " c Processor Error Type = %x %s\n", gen->error_type, gen->validation & GENPROC_VALID_PROC_ERR_TYPE ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 263: printk(0, " c Operation = %x %s\n", gen->operation, gen->validation & GENPROC_VALID_OPERATION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 264: printk(0, " c Flags = %x %s\n", gen->flags, gen->validation & GENPROC_VALID_FLAGS ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 265: printk(0, " c Level = %x %s\n", gen->level, gen->validation & GENPROC_VALID_LEVEL ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 266: printk(0, " c CPU Version Info = %llx %s\n", gen->cpu_version, gen->validation & GENPROC_VALID_CPU_VERSION ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 267: printk(0, " c CPU Brand String = %s %s\n", gen->cpu_brand_string, gen->validation & GENPROC_VALID_CPU_BRAND ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 268: printk(0, " c Processor ID = %llx %s\n", gen->proc_id, gen->validation & GENPROC_VALID_CPU_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 269: printk(0, " c Target Address = %llx %s\n", gen->target_addr, gen->validation & GENPROC_VALID_TGT_ADDR ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 270: printk(0, " c Requestor Identifier = %llx %s\n", gen->requestor_id, gen->validation & GENPROC_VALID_REQR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 271: printk(0, " c Responder Identifier = %llx %s\n", gen->responder_id, gen->validation & GENPROC_VALID_RSPR_ID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 272: printk(0, " c Instruction IP = %llx %s\n", gen->instruction_ip, gen->validation & GENPROC_VALID_INSTR_IP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 296: return sizeof(acpi_hest_generic_data_v300_t) + entry->data_length; line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 301: static const char *guids382[] = { static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 319: if(!guidcmp(&guid, &CPER_SEC_PROC_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 321: if(!guidcmp(&guid, &CPER_SEC_PROC_IA32X64_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 323: if(!guidcmp(&guid, &CPER_SEC_PROC_ARM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 325: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 327: if(!guidcmp(&guid, &CPER_SEC_PLATFORM_MEM2_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 329: if(!guidcmp(&guid, &CPER_SEC_PCIE_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 331: if(!guidcmp(&guid, &CPER_SEC_FW_ERR_REC_REF_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 333: if(!guidcmp(&guid, &CPER_SEC_PCI_X_BUS_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 335: if(!guidcmp(&guid, &CPER_SEC_PCI_DEV_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 337: if(!guidcmp(&guid, &CPER_SEC_DMAR_GENERIC_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 339: if(!guidcmp(&guid, &CPER_SEC_DMAR_VT_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 341: if(!guidcmp(&guid, &CPER_SEC_DMAR_IOMMU_GUID)) space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 351: printk(0, " ___ 382 found @0x%p sizeof(%s) = 0x%zx/%zd ___\n", entry, entry->revision == 0x300 ? "v3" : "old-type", line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 352: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t), line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 353: entry->revision == 0x300 ? sizeof(acpi_hest_generic_data_v300_t) : sizeof(acpi_hest_generic_data_t)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 354: printk(0, " 3 Section Type GUID = %s\n", guid382_name(entry->section_type)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 357: printk(0, " 3 Severity = %x: %s\n", entry->error_severity, acpi_sev(entry->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 358: printk(0, " 3 Revision = %x\n", entry->revision); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 359: printk(0, " 3 Validation = %x\n", entry->validation_bits); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 361: printk(0, " 3 Error Data Length = %x\n", entry->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 362: printk(0, " 3 FRU ID = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 363: printk(0, " 3 FRU text = <todo> %s\n", entry->validation_bits & ACPI_GENERROR_VALID_FRUID_TEXT ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 365: /* I can cheat on x300 because I know only diff is timestamp */ line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 370: entry->timestamp.hour, entry->timestamp.min, entry->timestamp.sec, line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 371: entry->validation_bits & ACPI_GENERROR_VALID_TIMESTAMP ? "V" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 375: /* each table-382 entry should contain 0 or 1 cper structure at its end */ line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 378: parse_cper_structure((void *)(entry + 1), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 380: parse_cper_structure((void *)((u8 *)entry + sizeof(acpi_hest_generic_data_t)), entry->section_type); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 384: entry = (acpi_hest_generic_data_v300_t *)((u8 *)entry + entry382_size(entry)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 400: static acpi_hest_generic_data_v300_t *ptr382_from_bert_entry(acpi_generic_error_status_t *bert_data) line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 403: return (acpi_hest_generic_data_v300_t *)((u8 *)bert_data + sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 429: printk(0, "***** BERT storage at 0x%p - 0x%p (%zd) *****\n", bert_base, (u8 *)bert_base + size, size); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 431: while(offset < size) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 432: entries = (bert_data->block_status & GENERIC_ERR_STS_ENTRY_COUNT_MASK) >> GENERIC_ERR_STS_ENTRY_COUNT_SHIFT; line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 433: printk(0, " ___ BERT entry @0x%p - (sizeof(status)=0x%zx/%zd) ___\n", bert_data, sizeof(*bert_data), sizeof(*bert_data)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 434: printk(0, " b Block Status = %x\n", bert_data->block_status); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 436: bert_data->block_status & BIT(0) ? " uncorrectable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 437: bert_data->block_status & BIT(1) ? " correctable" : "", line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 438: bert_data->block_status & BIT(2) ? " mult-uncorrected" : "", line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 439: bert_data->block_status & BIT(3) ? " mult-corrected" : ""); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 441: printk(0, " b Raw Data Offset = %x\n", bert_data->raw_data_offset); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 442: printk(0, " b Raw Data Length = %x\n", bert_data->raw_data_length); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 443: printk(0, " b Data Length = %x\n", bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 444: printk(0, " b Error Severity = %x: %s\n", bert_data->error_severity, acpi_sev(bert_data->error_severity)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 445: if (bert_data->data_length && bert_data->data_length < sizeof(acpi_hest_generic_data_v300_t)) line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 447: bert_data->data_length, sizeof(acpi_hest_generic_data_v300_t)); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 448: if (bert_data->raw_data_length && bert_data->raw_data_offset < sizeof(*bert_data) + bert_data->data_length) line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 450: bert_data->raw_data_offset, sizeof(*bert_data), bert_data->data_length); line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 453: /* can have zero or more data entries, of type 382 and/or of raw */ line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 454: gen382 = ptr382_from_bert_entry(bert_data); // todo: this only handles a single 382 entry line over 80 characters https://review.coreboot.org/#/c/28480/3/src/soc/amd/stoneyridge/bertdump.c@… PS3, Line 463: bert_data = (acpi_generic_error_status_t *)((u8 *)bert_data + offset); line over 80 characters -- To view, visit https://review.coreboot.org/28480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ecf920499a662db34a332e9df05e4ee2383b6d4 Gerrit-Change-Number: 28480 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Sep 2018 18:14:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit September 2018