coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

1 participants
2751 discussions

Change in coreboot[master]: Documentation: Add cavium SoC and mainboard
by Patrick Rudolph (Code Review) 18 Jun '18

18 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27150 Change subject: Documentation: Add cavium SoC and mainboard ...................................................................... Documentation: Add cavium SoC and mainboard Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/index.md A Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg A Documentation/mainboard/cavium/cn8100_sff_evb.md M Documentation/mainboard/index.md A Documentation/soc/cavium/bootflow.md A Documentation/soc/cavium/cavium_bootflow.png A Documentation/soc/cavium/cn81xx/index.md A Documentation/soc/cavium/index.md M Documentation/soc/index.md A Documentation/vendorcode/cavium/bdk.md A Documentation/vendorcode/cavium/index.md A Documentation/vendorcode/index.md 12 files changed, 273 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27150/1 diff --git a/Documentation/index.md b/Documentation/index.md index 4ec4550..cf22dca 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -18,4 +18,5 @@ * [System on Chip-specific documentation](soc/index.md) * [Mainboard-specific documentation](mainboard/index.md) * [SuperIO-specific documentation](superio/index.md) +* [Vendorcode-specific documentation](vendorcode/index.md) * [Release notes for past releases](releases/index.md) diff --git a/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg new file mode 100644 index 0000000..0afe778 --- /dev/null +++ b/Documentation/mainboard/cavium/cavium_cn81xx_sff_evb.jpg Binary files differ diff --git a/Documentation/mainboard/cavium/cn8100_sff_evb.md b/Documentation/mainboard/cavium/cn8100_sff_evb.md new file mode 100644 index 0000000..b16a8ae --- /dev/null +++ b/Documentation/mainboard/cavium/cn8100_sff_evb.md @@ -0,0 +1,76 @@ +# CN81xx Evaluation-board SFF + +## Specs + +* 3 mini PCIe slots +* 4 SATA ports +* one USB3.0 A connector +* 20Pin JTAG +* 4 Gigabit Ethernet +* 2 SFP+ connectors +* PCIe x4 slot +* UART over USB +* eMMC Flash or MicroSD card slot for on-board storage +* 1 Slot with DDR-4 memory with ECC support +* SPI flash +* MMC and uSD-card + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | no | ++---------------------+----------------+ +| Model | Micron 25Q128A | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| In circuit flashing | no | ++---------------------+----------------+ +| Package | SOIC-8 | ++---------------------+----------------+ +| Write protection | No | ++---------------------+----------------+ +| Dual BIOS feature | No | ++---------------------+----------------+ +| Internal flashing | ? | ++---------------------+----------------+ +``` + +## Notes about the hardware + +1. Cavium connected *GPIO10* to a global reset line. + It's unclear which chips are connected, but at least the PHY and SATA chips + are connected. + +2. The 4 QLMs can be configured using DIP switches (SW1). That means only a + subset of of the available connectors is working at time. + +3. The boot source can be configure using DIP switches (SW1). + +4. The core and system clock frequency can be configured using DIP switches + (SW3 / SW2). + +5. The JTAG follows Cavium's own protocol. Support for it is missing in + OpenOCD. You have to use ARMs official hardware and software. + +## Technology + +```eval_rst ++---------------+----------------------------------------+ +| SoC | :doc:`../../soc/cavium/cn81xx/index` | ++---------------+----------------------------------------+ +| CPU | Cavium ARMv8-Quadcore `CN81XX`_ | ++---------------+----------------------------------------+ + +.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html + +``` + +## Picture + +![][cn81xx_board] + +[cn81xx_board]: cavium_cn81xx_sff_evb.jpg diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 23e1ed2..8693f63 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -9,3 +9,7 @@ ## HP - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) + +## Cavium + +- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) diff --git a/Documentation/soc/cavium/bootflow.md b/Documentation/soc/cavium/bootflow.md new file mode 100644 index 0000000..70bf865 --- /dev/null +++ b/Documentation/soc/cavium/bootflow.md @@ -0,0 +1,19 @@ +# Cavium bootflow + +The on-chip **BOOTROM** first sets up the L2 cache and the SPI controller. +It then reads **CSIB_NBL1FW** and **CLIB_NBL1FW** configuration data to get +the position of the bootstage in flash. It then loads 192KiB from flash into +L2 cache to a fixed address. The boot mode is called "Non-Secure-Boot" as +the signature of the bootstage isn't verified. +The **BOOTROM** can do AES decryption for obfuscation or verify the signature +of the bootstage. Both features aren't used and won't be described any further. + +* The typical position of bootstage in flash is at address **0x20000**. +* The entry point in physical DRAM is at address **0x100000**. + +## Layout + +![Bootflow of Cavium CN8xxx SoCs][cavium_bootflow] + +[cavium_bootflow]: cavium_bootflow.png + diff --git a/Documentation/soc/cavium/cavium_bootflow.png b/Documentation/soc/cavium/cavium_bootflow.png new file mode 100644 index 0000000..1e90173 --- /dev/null +++ b/Documentation/soc/cavium/cavium_bootflow.png Binary files differ diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md new file mode 100644 index 0000000..69fe710 --- /dev/null +++ b/Documentation/soc/cavium/cn81xx/index.md @@ -0,0 +1,119 @@ +# Cavium CN81xx documentation + +## Reference code + +```eval_rst +The Cavium reference code is called `BDK`_ (board development kit) and is part +of the `Octeon-TX-SDK`_. Parts of the `BDK`_ have been integrated into coreoboot. +``` + +## SOC code + +The SOC folder contains functions for: +* TWSI +* UART +* TIMER +* SPI +* MMU +* DRAM +* CLOCK +* GPIO +* Secondary CPUs +* PCI + +All other hardware is initilized by the BDK code, which is invoked from +ramstage. + +## Notes about the hardware + +Cavium SoC do **not** have embedded SRAM. The **BOOTROM** setups the +L2 cache and loads 192KiB of firmware starting from 0x20000 to a fixed +location. It then jumps to the firmware. + +```eval_rst +For more details have a look at `Cavium CN8XXX Bootflow`_. +``` + +## CAR setup + +For Cache-as-RAM we only need to lock the cachelines which are used by bootblock +or romstage until DRAM has been set up. At the end of romstage the cachelines +are unlocked and the contents are flushed to DRAM. +Locked cachelines are never evicted. + +The CAR setup is done in '''bootblock_custom.S''' and thus doesn't use the common +aarch64 '''bootblock.S''' code. + +## DRAM setup + +```eval_rst +The DRAM setup is done by the `BDK`_. +``` + +## PCI setup + +The PCI setup is done using the MMCONF mechanism. +Besides configuring device visibility (secure/unsecure) the MSI-X interrupts +needs to be configured. + +## Devicetree patching + +The Linux devicetree needs to be patched, depending on the available hardware +and their configuration. Some values depends on fuses, some on user selectable +configuration. + +The following SoC specific fixes are made: + +1. Fix SCLK +2. Fix UUA refclock +3. Remove unused PEM entries +4. Remove unused QLM entries +5. Set local MAC address + +## CN81xx quirks + +The CN81xx needs some quirks that are not documented or hidden in the code. + +### Violation of PCI spec + +**Problem:** + +* The PCI device 01:01.0 is disabled, but a multifunction device. +* The PCI device 01:01.2 - 00:01.7 is enabled and can't be found by the coreboot + PCI allocator. + +**Solution:** + +The PCI Bus 0 and 1 are scanned manually in SOC's PCI code. + + +### Crash accessing SLI memory + +**Problem:** + +The SLI memory region decodes to attached PCIe devices. +Accessing the memory region results in 'Data Abort Exception' if the link of the +PCIe device never had been enabled. + +**Solution:** + +Enable the PCIe link at least once. (You can disabling the link and the SLI +memory reads as 0xffffffff.) + + +### RNG Data Abort Exception + +**Problem:** + +'Data Abort Exception' on accessing the enabled RNG. + +**Solution**: + +Read the BDK_RNM_CTL_STATUS register at least once after writing it. + + +```eval_rst +.. _Octeon-TX-SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK +.. _Cavium CN8XXX Bootflow: ../bootflow.html +.. _BDK: ../../../vendorcode/cavium/bdk.html +``` diff --git a/Documentation/soc/cavium/index.md b/Documentation/soc/cavium/index.md new file mode 100644 index 0000000..5ccb47f --- /dev/null +++ b/Documentation/soc/cavium/index.md @@ -0,0 +1,8 @@ +# Cavium SOC-specific documentation + +This section contains documentation about coreboot on specific Cavium SOCs. + +## Platforms + +- [CN81xx series](cn81xx/index.md) +- [CN8xxx bootflow](bootflow.md) diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md index ca50dc8..6081947 100644 --- a/Documentation/soc/index.md +++ b/Documentation/soc/index.md @@ -5,3 +5,4 @@ ## Vendor - [Intel](intel/index.md) +- [Cavium](cavium/index.md) diff --git a/Documentation/vendorcode/cavium/bdk.md b/Documentation/vendorcode/cavium/bdk.md new file mode 100644 index 0000000..5763ece --- /dev/null +++ b/Documentation/vendorcode/cavium/bdk.md @@ -0,0 +1,30 @@ +# Cavium's BDK + +## BDK +A part of Cavium's BDK can be found in '''src/vendorcode/cavium/bdk'''. +It does the **DRAM init** in romstage and the **PCIe**, **QLM**, **SLI**, +**PHY**, **BGX**, **SATA** init in ramstage. + +## Devicetree +The BDK does use it's own devicetree, as coreboot's devicetree isn't +compatible. The devicetree stores key-value pairs (see **bdk-devicetree.h** +for implementation details), where the key and the value are stored as strings. + +The key-value pairs must be advertised in romstage and ramstage using the +'''bdk_config_set_fdt()''' method. + +The tool '''util/cavium/devicetree_convert.py''' can be used to convert a +devicetree to a key-value array. + +## Modifications + +* The BDK has been modified to compile under coreboot's toolchain. +* Removed FDT devicetree support. +* Dropped files that aren't required for SoC bringup +* Added Kconfig values for verbose console output + +## Debugging + +You can enable verbose console output in *menuconfig*: + +Go to **Chipset**, **BDK** and enable one or multiple stages. diff --git a/Documentation/vendorcode/cavium/index.md b/Documentation/vendorcode/cavium/index.md new file mode 100644 index 0000000..e06e2ba --- /dev/null +++ b/Documentation/vendorcode/cavium/index.md @@ -0,0 +1,8 @@ +# Cavium vendorcode-specific documentation + +This section contains documentation about coreboot on Cavium specific +vendorcode. + +## Sections + +- [BDK](bdk.md) diff --git a/Documentation/vendorcode/index.md b/Documentation/vendorcode/index.md new file mode 100644 index 0000000..3374eaf --- /dev/null +++ b/Documentation/vendorcode/index.md @@ -0,0 +1,7 @@ +# Vendorcode-specific documentation + +This section contains documentation about coreboot on specific vendorcode. + +## Vendor + +- [Cavium](cavium/index.md) -- To view, visit https://review.coreboot.org/27150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Gerrit-Change-Number: 27150 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

Change in coreboot[master]: cbfstool: add an option for creating a topswap bootblock
by build bot (Jenkins) (Code Review) 18 Jun '18

18 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22537 ) Change subject: cbfstool: add an option for creating a topswap bootblock ...................................................................... Patch Set 20: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/29135/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/75043/ : SUCCESS -- To view, visit https://review.coreboot.org/22537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8 Gerrit-Change-Number: 22537 Gerrit-PatchSet: 20 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Comment-Date: Mon, 18 Jun 2018 09:19:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: cbfstool: Update FIT entries in the second bootblock
by build bot (Jenkins) (Code Review) 18 Jun '18

18 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26836 ) Change subject: cbfstool: Update FIT entries in the second bootblock ...................................................................... Patch Set 11: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/29136/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/75042/ : SUCCESS -- To view, visit https://review.coreboot.org/26836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644 Gerrit-Change-Number: 26836 Gerrit-PatchSet: 11 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 18 Jun 2018 09:18:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add SAR sensor device into devicet...
by build bot (Jenkins) (Code Review) 18 Jun '18

18 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27149 ) Change subject: mb/google/poppy/variants/nautilus: Add SAR sensor device into devicetree.cb ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29134/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75041/ : SUCCESS -- To view, visit https://review.coreboot.org/27149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915 Gerrit-Change-Number: 27149 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Jun 2018 07:15:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKU
by build bot (Jenkins) (Code Review) 18 Jun '18

18 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27147 ) Change subject: mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKU ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29133/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75040/ : SUCCESS -- To view, visit https://review.coreboot.org/27147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Gerrit-Change-Number: 27147 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Jun 2018 07:11:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Correct USB OC pin configuration
by build bot (Jenkins) (Code Review) 18 Jun '18

18 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27099 ) Change subject: mb/google/poppy/variants/nautilus: Correct USB OC pin configuration ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75038/ : SUCCESS -- To view, visit https://review.coreboot.org/27099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 Gerrit-Change-Number: 27099 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Jun 2018 07:09:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5
by build bot (Jenkins) (Code Review) 18 Jun '18

18 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27148 ) Change subject: mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5 ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29132/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75039/ : SUCCESS -- To view, visit https://review.coreboot.org/27148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111 Gerrit-Change-Number: 27148 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Jun 2018 07:07:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Add SAR sensor device into devicet...
by Seunghwan Kim (Code Review) 18 Jun '18

18 Jun '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27149 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nautilus: Add SAR sensor device into devicetree.cb ...................................................................... mb/google/poppy/variants/nautilus: Add SAR sensor device into devicetree.cb This change defines SAR sensor device into devicetree.cb. Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio. BUG=None BRANCH=poppy TEST=Verified SAR sensor device is loaded by driver in Chrome OS Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27149/2 -- To view, visit https://review.coreboot.org/27149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915 Gerrit-Change-Number: 27149 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5
by Seunghwan Kim (Code Review) 18 Jun '18

18 Jun '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27148 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5 ...................................................................... mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5 Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage. BUG=None BRANCH=poppy TEST=Verified the leakage is gone after update coreboot Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/Makefile.inc A src/mainboard/google/poppy/variants/nautilus/smihandler.c 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27148/2 -- To view, visit https://review.coreboot.org/27148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111 Gerrit-Change-Number: 27148 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKU
by Seunghwan Kim (Code Review) 18 Jun '18

18 Jun '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27147 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKU ...................................................................... mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKU For supporting new SKU, we need to override GPIO table and device configuration. The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it. BUG=b:80052672 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/poppy/variants/nautilus/Makefile.inc M src/mainboard/google/poppy/variants/nautilus/gpio.c A src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h A src/mainboard/google/poppy/variants/nautilus/mainboard.c 4 files changed, 145 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27147/2 -- To view, visit https://review.coreboot.org/27147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Gerrit-Change-Number: 27147 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2018