coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

1 participants
2751 discussions

Change in coreboot[master]: util/lint/checkpatch_json: Fix checkpatch output keyword match string
by build bot (Jenkins) (Code Review) 22 Jun '18

22 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27170 ) Change subject: util/lint/checkpatch_json: Fix checkpatch output keyword match string ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75183/ : SUCCESS -- To view, visit https://review.coreboot.org/27170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib690ab34a1ffabc4f83642634fd34beea16a64dc Gerrit-Change-Number: 27170 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Jun 2018 04:23:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP] mb/google/octopus: Fix unused pins and those with external term...
by build bot (Jenkins) (Code Review) 21 Jun '18

21 Jun '18

1 0

Change in coreboot[master]: [WIP] mb/google/octopus: Fix unused pins and those with external term...
by build bot (Jenkins) (Code Review) 21 Jun '18

21 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27183 ) Change subject: [WIP] mb/google/octopus: Fix unused pins and those with external terminations ...................................................................... Patch Set 1: (24 comments) https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 96: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 131: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 134: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 166: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 175: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 203: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 226: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 228: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 259: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 94: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 129: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 131: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 132: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 135: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 164: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 170: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 173: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 203: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 227: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/1/src/mainboard/google/octopus/varian… PS1, Line 258: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters -- To view, visit https://review.coreboot.org/27183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Gerrit-Change-Number: 27183 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Jun 2018 02:34:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP] mb/google/octopus: Fix unused pins and those with external term...
by Shamile Khan (Code Review) 21 Jun '18

21 Jun '18

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/27183 Change subject: [WIP] mb/google/octopus: Fix unused pins and those with external terminations ...................................................................... [WIP] mb/google/octopus: Fix unused pins and those with external terminations BUG=None TEST=Octopus coreboot compiles. Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bip/gpio.c 2 files changed, 103 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/27183/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index a7b8f19..c18856e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -26,14 +26,14 @@ */ static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */ + PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, UP_20K, DEEP, NF1), /* CX_PREQ_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, UP_20K, DEEP, NF1), /* CX_PRDY_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ @@ -65,44 +65,44 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA5_VNN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_42, 0, DEEP, DN_20K, HIZCRx1, DISPUPD), /* GP_INTD_DSI_TE1 */ + PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ + PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ + PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ + PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_46, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SDA */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_47, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SCL */ + PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ + PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_54, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* LPSS_I2C2_SDA -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_55, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* LPSS_I2C2_SCL -- unused */ + PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ + PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ - PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SDA - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SCL - unused */ + PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */ + PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ - PAD_NC(GPIO_62, NONE), /* GPIO_62 -- NC */ + PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */ + PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_TXD */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_CLK */ + PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ + PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_B */ + PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ @@ -110,9 +110,9 @@ /* NORTH COMMUNITY GPIOS */ /* svid - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Alert - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Data - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Clk - unused */ + PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ + PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ + PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ /* LPSS */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ @@ -128,22 +128,22 @@ PAD_NC(GPIO_89, NONE), /* GPIO_89 -- NC */ /* Fast SPI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* FST_SPI_MISO_IO1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */ PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ /* PMU Signals */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* PMU_PWRBTN_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, NONE, DEEP, NF1, HIZCRx0, DISPUPD),/* EMMC_DNX_PWR_EN_B - unused */ + PAD_NC(GPIO_104, NONE),/* EMMC_DNX_PWR_EN_B - unused */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ @@ -163,22 +163,22 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ /* PCIE_WAKE[0:3]_B */ - PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */ - PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */ + PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ /* PCIE_CLKREQ[0:3]_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ /* DDI[0:1] SDA and SCL -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */ + PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ + PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ + PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ + PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ /* Panel 0 control */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ @@ -190,7 +190,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ - PAD_NC(GPIO_134, NONE),/* GPIO_134 -- NC */ + PAD_NC(GPIO_134, NONE),/* GPIO_134 -- unused */ PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ @@ -200,7 +200,7 @@ // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others). // Settings here do not match table // Also we may be able to use eSPI WAKE# Virtual Wire instead - PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */ + PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ PAD_CFG_GPI_SCI_LOW(GPIO_144, NONE, DEEP, LEVEL),/* GPIO_144 -- PEN_EJECT_ODL(wake) */ @@ -214,7 +214,7 @@ */ /* AUDIO COMMUNITY GPIOS*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_156, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_I2S0_MCLK */ + PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */ @@ -223,8 +223,9 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* AVS_I2S2_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ @@ -236,8 +237,8 @@ PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 */ /* SCC COMMUNITY GPIOS */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_ALERTB */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */ + PAD_NC(GPIO_176, NONE), /* SMB_ALERTB -- unused */ + PAD_NC(GPIO_177, NONE), /* SMB_CLK -- unused */ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ @@ -255,8 +256,8 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC0_STROBE */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ + PAD_NC(GPIO_210, DN_20K), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index 5f83ee4..685ffef 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -24,14 +24,14 @@ */ static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */ + PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, UP_20K, DEEP, NF1), /* CX_PREQ_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, UP_20K, DEEP, NF1), /* CX_PRDY_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ @@ -63,44 +63,44 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA5_VNN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_42, 0, DEEP, DN_20K, HIZCRx1, DISPUPD), /* GP_INTD_DSI_TE1 */ + PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ + PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ + PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ + PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_46, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SDA */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_47, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SCL */ + PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ + PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_54, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* LPSS_I2C2_SDA -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_55, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* LPSS_I2C2_SCL -- unused */ + PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ + PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ - PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SDA - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SCL - unused */ + PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */ + PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ - PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */ + PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_TXD */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_CLK */ + PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ + PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_B */ + PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ @@ -108,9 +108,9 @@ /* NORTH COMMUNITY GPIOS */ /* svid - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Alert - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Data - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Clk - unused */ + PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ + PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ + PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ /* LPSS */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ @@ -126,22 +126,22 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_89, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* LPSS_SPI_2_TXD */ /* Fast SPI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* FST_SPI_MISO_IO1 */ - PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ + PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */ + PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ /* PMU Signals */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* PMU_PWRBTN_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, NONE, DEEP, NF1, HIZCRx0, DISPUPD),/* EMMC_DNX_PWR_EN_B - unused */ + PAD_NC(GPIO_104, NONE),/* EMMC_DNX_PWR_EN_B - unused */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ @@ -161,22 +161,22 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ /* PCIE_WAKE[0:3]_B */ - PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */ - PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */ + PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ /* PCIE_CLKREQ[0:3]_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ /* DDI[0:1] SDA and SCL -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */ + PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ + PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ + PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ + PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ /* Panel 0 control */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ @@ -200,7 +200,7 @@ // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others). // Settings here do not match table // Also we may be able to use eSPI WAKE# Virtual Wire instead - PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */ + PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ @@ -214,17 +214,17 @@ */ /* AUDIO COMMUNITY GPIOS*/ - PAD_CFG_GPIO_HI_Z(GPIO_156, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_MCLK -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_157, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_BCLK -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_158, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_WS_SYNC -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_159, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_SDI -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_160, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_SDO -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_161, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S1_MCLK -- unused */ + PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ + PAD_NC(GPIO_157, DN_20K),/* AVS_I2S0_BCLK -- unused */ + PAD_NC(GPIO_158, DN_20K),/* AVS_I2S0_WS_SYNC -- unused */ + PAD_NC(GPIO_159, DN_20K),/* AVS_I2S0_SDI -- unused */ + PAD_NC(GPIO_160, DN_20K),/* AVS_I2S0_SDO -- unused */ + PAD_NC(GPIO_161, DN_20K),/* AVS_I2S1_MCLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* AVS_I2S2_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ @@ -236,8 +236,8 @@ PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 */ /* SCC COMMUNITY GPIOS */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_ALERTB */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */ + PAD_NC(GPIO_176, NONE), /* SMB_ALERTB -- unused */ + PAD_NC(GPIO_177, NONE), /* SMB_CLK -- unused */ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ @@ -255,8 +255,8 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC0_STROBE */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ + PAD_NC(GPIO_210, DN_20K), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/27183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Gerrit-Change-Number: 27183 Gerrit-PatchSet: 1 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nami: Touchscreen gpio setting for Pantheon
by build bot (Jenkins) (Code Review) 21 Jun '18

21 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27177 ) Change subject: mb/google/poppy/variants/nami: Touchscreen gpio setting for Pantheon ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75180/ : SUCCESS -- To view, visit https://review.coreboot.org/27177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af Gerrit-Change-Number: 27177 Gerrit-PatchSet: 4 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Jun 2018 02:01:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: intel/skylake: nhlt: Add capture config for echo ref stream
by build bot (Jenkins) (Code Review) 21 Jun '18

21 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27182 ) Change subject: intel/skylake: nhlt: Add capture config for echo ref stream ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29249/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75179/ : SUCCESS -- To view, visit https://review.coreboot.org/27182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9 Gerrit-Change-Number: 27182 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 22 Jun 2018 00:00:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: intel/skylake: nhlt: Add capture config for echo ref stream
by Sathyanarayana Nujella (Code Review) 21 Jun '18

21 Jun '18

Sathyanarayana Nujella has uploaded this change for review. ( https://review.coreboot.org/27182 Change subject: intel/skylake: nhlt: Add capture config for echo ref stream ...................................................................... intel/skylake: nhlt: Add capture config for echo ref stream During Speaker playback, quad Channel I/V feedback data is captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data needs to be given as echo ref stream. So, adding stereo capture config to max98373_capture_formats. BUG=b:110074225 TEST='Audio playback and Capture Stereo echo ref data' Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- M src/soc/intel/skylake/nhlt/max98373.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/27182/1 diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 7d01b92..beb4558 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -37,7 +37,7 @@ }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample. */ + /* 48 KHz 16-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, @@ -46,6 +46,15 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-16b.bin", }, + /* 48 KHz 16-bits per sample - Stereo Channel */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 16, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98373-render-2ch-48khz-16b.bin", + }, }; static const struct nhlt_endp_descriptor max98373_descriptors[] = { -- To view, visit https://review.coreboot.org/27182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9 Gerrit-Change-Number: 27182 Gerrit-PatchSet: 1 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com>

1 0

Change in coreboot[master]: mb/google/nami: Enable xDCI
by build bot (Jenkins) (Code Review) 21 Jun '18

21 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27181 ) Change subject: mb/google/nami: Enable xDCI ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29246/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75176/ : SUCCESS -- To view, visit https://review.coreboot.org/27181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Gerrit-Change-Number: 27181 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Jun 2018 21:59:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/nami: Enable xDCI
by Furquan Shaikh (Code Review) 21 Jun '18

21 Jun '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27181 ) Change subject: mb/google/nami: Enable xDCI ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/27181/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27181/1//COMMIT_MSG@7 PS1, Line 7: nami poppy/variants/nami: -- To view, visit https://review.coreboot.org/27181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Gerrit-Change-Number: 27181 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 21 Jun 2018 21:51:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/nami: Enable xDCI
by Shelley Chen (Code Review) 21 Jun '18

21 Jun '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/27181 Change subject: mb/google/nami: Enable xDCI ...................................................................... mb/google/nami: Enable xDCI This change enables xDCI controller on nami. BUG=b:110443736 BRANCH=None TEST=None Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27181/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d4f262e..54d989f 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -295,7 +295,7 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) + device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/27181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Gerrit-Change-Number: 27181 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2018