Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27204
to look at the new patch set (#3).
Change subject: nb/intel/i945: Add C1DRBs when channel B is empty
......................................................................
nb/intel/i945: Add C1DRBs when channel B is empty
C1DRBs must be programmed with the same value as C0DRB3
when the channel B is empty.
If channels are interleave, C0DRB* is equal to C1DRB*.
Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 19 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/27204/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Gerrit-Change-Number: 27204
Gerrit-PatchSet: 3
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27204
to look at the new patch set (#2).
Change subject: nb/intel/i945: Add C1DRBs when channel B is empty
......................................................................
nb/intel/i945: Add C1DRBs when channel B is empty
C1DRBs must be programmed with the same value as C0DRB3
when the channel B is empty.
If channels are interleave, C0DRB* is equal to C1DRB*.
Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 19 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/27204/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Gerrit-Change-Number: 27204
Gerrit-PatchSet: 2
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27204
Change subject: nb/intel/i945: Add C1DRBs when channel B is empty
......................................................................
nb/intel/i945: Add C1DRBs when channel B is empty
C1DRBs must be programmed with the same value as C0DRB3
when the channel B is empty.
If channels are interleave, C0DRB* is equal to C1DRB*.
Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 16 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/27204/1
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 6719961..615832d 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1189,25 +1189,27 @@
for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
cum0 += sysinfo->banksize[i];
MCHBAR8(C0DRB0+i) = cum0;
+ /* If interleaved C0DRB's = C1DRB's */
+ if (sysinfo->interleaved)
+ MCHBAR8(C1DRB0+i) = cum0;
+ }
+
+ /* If channel 1 is empty, all of the C1DRBs are programmed with the same value as C0DRB3 */
+ if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
+ sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) {
+ for (i = 0; i < 2 * DIMM_SOCKETS; i++)
+ MCHBAR8(C1DRB0+i) = cum1;
}
/* Assume we continue in Channel 1 where we stopped in Channel 0 */
cum1 = cum0;
- /* Exception: Interleaved starts from the beginning */
- if (sysinfo->interleaved)
- cum1 = 0;
-
-#if 0
- /* Exception: Channel 1 is not populated. C1DRB stays zero */
- if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
- sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
- cum1 = 0;
-#endif
-
- for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
- cum1 += sysinfo->banksize[i + 4];
- MCHBAR8(C1DRB0+i) = cum1;
+ if (!(sysinfo->interleaved) && (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
+ sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
+ for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
+ cum1 += sysinfo->banksize[i + 4];
+ MCHBAR8(C1DRB0+i) = cum1;
+ }
}
/* Set TOLUD Top Of Low Usable DRAM */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Gerrit-Change-Number: 27204
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27090 )
Change subject: cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header
......................................................................
cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header
Some older CPUs have a fixed size of 2048 bytes for microcode total size.
Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27090
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/cbfstool/fit.c
1 file changed, 7 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index e3e6c32..d33cb56 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -226,13 +226,18 @@
mcu_header = rom_buffer_pointer(&image->buffer, current_offset);
+ /* Newer microcode updates include a size field, whereas older
+ * containers set it at 0 and are exactly 2048 bytes long */
+ uint32_t total_size = mcu_header->total_size
+ ? mcu_header->total_size : 2048;
+
/* Quickly sanity check a prospective microcode update. */
- if (mcu_header->total_size < sizeof(*mcu_header))
+ if (total_size < sizeof(*mcu_header))
break;
/* FIXME: Should the checksum be validated? */
mcus[num_mcus].offset = current_offset;
- mcus[num_mcus].size = mcu_header->total_size;
+ mcus[num_mcus].size = total_size;
/* Proceed to next payload. */
current_offset += mcus[num_mcus].size;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Gerrit-Change-Number: 27090
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25152 )
Change subject: payloads/LinuxBoot: Add ARM64 support
......................................................................
Patch Set 5: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/29257/ : SUCCESS
https://qa.coreboot.org/job/coreboot-gerrit/75189/ : SUCCESS
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Gerrit-Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c
Gerrit-Change-Number: 25152
Gerrit-PatchSet: 5
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Fri, 22 Jun 2018 07:56:41 +0000
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