coreboot-gerrit June 2018

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Change in coreboot[master]: mb/google/octopus: Fix unused pins and those with external terminations
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

1 0

Change in coreboot[master]: mb/google/octopus: Fix unused pins and those with external terminations
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27183 ) Change subject: mb/google/octopus: Fix unused pins and those with external terminations ...................................................................... Patch Set 3: (32 comments) https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 96: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 131: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 134: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 166: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 175: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 198: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 203: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 225: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 227: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 248: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 258: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 285: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 94: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 136: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 138: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 142: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 146: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 171: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 177: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 180: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 204: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 205: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 210: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 232: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 234: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 255: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 265: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27183/3/src/mainboard/google/octopus/varian… PS3, Line 292: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters -- To view, visit https://review.coreboot.org/27183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Gerrit-Change-Number: 27183 Gerrit-PatchSet: 3 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shamile Khan <shamile(a)gmail.com> Gerrit-Comment-Date: Thu, 28 Jun 2018 20:17:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable IO CF9 in bootblock
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27267 ) Change subject: stoneyridge: Enable IO CF9 in bootblock ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29538/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75495/ : SUCCESS -- To view, visit https://review.coreboot.org/27267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Gerrit-Change-Number: 27267 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 19:53:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: stoneyridge: Enable IO CF9 in bootblock
by Raul Rangel (Code Review) 28 Jun '18

28 Jun '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27267 Change subject: stoneyridge: Enable IO CF9 in bootblock ...................................................................... stoneyridge: Enable IO CF9 in bootblock If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27267/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 06ef898..9f8a7d2 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -32,6 +32,8 @@ #define PSP_MAILBOX_BAR_EN 0x10 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_DECODE_EN 0x00 +#define CF9_IO_EN BIT(1) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c46bcb4..591a8f7 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -368,6 +368,13 @@ outb(byte, PM_DATA); } +static void sb_enable_cf9_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -542,6 +549,7 @@ sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); + sb_enable_cf9_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/27267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Gerrit-Change-Number: 27267 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: cbfstool: fix FIT entry checksum value for ucode entries
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27266 ) Change subject: cbfstool: fix FIT entry checksum value for ucode entries ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29537/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75494/ : SUCCESS -- To view, visit https://review.coreboot.org/27266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676 Gerrit-Change-Number: 27266 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 18:40:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cbfstool: fix FIT entry checksum value for ucode entries
by Matt DeVillier (Code Review) 28 Jun '18

28 Jun '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27266 Change subject: cbfstool: fix FIT entry checksum value for ucode entries ...................................................................... cbfstool: fix FIT entry checksum value for ucode entries commit c1072f2 [cbfstool: Update FIT entries in the second bootblock] incorrectly changed the value of type_checksum_valid for microcode entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on Skylake/FSP1.1 devices (and others?). Correct this by reverting to the previous value. Test: build/boot google/chell, observe FspTempRamInit no longer fails, device boots as expected. Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/cbfstool/fit.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27266/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 31ab3de..ad9ab37 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -182,8 +182,7 @@ * rather from the MCU header, hence we can assign zero here */ entry->size_reserved = 0x0000; - /* Checksum valid should be cleared for MCU */ - entry->type_checksum_valid = 0; + entry->type_checksum_valid = FIT_TYPE_MICROCODE; entry->version = FIT_MICROCODE_VERSION; entry->checksum = 0; fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); -- To view, visit https://review.coreboot.org/27266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676 Gerrit-Change-Number: 27266 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: sb/intel/i82801ix: Use the common ACPI pirq generator
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22980 ) Change subject: sb/intel/i82801ix: Use the common ACPI pirq generator ...................................................................... Patch Set 27: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29535/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75492/ : SUCCESS -- To view, visit https://review.coreboot.org/22980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Gerrit-Change-Number: 22980 Gerrit-PatchSet: 27 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 18:00:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801{g, j}x: Automatically generate ACPI PIRQ tables
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22981 ) Change subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables ...................................................................... Patch Set 21: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29536/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75493/ : SUCCESS -- To view, visit https://review.coreboot.org/22981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Gerrit-Change-Number: 22981 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 17:58:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nocturne: Do not set 4 LSB of SX9310 CRTL0
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27265 ) Change subject: nocturne: Do not set 4 LSB of SX9310 CRTL0 ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/75490/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/29534/ : SUCCESS -- To view, visit https://review.coreboot.org/27265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Gerrit-Change-Number: 27265 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 28 Jun 2018 17:18:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nocturne: Fix casing for register definition
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27264 ) Change subject: nocturne: Fix casing for register definition ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29533/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75489/ : SUCCESS -- To view, visit https://review.coreboot.org/27264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Gerrit-Change-Number: 27264 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 17:17:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018