coreboot-gerrit June 2018

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Change in coreboot[master]: nocturne: Do not set 4 LSB of SX9310 CRTL0
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27265 ) Change subject: nocturne: Do not set 4 LSB of SX9310 CRTL0 ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/75491/ : FAILURE -- To view, visit https://review.coreboot.org/27265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Gerrit-Change-Number: 27265 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 28 Jun 2018 17:16:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nocturne: Do not set 4 LSB of SX9310 CRTL0
by Furquan Shaikh (Code Review) 28 Jun '18

28 Jun '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27265 ) Change subject: nocturne: Do not set 4 LSB of SX9310 CRTL0 ...................................................................... Patch Set 2: Lot of unrelated changes got into this CL. -- To view, visit https://review.coreboot.org/27265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Gerrit-Change-Number: 27265 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 28 Jun 2018 17:15:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nocturne: Fix casing for register definition
by Furquan Shaikh (Code Review) 28 Jun '18

28 Jun '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27264 ) Change subject: nocturne: Fix casing for register definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Gerrit-Change-Number: 27264 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 28 Jun 2018 17:15:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nocturne: Do not set 4 LSB of SX9310 CRTL0
by Gwendal Grignou (Code Review) 28 Jun '18

28 Jun '18

Gwendal Grignou has uploaded a new patch set (#2). ( https://review.coreboot.org/27265 ) Change subject: nocturne: Do not set 4 LSB of SX9310 CRTL0 ...................................................................... nocturne: Do not set 4 LSB of SX9310 CRTL0 These bits start the acquisition process. They should only be set by the driver. BUG=b:74363445 TEST=compile Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> --- M 3rdparty/arm-trusted-firmware M 3rdparty/blobs M 3rdparty/chromeec M 3rdparty/libgfxinit M 3rdparty/libhwbase M 3rdparty/vboot M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M util/nvidia/cbootimage 8 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27265/2 -- To view, visit https://review.coreboot.org/27265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Gerrit-Change-Number: 27265 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org>

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Change in coreboot[master]: nocturne: Do not set 4 LSB of CRTL0
by Gwendal Grignou (Code Review) 28 Jun '18

28 Jun '18

Gwendal Grignou has uploaded this change for review. ( https://review.coreboot.org/27265 Change subject: nocturne: Do not set 4 LSB of CRTL0 ...................................................................... nocturne: Do not set 4 LSB of CRTL0 These bits start the acquisition process. They should only be set by the driver. BUG=b:74363445 TEST=compile Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> --- M 3rdparty/arm-trusted-firmware M 3rdparty/blobs M 3rdparty/chromeec M 3rdparty/libgfxinit M 3rdparty/libhwbase M 3rdparty/vboot M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M util/nvidia/cbootimage 8 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27265/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278..236c27d 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit 236c27d21f52ad8f0a998e54774e3d8a4b59129d diff --git a/3rdparty/blobs b/3rdparty/blobs index 78a02a7..8e9f99b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 78a02a7f9d979fcc864638cc40084e662476095f +Subproject commit 8e9f99b3e60d0ffe8b67cc93ea4ab1b9ed191e45 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..bcffec7 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit bcffec7fdc50e959cb298d094d8af472777dba75 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 718c79b..88a7f17 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 718c79bb0713b5b90c9cc44e03197dc777066e3d +Subproject commit 88a7f17b7d7a4f8a4d25ef6b87c71236b0862f5d diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index 637f2a4..aab715f 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit 637f2a4f21ead8ccc45d5256834eb27ce72088db +Subproject commit aab715f166bf1b54cfbd6982e8df49248ea544d8 diff --git a/3rdparty/vboot b/3rdparty/vboot index 392211f..adfafba 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 392211f0358919d510179ad399d8f056180e652e +Subproject commit adfafba793684ed92965dfbd86b3fb3463975d8c diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 09b7ef9..17bd3c0 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -305,7 +305,7 @@ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "0" - register "reg_prox_ctrl0" = "0x1a" + register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" register "reg_prox_ctrl3" = "0x0e" @@ -346,7 +346,7 @@ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "1" - register "reg_prox_ctrl0" = "0x1a" + register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" register "reg_prox_ctrl3" = "0x0e" diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage index 64045f9..efe19b2 160000 --- a/util/nvidia/cbootimage +++ b/util/nvidia/cbootimage @@ -1 +1 @@ -Subproject commit 64045f993c2cd8989838aeaad3d22107d96d5596 +Subproject commit efe19b2eb9db7bb3ba913f0af7d5ececb173fe82 -- To view, visit https://review.coreboot.org/27265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Gerrit-Change-Number: 27265 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org>

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Change in coreboot[master]: nocturne: Fix casing for register definition
by Gwendal Grignou (Code Review) 28 Jun '18

28 Jun '18

Gwendal Grignou has uploaded this change for review. ( https://review.coreboot.org/27264 Change subject: nocturne: Fix casing for register definition ...................................................................... nocturne: Fix casing for register definition Use lower case for hex values. BUG=b:74363445 TEST=compile Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27264/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 91c0b44..09b7ef9 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -305,15 +305,15 @@ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "0" - register "reg_prox_ctrl0" = "0x1A" + register "reg_prox_ctrl0" = "0x1a" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0E" + register "reg_prox_ctrl3" = "0x0e" register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xC6" + register "reg_prox_ctrl5" = "0xc6" register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0D" - register "reg_prox_ctrl8" = "0x8D" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" register "reg_prox_ctrl9" = "0x43" register "reg_prox_ctrl10" = "0x11" register "reg_prox_ctrl11" = "0x00" @@ -326,8 +326,8 @@ register "reg_prox_ctrl18" = "0x00" register "reg_prox_ctrl19" = "0x00" register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8A" - register "reg_sar_ctrl2" = "0x3C" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end end # I2C #1 @@ -346,15 +346,15 @@ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "1" - register "reg_prox_ctrl0" = "0x1A" + register "reg_prox_ctrl0" = "0x1a" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0E" + register "reg_prox_ctrl3" = "0x0e" register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xC6" + register "reg_prox_ctrl5" = "0xc6" register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0D" - register "reg_prox_ctrl8" = "0x8D" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" register "reg_prox_ctrl9" = "0x43" register "reg_prox_ctrl10" = "0x11" register "reg_prox_ctrl11" = "0x00" @@ -367,8 +367,8 @@ register "reg_prox_ctrl18" = "0x00" register "reg_prox_ctrl19" = "0x00" register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8A" - register "reg_sar_ctrl2" = "0x3C" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" device i2c 28 on end end end # I2C #5 -- To view, visit https://review.coreboot.org/27264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Gerrit-Change-Number: 27264 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org>

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Change in coreboot[master]: smmstore: Add a key/val store facility in flash, mediated through SMM
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

1 0

Change in coreboot[master]: smmstore: Add a key/val store facility in flash, mediated through SMM
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25182 ) Change subject: smmstore: Add a key/val store facility in flash, mediated through SMM ...................................................................... Patch Set 7: (5 comments) https://review.coreboot.org/#/c/25182/7/src/drivers/smmstore/store.c File src/drivers/smmstore/store.c: https://review.coreboot.org/#/c/25182/7/src/drivers/smmstore/store.c@185 PS7, Line 185: if (rdev_writeat(&store, &key_sz, end, 4) != 4) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/7/src/drivers/smmstore/store.c@189 PS7, Line 189: if (rdev_writeat(&store, &value_sz, end, 4) != 4) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/7/src/drivers/smmstore/store.c@193 PS7, Line 193: if (rdev_writeat(&store, key, end, key_sz) != key_sz) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/7/src/drivers/smmstore/store.c@197 PS7, Line 197: if (rdev_writeat(&store, value, end, value_sz) != value_sz) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/7/src/drivers/smmstore/store.c@202 PS7, Line 202: if (rdev_writeat(&store, &nul, end, 1) != 1) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/25182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5 Gerrit-Change-Number: 25182 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 16:59:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arch/x86: add SMM caller
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25193 ) Change subject: arch/x86: add SMM caller ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29531/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75487/ : SUCCESS -- To view, visit https://review.coreboot.org/25193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a9cc626dae9a7751034615ef409eebc6035f5c3 Gerrit-Change-Number: 25193 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 16:59:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: smmstore: Add a key/val store facility in flash, mediated through SMM
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

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coreboot-gerrit June 2018