coreboot-gerrit June 2018

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Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by Matt DeVillier (Code Review) 28 Jun '18

28 Jun '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27269 Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... arch/x86/acpi: Add DMAR RMRR helper functions Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/skylake/acpi.c 6 files changed, 60 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27269/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8b6b2c1..60d2879 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -449,7 +449,7 @@ } unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u32 bar) + u16 segment, u64 bar) { dmar_entry_t *drhd = (dmar_entry_t *)current; memset(drhd, 0, sizeof(*drhd)); @@ -462,6 +462,20 @@ return drhd->length; } +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, + u64 bar, u64 limit) +{ + dmar_rmrr_entry_t *rmrr = (dmar_rmrr_entry_t *)current; + memset(rmrr, 0, sizeof(*rmrr)); + rmrr->type = DMAR_RMRR; + rmrr->length = sizeof(*rmrr); /* will be fixed up later */ + rmrr->segment = segment; + rmrr->bar = bar; + rmrr->limit = limit; + + return rmrr->length; +} + unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment) { @@ -481,13 +495,19 @@ drhd->length = current - base; } +void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current) +{ + dmar_rmrr_entry_t *rmrr = (dmar_rmrr_entry_t *)base; + rmrr->length = current - base; +} + void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current) { dmar_atsr_entry_t *atsr = (dmar_atsr_entry_t *)base; atsr->length = current - base; } -static unsigned long acpi_create_dmar_drhd_ds(unsigned long current, +static unsigned long acpi_create_dmar_ds(unsigned long current, enum dev_scope_type type, u8 enumeration_id, u8 bus, u8 dev, u8 fn) { /* we don't support longer paths yet */ @@ -505,31 +525,31 @@ return ds->length; } -unsigned long acpi_create_dmar_drhd_ds_pci_br(unsigned long current, u8 bus, +unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_drhd_ds(current, + return acpi_create_dmar_ds(current, SCOPE_PCI_SUB, 0, bus, dev, fn); } -unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 bus, +unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_drhd_ds(current, + return acpi_create_dmar_ds(current, SCOPE_PCI_ENDPOINT, 0, bus, dev, fn); } -unsigned long acpi_create_dmar_drhd_ds_ioapic(unsigned long current, +unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_drhd_ds(current, + return acpi_create_dmar_ds(current, SCOPE_IOAPIC, enumeration_id, bus, dev, fn); } -unsigned long acpi_create_dmar_drhd_ds_msi_hpet(unsigned long current, +unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_drhd_ds(current, + return acpi_create_dmar_ds(current, SCOPE_MSI_HPET, enumeration_id, bus, dev, fn); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f5e2e81..1811965 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -331,6 +331,15 @@ u64 bar; } __packed dmar_entry_t; +typedef struct dmar_rmrr_entry { + u16 type; + u16 length; + u16 reserved; + u16 segment; + u64 bar; + u64 limit; +} __packed dmar_rmrr_entry_t; + typedef struct dmar_atsr_entry { u16 type; u16 length; @@ -738,19 +747,22 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u32 bar); + u16 segment, u64 bar); +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, + u64 bar, u64 limit); unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); +void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current); void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current); -unsigned long acpi_create_dmar_drhd_ds_pci_br(unsigned long current, +unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, +unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_drhd_ds_ioapic(unsigned long current, +unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn); -unsigned long acpi_create_dmar_drhd_ds_msi_hpet(unsigned long current, +unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn); void acpi_write_hest(acpi_hest_t *hest, diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 292219f..b3ceed9 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -85,7 +85,7 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); - current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } @@ -95,11 +95,11 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_drhd_ds_ioapic(current, + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_drhd_ds_msi_hpet(current, + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 91ecac5..88ac2b1 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -74,19 +74,19 @@ if (igfx && igfx->enabled) { const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); - current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); - current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); } const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); - current += acpi_create_dmar_drhd_ds_ioapic(current, + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_drhd_ds_msi_hpet(current, + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 36d3e58..af8e012 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -586,7 +586,7 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); - current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } @@ -596,11 +596,11 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_drhd_ds_ioapic(current, + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_drhd_ds_msi_hpet(current, + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 2c3df09..4ad4831 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -557,7 +557,7 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); - current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } @@ -582,9 +582,9 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_drhd_ds_ioapic(current, + current += acpi_create_dmar_ds_ioapic(current, 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); - current += acpi_create_dmar_drhd_ds_msi_hpet(current, + current += acpi_create_dmar_ds_msi_hpet(current, 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); acpi_dmar_drhd_fixup(tmp, current); -- To view, visit https://review.coreboot.org/27269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Gerrit-Change-Number: 27269 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: Documentation/soc/intel: Add common code design document
by Philipp Deppenwiese (Code Review) 28 Jun '18

28 Jun '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27087 ) Change subject: Documentation/soc/intel: Add common code design document ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/27087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Gerrit-Change-Number: 27087 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 23:10:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25514 ) Change subject: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29551/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75509/ : SUCCESS -- To view, visit https://review.coreboot.org/25514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d Gerrit-Change-Number: 25514 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 22:43:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: coreboot_tables: pass the early_mmc_wake_hw status to payload
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25464 ) Change subject: coreboot_tables: pass the early_mmc_wake_hw status to payload ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29550/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75508/ : SUCCESS -- To view, visit https://review.coreboot.org/25464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Gerrit-Change-Number: 25464 Gerrit-PatchSet: 12 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 22:39:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: stoneyridge: Enable IO CF9 in bootblock
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27267 ) Change subject: stoneyridge: Enable IO CF9 in bootblock ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29548/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75506/ : SUCCESS -- To view, visit https://review.coreboot.org/27267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Gerrit-Change-Number: 27267 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 22:37:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable legacy IO
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27268 ) Change subject: stoneyridge: Enable legacy IO ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29549/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75507/ : SUCCESS -- To view, visit https://review.coreboot.org/27268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Gerrit-Change-Number: 27268 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 22:35:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: stoneyridge: Enable legacy IO
by Raul Rangel (Code Review) 28 Jun '18

28 Jun '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/27268 Change subject: stoneyridge: Enable legacy IO ...................................................................... stoneyridge: Enable legacy IO Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27268/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9f8a7d2..3127f5c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -34,6 +34,7 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 #define CF9_IO_EN BIT(1) +#define LEGACY_IO_EN BIT(0) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 591a8f7..18e6c6c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -375,6 +375,13 @@ pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); } +static void sb_enable_legacy_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -550,6 +557,7 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); sb_enable_cf9_io(); + sb_enable_legacy_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/27268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Gerrit-Change-Number: 27268 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: stoneyridge: Enable IO CF9 in bootblock
by Raul Rangel (Code Review) 28 Jun '18

28 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27267 to look at the new patch set (#2). Change subject: stoneyridge: Enable IO CF9 in bootblock ...................................................................... stoneyridge: Enable IO CF9 in bootblock If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27267/2 -- To view, visit https://review.coreboot.org/27267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Gerrit-Change-Number: 27267 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25514 ) Change subject: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29547/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75504/ : SUCCESS -- To view, visit https://review.coreboot.org/25514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d Gerrit-Change-Number: 25514 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 21:32:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: coreboot_tables: pass the early_mmc_wake_hw status to payload
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25464 ) Change subject: coreboot_tables: pass the early_mmc_wake_hw status to payload ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29546/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75505/ : SUCCESS -- To view, visit https://review.coreboot.org/25464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Gerrit-Change-Number: 25464 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Jun 2018 21:29:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018