coreboot-gerrit June 2018

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Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27269 ) Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29558/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75516/ : SUCCESS -- To view, visit https://review.coreboot.org/27269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Gerrit-Change-Number: 27269 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 03:21:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Generate ACPI RMRR table
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27270 ) Change subject: soc/intel/skylake: Generate ACPI RMRR table ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29559/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75517/ : SUCCESS -- To view, visit https://review.coreboot.org/27270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Gerrit-Change-Number: 27270 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 03:11:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by Matt DeVillier (Code Review) 29 Jun '18

29 Jun '18

Hello Youness Alaoui, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27269 to look at the new patch set (#2). Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... arch/x86/acpi: Add DMAR RMRR helper functions Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/skylake/acpi.c 8 files changed, 71 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27269/2 -- To view, visit https://review.coreboot.org/27269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Gerrit-Change-Number: 27269 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Generate ACPI RMRR table
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27270 ) Change subject: soc/intel/skylake: Generate ACPI RMRR table ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/75515/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/29557/ : SUCCESS -- To view, visit https://review.coreboot.org/27270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Gerrit-Change-Number: 27270 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 01:29:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/acpi: Add DMAR RMRR helper functions
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27269 ) Change subject: arch/x86/acpi: Add DMAR RMRR helper functions ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/75514/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/29556/ : SUCCESS -- To view, visit https://review.coreboot.org/27269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Gerrit-Change-Number: 27269 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 01:17:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25514 ) Change subject: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK ...................................................................... Patch Set 12: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29555/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75513/ : SUCCESS -- To view, visit https://review.coreboot.org/25514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d Gerrit-Change-Number: 25514 Gerrit-PatchSet: 12 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 01:14:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: intel/common/block/scs: Add ability to send early CMD0, CMD1
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25068 ) Change subject: intel/common/block/scs: Add ability to send early CMD0, CMD1 ...................................................................... Patch Set 12: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29554/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75512/ : SUCCESS -- To view, visit https://review.coreboot.org/25068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e Gerrit-Change-Number: 25068 Gerrit-PatchSet: 12 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 01:11:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: coreboot_tables: pass the early_mmc_wake_hw status to payload
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25464 ) Change subject: coreboot_tables: pass the early_mmc_wake_hw status to payload ...................................................................... Patch Set 13: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29553/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75511/ : SUCCESS -- To view, visit https://review.coreboot.org/25464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Gerrit-Change-Number: 25464 Gerrit-PatchSet: 13 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 01:08:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: commonlib/storage: Make pci sdhci code compile in romstage
by build bot (Jenkins) (Code Review) 28 Jun '18

28 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25067 ) Change subject: commonlib/storage: Make pci sdhci code compile in romstage ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29552/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75510/ : SUCCESS -- To view, visit https://review.coreboot.org/25067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc Gerrit-Change-Number: 25067 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 29 Jun 2018 01:06:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Generate ACPI RMRR table
by Matt DeVillier (Code Review) 28 Jun '18

28 Jun '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27270 Change subject: soc/intel/skylake: Generate ACPI RMRR table ...................................................................... soc/intel/skylake: Generate ACPI RMRR table An ACPI RMRR table is requried for IOMMU to work properly with an iGPU (without using passthrough mode), so create one along with the DRHD DMAR table if the iGPU is present and enabled. Test: build/boot google/chell and purism/librem13v2 with kernel parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated graphics functional without corruption. Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/systemagent.c 3 files changed, 72 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27270/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 4ad4831..e0516ab 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -551,15 +551,34 @@ const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; + const u32 tolud_addr = sa_get_tolud_addr(); + const u32 igd_rmrr_base = tolud_addr - + (sa_get_igd_mem_sz() + sa_get_gtt_mem_sz()); + const u32 igd_rmrr_limit = tolud_addr - 1; + /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ if (igfx_dev && igfx_dev->enabled && gfxvten && gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { - const unsigned long tmp = current; + unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); + + /* + * Add RMRR entry + * Address calculations taken from edk2 reference implementation + */ + if (tolud_addr > 0) { + tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + igd_rmrr_base, igd_rmrr_limit); + current += acpi_create_dmar_ds_pci(current, 0, + SA_DEV_SLOT_IGD, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } } struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 8e53f54..9724b03 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -25,6 +25,12 @@ /* Device 0:0.0 PCI configuration space */ #define EPBAR 0x40 +#define GGC_REG 0x50 +#define GGC_GMS_MASK 0xff00 +#define GGC_GMS_OFST 0x08 +#define GGC_GGMS_MASK 0xc0 +#define GGC_GGMS_OFST 0x06 +#define GGC_GGMS_8MB 0x03 #define DMIBAR 0x68 #define SMRAM 0x88 /* System Management RAM Control */ #define D_OPEN (1 << 6) @@ -47,6 +53,9 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 bool soc_is_vtd_capable(void); +u32 sa_get_tolud_addr(void); +u32 sa_get_igd_mem_sz(void); +u32 sa_get_gtt_mem_sz(void); static const struct sa_mmio_descriptor soc_vtd_resources[] = { { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 2c4408fe..3911e80 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -36,6 +36,49 @@ !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); } +u32 sa_get_tolud_addr(void) +{ + struct device *const root_dev = SA_DEV_ROOT; + + return root_dev ? pci_read_config32(root_dev, TOLUD) & ~(0x01) : 0x0; +} + +u32 sa_get_igd_mem_sz(void) +{ + struct device *const root_dev = SA_DEV_ROOT; + u16 igd_mode; + u32 igd_mem_sz; + + if (!root_dev) + return 0x0; + + igd_mode = (pci_read_config16(root_dev, GGC_REG) & GGC_GMS_MASK) + >> GGC_GMS_OFST; + if (igd_mode < 0xF0) + igd_mem_sz = igd_mode * 32 * (1024) * (1024); + else + igd_mem_sz = 4 * (igd_mode - 0xF0 + 1) * (1024) * (1024); + + return igd_mem_sz; +} + +u32 sa_get_gtt_mem_sz(void) +{ + struct device *const root_dev = SA_DEV_ROOT; + u16 gtt_mode; + u32 gtt_mem_sz = 0; + + if (!root_dev) + return 0x0; + + gtt_mode = (pci_read_config16(root_dev, GGC_REG) & GGC_GGMS_MASK) + >> GGC_GGMS_OFST; + if (gtt_mode <= GGC_GGMS_8MB) + gtt_mem_sz = (1 << gtt_mode) * (1024) * (1024); + + return gtt_mem_sz; +} + /* * SoC implementation * -- To view, visit https://review.coreboot.org/27270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Gerrit-Change-Number: 27270 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit June 2018