coreboot-gerrit June 2018

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Change in coreboot[master]: mb/google/link: Use new PMBASE API
by Patrick Rudolph (Code Review) 29 Jun '18

29 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27284 Change subject: mb/google/link: Use new PMBASE API ...................................................................... mb/google/link: Use new PMBASE API Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/link/mainboard_smi.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27284/1 diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 0babb54..0bd164e 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -20,6 +20,7 @@ #include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> +#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> @@ -31,7 +32,6 @@ static u8 mainboard_smi_ec(void) { u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; #if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log this event */ @@ -44,9 +44,7 @@ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); break; } -- To view, visit https://review.coreboot.org/27284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd Gerrit-Change-Number: 27284 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/google/parrot: Use new common SMBASE API
by Patrick Rudolph (Code Review) 29 Jun '18

29 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27282 Change subject: mb/google/parrot: Use new common SMBASE API ...................................................................... mb/google/parrot: Use new common SMBASE API Change-Id: Iee3a7cc3808ad7ec26464e54bf6144b70f426aa6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/parrot/smihandler.c 1 file changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/27282/1 diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 7681065..e30f78f 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -20,6 +20,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> @@ -29,7 +30,6 @@ static u8 mainboard_smi_ec(void) { u8 src; - u32 pm1_cnt; #if IS_ENABLED(CONFIG_ELOG_GSMI) static int battery_critical_logged; #endif @@ -54,9 +54,7 @@ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); break; } @@ -65,8 +63,6 @@ void mainboard_smi_gpi(u32 gpi_sts) { - u32 pm1_cnt; - printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ @@ -79,9 +75,7 @@ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } } -- To view, visit https://review.coreboot.org/27282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee3a7cc3808ad7ec26464e54bf6144b70f426aa6 Gerrit-Change-Number: 27282 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: sb/intel/lynxpoint: Use new common PMBASE API
by Patrick Rudolph (Code Review) 29 Jun '18

29 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27280 Change subject: sb/intel/lynxpoint: Use new common PMBASE API ...................................................................... sb/intel/lynxpoint: Use new common PMBASE API Change-Id: I4e62846d34af3d81d9b787a313caa6dabb275bcf Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/lynxpoint/early_pch.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/27280/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index cb4bc7e..37b7830 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -64,7 +64,7 @@ { printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + write_pmbase16(0x68, 1 << 11); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); } @@ -84,13 +84,13 @@ int is_s3 = 0; /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + pm1_sts = read_pmbase16(PM1_STS); if (pm1_sts & WAK_STS) { /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + pm1_cnt = read_pmbase32(PM1_CNT); if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { /* Clear SLP_TYPE. */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); is_s3 = 1; } } -- To view, visit https://review.coreboot.org/27280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e62846d34af3d81d9b787a313caa6dabb275bcf Gerrit-Change-Number: 27280 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: sb/intel/common/smihandler: Use new PMBASE API
by Patrick Rudolph (Code Review) 29 Jun '18

29 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27281 Change subject: sb/intel/common/smihandler: Use new PMBASE API ...................................................................... sb/intel/common/smihandler: Use new PMBASE API Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/common/smihandler.c 1 file changed, 15 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27281/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index a5ebf25..5cdc992 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -30,8 +30,6 @@ static int smm_initialized = 0; -static u16 pmbase; - void gpi_route_interrupt(u8 gpi, u8 mode) { u32 gpi_rout; @@ -57,11 +55,7 @@ */ void southbridge_smi_set_eos(void) { - u8 reg8; - - reg8 = inb(pmbase + SMI_EN); - reg8 |= EOS; - outb(reg8, pmbase + SMI_EN); + write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) | EOS); } static void busmaster_disable_on_bus(int bus) @@ -124,12 +118,10 @@ outb(tmp72, 0x72); /* First, disable further SMIs */ - reg8 = inb(pmbase + SMI_EN); - reg8 &= ~SLP_SMI_EN; - outb(reg8, pmbase + SMI_EN); + write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = read_pmbase32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -169,7 +161,7 @@ case ACPI_S5: printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); - outl(0, pmbase + GPE0_EN); + write_pmbase32(GPE0_EN, 0); /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated @@ -192,7 +184,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - outl(reg32 | SLP_EN, pmbase + PM1_CNT); + write_pmbase32(PM1_CNT, reg32 | SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ >= ACPI_S3) @@ -202,11 +194,11 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(pmbase + PM1_CNT); + reg32 = read_pmbase32(PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ reg32 &= ~(SLP_EN | SLP_TYP); - outl(reg32, pmbase + PM1_CNT); + write_pmbase32(PM1_CNT, reg32); } } @@ -273,7 +265,6 @@ static void southbridge_smi_apmc(void) { - u32 pmctrl; u8 reg8; /* Emulate B2 register as the FADT / Linux expects it */ @@ -295,15 +286,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl &= ~SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) &~SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - pmctrl = inl(pmbase + PM1_CNT); - pmctrl |= SCI_EN; - outl(pmctrl, pmbase + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_GNVS_UPDATE: @@ -350,7 +337,7 @@ #if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif - outl(reg32, pmbase + PM1_CNT); + write_pmbase32(PM1_CNT, reg32); } } @@ -365,24 +352,23 @@ static void southbridge_smi_gpi(void) { u16 reg16; - reg16 = inw(pmbase + ALT_GP_SMI_STS); - outw(reg16, pmbase + ALT_GP_SMI_STS); - reg16 &= inw(pmbase + ALT_GP_SMI_EN); + reg16 = reset_alt_gp_smi_status(); + reg16 &= read_pmbase16(ALT_GP_SMI_EN); mainboard_smi_gpi(reg16); if (reg16) printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); - outw(reg16, pmbase + ALT_GP_SMI_STS); + write_pmbase16(ALT_GP_SMI_STS, reg16); } static void southbridge_smi_mc(void) { u32 reg32; - reg32 = inl(pmbase + SMI_EN); + reg32 = read_pmbase32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) @@ -435,7 +421,7 @@ { u32 reg32; - reg32 = inl(pmbase + SMI_EN); + reg32 = read_pmbase32(SMI_EN); /* Are periodic SMIs enabled? */ if ((reg32 & PERIODIC_EN) == 0) @@ -491,9 +477,6 @@ int i, dump = 0; u32 smi_sts; - /* Update global variable pmbase */ - pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ -- To view, visit https://review.coreboot.org/27281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Gerrit-Change-Number: 27281 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: intel: Get rid of smm_get_pmbase
by Patrick Rudolph (Code Review) 29 Jun '18

29 Jun '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27279 Change subject: intel: Get rid of smm_get_pmbase ...................................................................... intel: Get rid of smm_get_pmbase Change-Id: I2b3168c600a81502f9cd1ff3203c492cf026e532 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/cpu/x86/smm.h M src/mainboard/google/stout/ec.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 6 files changed, 2 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/27279/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7dcf4d7..35977a7 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -508,9 +508,6 @@ extern unsigned char _binary_smm_start[]; extern unsigned char _binary_smm_end[]; -/* Get PMBASE address */ -u16 smm_get_pmbase(void); - struct smm_runtime { u32 smbase; u32 save_state_size; diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index a459d0c..229f919 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmbase.h> #include <elog.h> #include "ec.h" @@ -64,7 +65,6 @@ void stout_ec_finalize_smm(void) { u8 ec_reg, critical_shutdown = 0; - u32 pm1_cnt; /* * Check EC for error conditions. @@ -115,9 +115,7 @@ printk(BIOS_ERR, "EC critical_shutdown"); /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } } #endif //__SMM__ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 234a1c5..a5ebf25 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -32,12 +32,6 @@ static u16 pmbase; -/* Defined in <cpu/x86/smm.h> which is used outside of common code*/ -u16 smm_get_pmbase(void) -{ - return get_pmbase(); -} - void gpi_route_interrupt(u8 gpi, u8 mode) { u32 gpi_rout; diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index c868ec6..7eb108a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -33,15 +33,6 @@ */ #include <northbridge/intel/fsp_sandybridge/northbridge.h> -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; -u16 smm_get_pmbase(void) -{ - return pmbase; -} - static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 0ef7ba8..870e442 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -33,15 +33,6 @@ */ #include <northbridge/intel/fsp_sandybridge/northbridge.h> -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; -u16 smm_get_pmbase(void) -{ - return pmbase; -} - static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 12a7ac0..eb72e6b 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -36,15 +36,6 @@ #include <southbridge/intel/common/gpio.h> #include <arch/io.h> -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; -u16 smm_get_pmbase(void) -{ - return pmbase; -} - static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located -- To view, visit https://review.coreboot.org/27279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b3168c600a81502f9cd1ff3203c492cf026e532 Gerrit-Change-Number: 27279 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: sb/intel/common: Add functions to manipulate PMBASE
by Patrick Rudolph (Code Review) 29 Jun '18

29 Jun '18

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/27278 to review the following change. Change subject: sb/intel/common: Add functions to manipulate PMBASE ...................................................................... sb/intel/common: Add functions to manipulate PMBASE Get rid of duplicated get_pmbase and use the new common function. TODO: Use the new functions to manipulate register in PMBASE. Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/pmbase.c A src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c 10 files changed, 112 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/27278/1 diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index bf3a86e..961b71b 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -18,6 +18,11 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) +romstage-y += pmbase.c +ramstage-y += pmbase.c +postcar-y += pmbase.c +smm-y += pmbase.c + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c new file mode 100644 index 0000000..ecdd1c5 --- /dev/null +++ b/src/southbridge/intel/common/pmbase.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/early_variables.h> + +#include "pmbase.h" + +/* LPC PM Base Address Register */ +#define PMBASE 0x40 + +/* PCI Configuration Space (D31:F0): LPC */ +#if defined(__SIMPLE_DEVICE__) +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#else +#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#endif + +u16 get_pmbase(void) +{ +#if defined(__SMM__) + /* Don't assume PMBASE is still the same */ + return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; +#else + static u16 pmbase CAR_GLOBAL; + + if (pmbase) + return pmbase; + + pmbase = pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc; + + return pmbase; +#endif +} + +void write_pmbase32(const u16 addr, const u32 val) +{ + outl(val, get_pmbase() | addr); +} + +void write_pmbase16(const u16 addr, const u16 val) +{ + outw(val, get_pmbase() | addr); +} + +void write_pmbase8(const u16 addr, const u8 val) +{ + outb(val, get_pmbase() | addr); +} + +u32 read_pmbase32(const u16 addr) +{ + return inl(get_pmbase() | addr); +} + +u16 read_pmbase16(const u16 addr) +{ + return inw(get_pmbase() | addr); +} + +u8 read_pmbase8(const u16 addr) +{ + return inb(get_pmbase() | addr); +} diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h new file mode 100644 index 0000000..27ad68a --- /dev/null +++ b/src/southbridge/intel/common/pmbase.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +u16 get_pmbase(void); + +void write_pmbase32(const u16 addr, const u32 val); +void write_pmbase16(const u16 addr, const u16 val); +void write_pmbase8(const u16 addr, const u8 val); + +u32 read_pmbase32(const u16 addr); +u16 read_pmbase16(const u16 addr); +u8 read_pmbase8(const u16 addr); diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 97df201..03ae473 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -22,7 +22,7 @@ #include <cpu/x86/smm.h> #include <elog.h> #include <pc80/mc146818rtc.h> - +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> #include "pmutil.h" diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index e2b6e58..9393ef4 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -101,8 +101,6 @@ #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a -u16 get_pmbase(void); - u16 reset_pm1_status(void); void dump_pm1_status(u16 pm1_sts); void dump_tco_status(u32 tco_sts); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index deaecb2..eaae8f2 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -23,18 +23,13 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/intel/smm/gen1/smi.h> - +#include "pmbase.h" #include "pmutil.h" #define DEBUG_PERIODIC_SMIS 0 static u16 pmbase; -u16 get_pmbase(void) -{ - return pmbase; -} - void southbridge_smm_init(void) { u32 smi_en; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 65a1b96..234a1c5 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -26,16 +26,12 @@ #include <halt.h> #include <pc80/mc146818rtc.h> #include "pmutil.h" +#include "pmbase.h" static int smm_initialized = 0; static u16 pmbase; -u16 get_pmbase(void) -{ - return pmbase; -} - /* Defined in <cpu/x86/smm.h> which is used outside of common code*/ u16 smm_get_pmbase(void) { diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 1a390cc..762347e 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -57,16 +57,6 @@ return pch_silicon_type() == PCH_TYPE_LPT_LP; } -u16 get_pmbase(void) -{ - static u16 pmbase; - - if (!pmbase) - pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; - return pmbase; -} - u16 get_gpiobase(void) { static u16 gpiobase; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ae996e8..f38c1dc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -144,7 +144,6 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_is_lp(void); -u16 get_pmbase(void); u16 get_gpiobase(void); /* Power Management register handling in pmutil.c */ diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index e96d683..30ef9aa 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <security/vboot/vbnv.h> +#include <common/pmbase.h> #include "pch.h" #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) -- To view, visit https://review.coreboot.org/27278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Gerrit-Change-Number: 27278 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27275 ) Change subject: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75531/ : SUCCESS -- To view, visit https://review.coreboot.org/27275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Gerrit-Change-Number: 27275 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 08:11:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion
by build bot (Jenkins) (Code Review) 29 Jun '18

29 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27140 ) Change subject: soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75528/ : SUCCESS -- To view, visit https://review.coreboot.org/27140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e Gerrit-Change-Number: 27140 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 08:05:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD
by TH Lin (Code Review) 29 Jun '18

29 Jun '18

TH Lin has posted comments on this change. ( https://review.coreboot.org/27275 ) Change subject: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/27275/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27275/1//COMMIT_MSG@6 PS1, Line 6: : mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SP > mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD Update https://review.coreboot.org/#/c/27275/1//COMMIT_MSG@11 PS1, Line 11: . > , Thanks. https://review.coreboot.org/#/c/27275/1//COMMIT_MSG@12 PS1, Line 12: nami > nami Thanks. -- To view, visit https://review.coreboot.org/27275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Gerrit-Change-Number: 27275 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Jun 2018 07:58:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD
by TH Lin (Code Review) 29 Jun '18

29 Jun '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27275 to look at the new patch set (#2). Change subject: mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD ...................................................................... mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPD nayna/NT6CL256T32CM-H1 file change byte 145/146 to be"20" for JEDEC spec BUG=b:79443146.b:109708239 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test on R69.10825 with mosys Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Signed-off-by: T.H. Lin <t.h_lin(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/spd/nayna_dimm_NT6CL256T32CM-H1.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27275/2 -- To view, visit https://review.coreboot.org/27275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Gerrit-Change-Number: 27275 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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