coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

1 participants
2751 discussions

Change in coreboot[master]: src: Remove unneeded whitespace
by Elyes HAOUAS (Code Review) 09 Jun '18

09 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26991 to look at the new patch set (#5). Change subject: src: Remove unneeded whitespace ...................................................................... src: Remove unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/RFC/config.tex M src/drivers/intel/fsp2_0/hand_off_block.c M src/include/bootstate.h M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/torpedo/devicetree.cb M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/acpi/thermal.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3gtopo.h M src/northbridge/amd/amdmct/amddefs.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctecc_d.c M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/intel/e7505/e7505.h M src/soc/amd/common/block/pi/def_callouts.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/cs5536.h M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/pcie.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl M src/southbridge/intel/fsp_bd82x6x/me.h M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/acpi/pch.asl M src/southbridge/intel/fsp_i89xx/me.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/acpi/soc.asl M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/via/common/early_smbus_print_error.c M util/autoport/readme.md M util/crossgcc/buildgcc M util/intelmetool/me.h M util/romcc/romcc.c M util/vgabios/device.c M util/vgabios/testbios.c 81 files changed, 397 insertions(+), 397 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/26991/5 -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26942 ) Change subject: src: Use "foo *bar" instead of "foo* bar" ...................................................................... Patch Set 9: (37 comments) https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h File src/device/oprom/yabel/compat/of.h: https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 38: #define p32cast (int) (unsigned long) (void *) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 53: phandle_t of_peer(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 54: phandle_t of_child(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 55: phandle_t of_parent(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 60: ihandle_t of_open(const char *); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 67: void of_release(void *, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 67: void of_release(void *, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 70: void *of_set_callback(void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/device/oprom/yabel/compat/of.h@… PS9, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned short' should also have an identifier name https://review.coreboot.org/#/c/26942/9/src/northbridge/amd/amdht/ht_wrappe… File src/northbridge/amd/amdht/ht_wrapper.c: https://review.coreboot.org/#/c/26942/9/src/northbridge/amd/amdht/ht_wrappe… PS9, Line 58: static const char *event_class_string_decodes[] = { static const char * array should probably be static const char * const -- To view, visit https://review.coreboot.org/26942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Gerrit-Change-Number: 26942 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 11:07:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 4: (23 comments) https://review.coreboot.org/#/c/26991/4/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/4/src/include/bootstate.h@127 PS4, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/agesa/family14/… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/agesa/family14/… PS4, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdht/h3gtopo.h… PS4, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/amddefs.h File src/northbridge/amd/amdmct/amddefs.h: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/amddefs.… PS4, Line 77: #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) please, no space before tabs https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct/mct_… File src/northbridge/amd/amdmct/mct/mct_d.c: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct/mct_… PS4, Line 3756: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct/mctd… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct/mctd… PS4, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… PS4, Line 7912: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… PS4, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… PS4, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/amdmct/mct_ddr3… PS4, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/lx/northbridgei… File src/northbridge/amd/lx/northbridgeinit.c: https://review.coreboot.org/#/c/26991/4/src/northbridge/amd/lx/northbridgei… PS4, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb800/late… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb800/late… PS4, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb800/late… PS4, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb800/late… PS4, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb800/late… PS4, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb900/late… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb900/late… PS4, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb900/late… PS4, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/cimx/sb900/late… PS4, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/rs780/gfx.c@452 PS4, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/rs780/rs780.c@96 PS4, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/4/src/southbridge/amd/sr5650/cmn.h@23 PS4, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters https://review.coreboot.org/#/c/26991/4/util/vgabios/device.c File util/vgabios/device.c: https://review.coreboot.org/#/c/26991/4/util/vgabios/device.c@83 PS4, Line 83: DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__); line over 80 characters https://review.coreboot.org/#/c/26991/4/util/vgabios/testbios.c File util/vgabios/testbios.c: https://review.coreboot.org/#/c/26991/4/util/vgabios/testbios.c@119 PS4, Line 119: ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ...\n", line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 11:00:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/431/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/74686/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/28796/ : SUCCESS -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 11:00:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by Elyes HAOUAS (Code Review) 09 Jun '18

09 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26991 to look at the new patch set (#4). Change subject: src: Remove unneeded whitespace ...................................................................... src: Remove unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/RFC/config.tex M src/drivers/intel/fsp2_0/hand_off_block.c M src/include/bootstate.h M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/torpedo/devicetree.cb M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/acpi/thermal.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3gtopo.h M src/northbridge/amd/amdmct/amddefs.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctecc_d.c M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/intel/e7505/e7505.h M src/soc/amd/common/block/pi/def_callouts.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/cs5536.h M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/pcie.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl M src/southbridge/intel/fsp_bd82x6x/me.h M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/acpi/pch.asl M src/southbridge/intel/fsp_i89xx/me.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/acpi/soc.asl M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/via/common/early_smbus_print_error.c M util/autoport/readme.md M util/crossgcc/buildgcc M util/intelmetool/me.h M util/romcc/romcc.c M util/vgabios/device.c M util/vgabios/testbios.c 81 files changed, 397 insertions(+), 397 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/26991/4 -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 3: (23 comments) https://review.coreboot.org/#/c/26991/3/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/3/src/include/bootstate.h@127 PS3, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/agesa/family14/… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/agesa/family14/… PS3, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdht/h3gtopo.h… PS3, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/amddefs.h File src/northbridge/amd/amdmct/amddefs.h: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/amddefs.… PS3, Line 77: #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) please, no space before tabs https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mct_… File src/northbridge/amd/amdmct/mct/mct_d.c: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mct_… PS3, Line 3756: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mctd… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mctd… PS3, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 7912: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/lx/northbridgei… File src/northbridge/amd/lx/northbridgeinit.c: https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/lx/northbridgei… PS3, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late… PS3, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late… PS3, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late… PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late… PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late… PS3, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late… PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late… PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/gfx.c@452 PS3, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/rs780.c@96 PS3, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/sr5650/cmn.h@23 PS3, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters https://review.coreboot.org/#/c/26991/3/util/vgabios/device.c File util/vgabios/device.c: https://review.coreboot.org/#/c/26991/3/util/vgabios/device.c@83 PS3, Line 83: DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__); line over 80 characters https://review.coreboot.org/#/c/26991/3/util/vgabios/testbios.c File util/vgabios/testbios.c: https://review.coreboot.org/#/c/26991/3/util/vgabios/testbios.c@119 PS3, Line 119: ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ...\n", line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 10:58:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/430/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/74685/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28795/ : SUCCESS -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 10:54:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by Elyes HAOUAS (Code Review) 09 Jun '18

09 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26991 to look at the new patch set (#3). Change subject: src: Remove unneeded whitespace ...................................................................... src: Remove unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/RFC/config.tex M src/drivers/intel/fsp2_0/hand_off_block.c M src/include/bootstate.h M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/torpedo/devicetree.cb M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/roda/rk886ex/acpi/thermal.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/amdfam10/resourcemap.c M src/northbridge/amd/amdht/h3gtopo.h M src/northbridge/amd/amdmct/amddefs.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctecc_d.c M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/lx/northbridgeinit.c M src/northbridge/amd/lx/raminit.c M src/northbridge/intel/e7505/e7505.h M src/soc/amd/common/block/pi/def_callouts.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/cs5536/cs5536.c M src/southbridge/amd/cs5536/cs5536.h M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/pcie.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl M src/southbridge/intel/fsp_bd82x6x/me.h M src/southbridge/intel/fsp_bd82x6x/smi.c M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/acpi/pch.asl M src/southbridge/intel/fsp_i89xx/me.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/acpi/soc.asl M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/via/common/early_smbus_print_error.c M util/autoport/readme.md M util/crossgcc/buildgcc M util/romcc/romcc.c M util/vgabios/device.c M util/vgabios/testbios.c 80 files changed, 375 insertions(+), 375 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/26991/3 -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 2: (23 comments) https://review.coreboot.org/#/c/26991/2/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/2/src/include/bootstate.h@127 PS2, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/agesa/family14/… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/agesa/family14/… PS2, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdht/h3gtopo.h… PS2, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/amddefs.h File src/northbridge/amd/amdmct/amddefs.h: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/amddefs.… PS2, Line 77: #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) please, no space before tabs https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct/mct_… File src/northbridge/amd/amdmct/mct/mct_d.c: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct/mct_… PS2, Line 3756: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct/mctd… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct/mctd… PS2, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… PS2, Line 7912: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… PS2, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… PS2, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/amdmct/mct_ddr3… PS2, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/lx/northbridgei… File src/northbridge/amd/lx/northbridgeinit.c: https://review.coreboot.org/#/c/26991/2/src/northbridge/amd/lx/northbridgei… PS2, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb800/late… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb800/late… PS2, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb800/late… PS2, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb800/late… PS2, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb800/late… PS2, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb900/late… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb900/late… PS2, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb900/late… PS2, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/cimx/sb900/late… PS2, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/rs780/gfx.c@452 PS2, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/rs780/rs780.c@96 PS2, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/2/src/southbridge/amd/sr5650/cmn.h@23 PS2, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters https://review.coreboot.org/#/c/26991/2/util/vgabios/device.c File util/vgabios/device.c: https://review.coreboot.org/#/c/26991/2/util/vgabios/device.c@83 PS2, Line 83: DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__); line over 80 characters https://review.coreboot.org/#/c/26991/2/util/vgabios/testbios.c File util/vgabios/testbios.c: https://review.coreboot.org/#/c/26991/2/util/vgabios/testbios.c@119 PS2, Line 119: ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ...\n", line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 10:20:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/429/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/74684/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28794/ : SUCCESS -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 10:20:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2018