coreboot-gerrit June 2018

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Change in coreboot[master]: sb/amd/sr5650: Get rid of device_t
by Elyes HAOUAS (Code Review) 10 Jun '18

10 Jun '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/26992 ) Change subject: sb/amd/sr5650: Get rid of device_t ...................................................................... sb/amd/sr5650: Get rid of device_t Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead in romstage. Change-Id: I669e8fe851a49216cee5593c5125331c0f0c243d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/sr5650/cmn.h M src/southbridge/amd/sr5650/early_setup.c M src/southbridge/amd/sr5650/sr5650.h 3 files changed, 56 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/26992/2 -- To view, visit https://review.coreboot.org/26992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I669e8fe851a49216cee5593c5125331c0f0c243d Gerrit-Change-Number: 26992 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: sb/amd/sr5650: Get rid of device_t
by Elyes HAOUAS (Code Review) 10 Jun '18

10 Jun '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26992 Change subject: sb/amd/sr5650: Get rid of device_t ...................................................................... sb/amd/sr5650: Get rid of device_t Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead in romstage. Change-Id: I669e8fe851a49216cee5593c5125331c0f0c243d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/sr5650/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/26992/1 diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig index 85f6b13..85a082f 100644 --- a/src/southbridge/amd/sr5650/Kconfig +++ b/src/southbridge/amd/sr5650/Kconfig @@ -1,4 +1,4 @@ -## +# ## This file is part of the coreboot project. ## ## Copyright (C) 2010 Advanced Micro Devices, Inc. -- To view, visit https://review.coreboot.org/26992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I669e8fe851a49216cee5593c5125331c0f0c243d Gerrit-Change-Number: 26992 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard: Get rid of device_t in ramstage
by build bot (Jenkins) (Code Review) 10 Jun '18

10 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26983 ) Change subject: mainboard: Get rid of device_t in ramstage ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74692/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28801/ : SUCCESS -- To view, visit https://review.coreboot.org/26983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Gerrit-Change-Number: 26983 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 15:20:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Get rid of device_t in ramstage
by build bot (Jenkins) (Code Review) 10 Jun '18

10 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26983 ) Change subject: mainboard: Get rid of device_t in ramstage ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74691/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/28800/ : SUCCESS -- To view, visit https://review.coreboot.org/26983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Gerrit-Change-Number: 26983 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 15:14:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Get rid of device_t in ramstage
by build bot (Jenkins) (Code Review) 10 Jun '18

10 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26983 ) Change subject: mainboard: Get rid of device_t in ramstage ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/26983/3/src/mainboard/emulation/qemu-i440fx… File src/mainboard/emulation/qemu-i440fx/acpi.h: https://review.coreboot.org/#/c/26983/3/src/mainboard/emulation/qemu-i440fx… PS3, Line 1: unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start); line over 80 characters -- To view, visit https://review.coreboot.org/26983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Gerrit-Change-Number: 26983 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 15:11:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Treat all stages commonly when adding drivers
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26871 ) Change subject: drivers/spi: Treat all stages commonly when adding drivers ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74690/ : SUCCESS -- To view, visit https://review.coreboot.org/26871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756 Gerrit-Change-Number: 26871 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 09 Jun 2018 13:47:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-toolchain/433/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/74689/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28799/ : SUCCESS -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 12:30:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 5: (22 comments) https://review.coreboot.org/#/c/26991/5/src/include/bootstate.h File src/include/bootstate.h: https://review.coreboot.org/#/c/26991/5/src/include/bootstate.h@127 PS5, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/agesa/family14/… File src/northbridge/amd/agesa/family14/chip.h: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/agesa/family14/… PS5, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdht/h3gtopo.h… PS5, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct/mct_… File src/northbridge/amd/amdmct/mct/mct_d.c: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct/mct_… PS5, Line 3756: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct/mctd… File src/northbridge/amd/amdmct/mct/mctdqs_d.c: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct/mctd… PS5, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 7912: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/lx/northbridgei… File src/northbridge/amd/lx/northbridgeinit.c: https://review.coreboot.org/#/c/26991/5/src/northbridge/amd/lx/northbridgei… PS5, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb800/late… File src/southbridge/amd/cimx/sb800/late.c: https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb800/late… PS5, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb800/late… PS5, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb800/late… PS5, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb800/late… PS5, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb900/late… File src/southbridge/amd/cimx/sb900/late.c: https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb900/late… PS5, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb900/late… PS5, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/cimx/sb900/late… PS5, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/rs780/gfx.c@452 PS5, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c: https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/rs780/rs780.c@96 PS5, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h: https://review.coreboot.org/#/c/26991/5/src/southbridge/amd/sr5650/cmn.h@23 PS5, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters https://review.coreboot.org/#/c/26991/5/util/vgabios/device.c File util/vgabios/device.c: https://review.coreboot.org/#/c/26991/5/util/vgabios/device.c@83 PS5, Line 83: DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__); line over 80 characters https://review.coreboot.org/#/c/26991/5/util/vgabios/testbios.c File util/vgabios/testbios.c: https://review.coreboot.org/#/c/26991/5/util/vgabios/testbios.c@119 PS5, Line 119: ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ...\n", line over 80 characters -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 11:18:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/432/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/74687/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28797/ : SUCCESS -- To view, visit https://review.coreboot.org/26991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Gerrit-Change-Number: 26991 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 11:14:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 09 Jun '18

09 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26942 ) Change subject: src: Use "foo *bar" instead of "foo* bar" ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74688/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28798/ : SUCCESS -- To view, visit https://review.coreboot.org/26942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Gerrit-Change-Number: 26942 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Jun 2018 11:14:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit June 2018